singt3.tan.qmsg

来自「在EDA开发软件QuartusII上利用VHDL语言实现DDS信号发生器」· QMSG 代码 · 共 10 行 · 第 1/2 页

{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clk " "Info: Assuming node \"clk\" is an undefined clock" {  } { { "singt3.vhd" "" { Text "E:/EDA/DDS/10k844/SINX/singt3.vhd" 6 -1 0 } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "clk" } } } }  } 0}  } {  } 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register lpm_counter:q_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[4\] register lpm_counter:q_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[6\] 65.36 MHz 15.3 ns Internal " "Info: Clock \"clk\" has Internal fmax of 65.36 MHz between source register \"lpm_counter:q_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[4\]\" and destination register \"lpm_counter:q_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[6\]\" (period= 15.3 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "11.700 ns + Longest register register " "Info: + Longest register to register delay is 11.700 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns lpm_counter:q_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[4\] 1 REG LC5_A14 31 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC5_A14; Fanout = 31; REG Node = 'lpm_counter:q_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[4\]'" {  } { { "E:/EDA/DDS/10k844/SINX/db/singt3_cmp.qrpt" "" { Report "E:/EDA/DDS/10k844/SINX/db/singt3_cmp.qrpt" Compiler "singt3" "UNKNOWN" "V1" "E:/EDA/DDS/10k844/SINX/db/singt3.quartus_db" { Floorplan "E:/EDA/DDS/10k844/SINX/" "" "" { lpm_counter:q_rtl_0|alt_counter_f10ke:wysi_counter|q[4] } "NODE_NAME" } "" } } { "alt_counter_f10ke.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/alt_counter_f10ke.tdf" 271 2 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.200 ns) + CELL(1.700 ns) 3.900 ns LessThan~60 2 COMB LC6_A13 1 " "Info: 2: + IC(2.200 ns) + CELL(1.700 ns) = 3.900 ns; Loc. = LC6_A13; Fanout = 1; COMB Node = 'LessThan~60'" {  } { { "E:/EDA/DDS/10k844/SINX/db/singt3_cmp.qrpt" "" { Report "E:/EDA/DDS/10k844/SINX/db/singt3_cmp.qrpt" Compiler "singt3" "UNKNOWN" "V1" "E:/EDA/DDS/10k844/SINX/db/singt3.quartus_db" { Floorplan "E:/EDA/DDS/10k844/SINX/" "" "3.900 ns" { lpm_counter:q_rtl_0|alt_counter_f10ke:wysi_counter|q[4] LessThan~60 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.500 ns) 5.400 ns LessThan~56 3 COMB LC7_A13 1 " "Info: 3: + IC(0.000 ns) + CELL(1.500 ns) = 5.400 ns; Loc. = LC7_A13; Fanout = 1; COMB Node = 'LessThan~56'" {  } { { "E:/EDA/DDS/10k844/SINX/db/singt3_cmp.qrpt" "" { Report "E:/EDA/DDS/10k844/SINX/db/singt3_cmp.qrpt" Compiler "singt3" "UNKNOWN" "V1" "E:/EDA/DDS/10k844/SINX/db/singt3.quartus_db" { Floorplan "E:/EDA/DDS/10k844/SINX/" "" "1.500 ns" { LessThan~60 LessThan~56 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.200 ns) + CELL(1.800 ns) 9.400 ns LessThan~58 4 COMB LC8_A14 11 " "Info: 4: + IC(2.200 ns) + CELL(1.800 ns) = 9.400 ns; Loc. = LC8_A14; Fanout = 11; COMB Node = 'LessThan~58'" {  } { { "E:/EDA/DDS/10k844/SINX/db/singt3_cmp.qrpt" "" { Report "E:/EDA/DDS/10k844/SINX/db/singt3_cmp.qrpt" Compiler "singt3" "UNKNOWN" "V1" "E:/EDA/DDS/10k844/SINX/db/singt3.quartus_db" { Floorplan "E:/EDA/DDS/10k844/SINX/" "" "4.000 ns" { LessThan~56 LessThan~58 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.600 ns) + CELL(1.700 ns) 11.700 ns lpm_counter:q_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[6\] 5 REG LC7_A14 10 " "Info: 5: + IC(0.600 ns) + CELL(1.700 ns) = 11.700 ns; Loc. = LC7_A14; Fanout = 10; REG Node = 'lpm_counter:q_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[6\]'" {  } { { "E:/EDA/DDS/10k844/SINX/db/singt3_cmp.qrpt" "" { Report "E:/EDA/DDS/10k844/SINX/db/singt3_cmp.qrpt" Compiler "singt3" "UNKNOWN" "V1" "E:/EDA/DDS/10k844/SINX/db/singt3.quartus_db" { Floorplan "E:/EDA/DDS/10k844/SINX/" "" "2.300 ns" { LessThan~58 lpm_counter:q_rtl_0|alt_counter_f10ke:wysi_counter|q[6] } "NODE_NAME" } "" } } { "alt_counter_f10ke.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/alt_counter_f10ke.tdf" 271 2 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "6.700 ns 57.26 % " "Info: Total cell delay = 6.700 ns ( 57.26 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.000 ns 42.74 % " "Info: Total interconnect delay = 5.000 ns ( 42.74 % )" {  } {  } 0}  } { { "E:/EDA/DDS/10k844/SINX/db/singt3_cmp.qrpt" "" { Report "E:/EDA/DDS/10k844/SINX/db/singt3_cmp.qrpt" Compiler "singt3" "UNKNOWN" "V1" "E:/EDA/DDS/10k844/SINX/db/singt3.quartus_db" { Floorplan "E:/EDA/DDS/10k844/SINX/" "" "11.700 ns" { lpm_counter:q_rtl_0|alt_counter_f10ke:wysi_counter|q[4] LessThan~60 LessThan~56 LessThan~58 lpm_counter:q_rtl_0|alt_counter_f10ke:wysi_counter|q[6] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "11.700 ns" { lpm_counter:q_rtl_0|alt_counter_f10ke:wysi_counter|q[4] LessThan~60 LessThan~56 LessThan~58 lpm_counter:q_rtl_0|alt_counter_f10ke:wysi_counter|q[6] } { 0.000ns 2.200ns 0.000ns 2.200ns 0.600ns } { 0.000ns 1.700ns 1.500ns 1.800ns 1.700ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 5.300 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 5.300 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.800 ns) 2.800 ns clk 1 CLK PIN_43 11 " "Info: 1: + IC(0.000 ns) + CELL(2.800 ns) = 2.800 ns; Loc. = PIN_43; Fanout = 11; CLK Node = 'clk'" {  } { { "E:/EDA/DDS/10k844/SINX/db/singt3_cmp.qrpt" "" { Report "E:/EDA/DDS/10k844/SINX/db/singt3_cmp.qrpt" Compiler "singt3" "UNKNOWN" "V1" "E:/EDA/DDS/10k844/SINX/db/singt3.quartus_db" { Floorplan "E:/EDA/DDS/10k844/SINX/" "" "" { clk } "NODE_NAME" } "" } } { "singt3.vhd" "" { Text "E:/EDA/DDS/10k844/SINX/singt3.vhd" 6 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.500 ns) + CELL(0.000 ns) 5.300 ns lpm_counter:q_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[6\] 2 REG LC7_A14 10 " "Info: 2: + IC(2.500 ns) + CELL(0.000 ns) = 5.300 ns; Loc. = LC7_A14; Fanout = 10; REG Node = 'lpm_counter:q_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[6\]'" {  } { { "E:/EDA/DDS/10k844/SINX/db/singt3_cmp.qrpt" "" { Report "E:/EDA/DDS/10k844/SINX/db/singt3_cmp.qrpt" Compiler "singt3" "UNKNOWN" "V1" "E:/EDA/DDS/10k844/SINX/db/singt3.quartus_db" { Floorplan "E:/EDA/DDS/10k844/SINX/" "" "2.500 ns" { clk lpm_counter:q_rtl_0|alt_counter_f10ke:wysi_counter|q[6] } "NODE_NAME" } "" } } { "alt_counter_f10ke.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/alt_counter_f10ke.tdf" 271 2 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.800 ns 52.83 % " "Info: Total cell delay = 2.800 ns ( 52.83 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.500 ns 47.17 % " "Info: Total interconnect delay = 2.500 ns ( 47.17 % )" {  } {  } 0}  } { { "E:/EDA/DDS/10k844/SINX/db/singt3_cmp.qrpt" "" { Report "E:/EDA/DDS/10k844/SINX/db/singt3_cmp.qrpt" Compiler "singt3" "UNKNOWN" "V1" "E:/EDA/DDS/10k844/SINX/db/singt3.quartus_db" { Floorplan "E:/EDA/DDS/10k844/SINX/" "" "5.300 ns" { clk lpm_counter:q_rtl_0|alt_counter_f10ke:wysi_counter|q[6] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "5.300 ns" { clk clk~out lpm_counter:q_rtl_0|alt_counter_f10ke:wysi_counter|q[6] } { 0.000ns 0.000ns 2.500ns } { 0.000ns 2.800ns 0.000ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 5.300 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 5.300 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.800 ns) 2.800 ns clk 1 CLK PIN_43 11 " "Info: 1: + IC(0.000 ns) + CELL(2.800 ns) = 2.800 ns; Loc. = PIN_43; Fanout = 11; CLK Node = 'clk'" {  } { { "E:/EDA/DDS/10k844/SINX/db/singt3_cmp.qrpt" "" { Report "E:/EDA/DDS/10k844/SINX/db/singt3_cmp.qrpt" Compiler "singt3" "UNKNOWN" "V1" "E:/EDA/DDS/10k844/SINX/db/singt3.quartus_db" { Floorplan "E:/EDA/DDS/10k844/SINX/" "" "" { clk } "NODE_NAME" } "" } } { "singt3.vhd" "" { Text "E:/EDA/DDS/10k844/SINX/singt3.vhd" 6 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.500 ns) + CELL(0.000 ns) 5.300 ns lpm_counter:q_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[4\] 2 REG LC5_A14 31 " "Info: 2: + IC(2.500 ns) + CELL(0.000 ns) = 5.300 ns; Loc. = LC5_A14; Fanout = 31; REG Node = 'lpm_counter:q_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[4\]'" {  } { { "E:/EDA/DDS/10k844/SINX/db/singt3_cmp.qrpt" "" { Report "E:/EDA/DDS/10k844/SINX/db/singt3_cmp.qrpt" Compiler "singt3" "UNKNOWN" "V1" "E:/EDA/DDS/10k844/SINX/db/singt3.quartus_db" { Floorplan "E:/EDA/DDS/10k844/SINX/" "" "2.500 ns" { clk lpm_counter:q_rtl_0|alt_counter_f10ke:wysi_counter|q[4] } "NODE_NAME" } "" } } { "alt_counter_f10ke.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/alt_counter_f10ke.tdf" 271 2 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.800 ns 52.83 % " "Info: Total cell delay = 2.800 ns ( 52.83 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.500 ns 47.17 % " "Info: Total interconnect delay = 2.500 ns ( 47.17 % )" {  } {  } 0}  } { { "E:/EDA/DDS/10k844/SINX/db/singt3_cmp.qrpt" "" { Report "E:/EDA/DDS/10k844/SINX/db/singt3_cmp.qrpt" Compiler "singt3" "UNKNOWN" "V1" "E:/EDA/DDS/10k844/SINX/db/singt3.quartus_db" { Floorplan "E:/EDA/DDS/10k844/SINX/" "" "5.300 ns" { clk lpm_counter:q_rtl_0|alt_counter_f10ke:wysi_counter|q[4] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "5.300 ns" { clk clk~out lpm_counter:q_rtl_0|alt_counter_f10ke:wysi_counter|q[4] } { 0.000ns 0.000ns 2.500ns } { 0.000ns 2.800ns 0.000ns } } }  } 0}  } { { "E:/EDA/DDS/10k844/SINX/db/singt3_cmp.qrpt" "" { Report "E:/EDA/DDS/10k844/SINX/db/singt3_cmp.qrpt" Compiler "singt3" "UNKNOWN" "V1" "E:/EDA/DDS/10k844/SINX/db/singt3.quartus_db" { Floorplan "E:/EDA/DDS/10k844/SINX/" "" "5.300 ns" { clk lpm_counter:q_rtl_0|alt_counter_f10ke:wysi_counter|q[6] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "5.300 ns" { clk clk~out lpm_counter:q_rtl_0|alt_counter_f10ke:wysi_counter|q[6] } { 0.000ns 0.000ns 2.500ns } { 0.000ns 2.800ns 0.000ns } } } { "E:/EDA/DDS/10k844/SINX/db/singt3_cmp.qrpt" "" { Report "E:/EDA/DDS/10k844/SINX/db/singt3_cmp.qrpt" Compiler "singt3" "UNKNOWN" "V1" "E:/EDA/DDS/10k844/SINX/db/singt3.quartus_db" { Floorplan "E:/EDA/DDS/10k844/SINX/" "" "5.300 ns" { clk lpm_counter:q_rtl_0|alt_counter_f10ke:wysi_counter|q[4] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "5.300 ns" { clk clk~out lpm_counter:q_rtl_0|alt_counter_f10ke:wysi_counter|q[4] } { 0.000ns 0.000ns 2.500ns } { 0.000ns 2.800ns 0.000ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.100 ns + " "Info: + Micro clock to output delay of source is 1.100 ns" {  } { { "alt_counter_f10ke.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/alt_counter_f10ke.tdf" 271 2 0 } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "2.500 ns + " "Info: + Micro setup delay of destination is 2.500 ns" {  } { { "alt_counter_f10ke.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/alt_counter_f10ke.tdf" 271 2 0 } }  } 0}  } { { "E:/EDA/DDS/10k844/SINX/db/singt3_cmp.qrpt" "" { Report "E:/EDA/DDS/10k844/SINX/db/singt3_cmp.qrpt" Compiler "singt3" "UNKNOWN" "V1" "E:/EDA/DDS/10k844/SINX/db/singt3.quartus_db" { Floorplan "E:/EDA/DDS/10k844/SINX/" "" "11.700 ns" { lpm_counter:q_rtl_0|alt_counter_f10ke:wysi_counter|q[4] LessThan~60 LessThan~56 LessThan~58 lpm_counter:q_rtl_0|alt_counter_f10ke:wysi_counter|q[6] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "11.700 ns" { lpm_counter:q_rtl_0|alt_counter_f10ke:wysi_counter|q[4] LessThan~60 LessThan~56 LessThan~58 lpm_counter:q_rtl_0|alt_counter_f10ke:wysi_counter|q[6] } { 0.000ns 2.200ns 0.000ns 2.200ns 0.600ns } { 0.000ns 1.700ns 1.500ns 1.800ns 1.700ns } } } { "E:/EDA/DDS/10k844/SINX/db/singt3_cmp.qrpt" "" { Report "E:/EDA/DDS/10k844/SINX/db/singt3_cmp.qrpt" Compiler "singt3" "UNKNOWN" "V1" "E:/EDA/DDS/10k844/SINX/db/singt3.quartus_db" { Floorplan "E:/EDA/DDS/10k844/SINX/" "" "5.300 ns" { clk lpm_counter:q_rtl_0|alt_counter_f10ke:wysi_counter|q[6] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "5.300 ns" { clk clk~out lpm_counter:q_rtl_0|alt_counter_f10ke:wysi_counter|q[6] } { 0.000ns 0.000ns 2.500ns } { 0.000ns 2.800ns 0.000ns } } } { "E:/EDA/DDS/10k844/SINX/db/singt3_cmp.qrpt" "" { Report "E:/EDA/DDS/10k844/SINX/db/singt3_cmp.qrpt" Compiler "singt3" "UNKNOWN" "V1" "E:/EDA/DDS/10k844/SINX/db/singt3.quartus_db" { Floorplan "E:/EDA/DDS/10k844/SINX/" "" "5.300 ns" { clk lpm_counter:q_rtl_0|alt_counter_f10ke:wysi_counter|q[4] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "5.300 ns" { clk clk~out lpm_counter:q_rtl_0|alt_counter_f10ke:wysi_counter|q[4] } { 0.000ns 0.000ns 2.500ns } { 0.000ns 2.800ns 0.000ns } } }  } 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk dout\[3\] lpm_counter:q_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[0\] 31.100 ns register " "Info: tco from clock \"clk\" to destination pin \"dout\[3\]\" through register \"lpm_counter:q_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[0\]\" is 31.100 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 5.300 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 5.300 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.800 ns) 2.800 ns clk 1 CLK PIN_43 11 " "Info: 1: + IC(0.000 ns) + CELL(2.800 ns) = 2.800 ns; Loc. = PIN_43; Fanout = 11; CLK Node = 'clk'" {  } { { "E:/EDA/DDS/10k844/SINX/db/singt3_cmp.qrpt" "" { Report "E:/EDA/DDS/10k844/SINX/db/singt3_cmp.qrpt" Compiler "singt3" "UNKNOWN" "V1" "E:/EDA/DDS/10k844/SINX/db/singt3.quartus_db" { Floorplan "E:/EDA/DDS/10k844/SINX/" "" "" { clk } "NODE_NAME" } "" } } { "singt3.vhd" "" { Text "E:/EDA/DDS/10k844/SINX/singt3.vhd" 6 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.500 ns) + CELL(0.000 ns) 5.300 ns lpm_counter:q_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[0\] 2 REG LC1_A14 51 " "Info: 2: + IC(2.500 ns) + CELL(0.000 ns) = 5.300 ns; Loc. = LC1_A14; Fanout = 51; REG Node = 'lpm_counter:q_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[0\]'" {  } { { "E:/EDA/DDS/10k844/SINX/db/singt3_cmp.qrpt" "" { Report "E:/EDA/DDS/10k844/SINX/db/singt3_cmp.qrpt" Compiler "singt3" "UNKNOWN" "V1" "E:/EDA/DDS/10k844/SINX/db/singt3.quartus_db" { Floorplan "E:/EDA/DDS/10k844/SINX/" "" "2.500 ns" { clk lpm_counter:q_rtl_0|alt_counter_f10ke:wysi_counter|q[0] } "NODE_NAME" } "" } } { "alt_counter_f10ke.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/alt_counter_f10ke.tdf" 271 2 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.800 ns 52.83 % " "Info: Total cell delay = 2.800 ns ( 52.83 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.500 ns 47.17 % " "Info: Total interconnect delay = 2.500 ns ( 47.17 % )" {  } {  } 0}  } { { "E:/EDA/DDS/10k844/SINX/db/singt3_cmp.qrpt" "" { Report "E:/EDA/DDS/10k844/SINX/db/singt3_cmp.qrpt" Compiler "singt3" "UNKNOWN" "V1" "E:/EDA/DDS/10k844/SINX/db/singt3.quartus_db" { Floorplan "E:/EDA/DDS/10k844/SINX/" "" "5.300 ns" { clk lpm_counter:q_rtl_0|alt_counter_f10ke:wysi_counter|q[0] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "5.300 ns" { clk clk~out lpm_counter:q_rtl_0|alt_counter_f10ke:wysi_counter|q[0] } { 0.000ns 0.000ns 2.500ns } { 0.000ns 2.800ns 0.000ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.100 ns + " "Info: + Micro clock to output delay of source is 1.100 ns" {  } { { "alt_counter_f10ke.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/alt_counter_f10ke.tdf" 271 2 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "24.700 ns + Longest register pin " "Info: + Longest register to pin delay is 24.700 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns lpm_counter:q_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[0\] 1 REG LC1_A14 51 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC1_A14; Fanout = 51; REG Node = 'lpm_counter:q_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[0\]'" {  } { { "E:/EDA/DDS/10k844/SINX/db/singt3_cmp.qrpt" "" { Report "E:/EDA/DDS/10k844/SINX/db/singt3_cmp.qrpt" Compiler "singt3" "UNKNOWN" "V1" "E:/EDA/DDS/10k844/SINX/db/singt3.quartus_db" { Floorplan "E:/EDA/DDS/10k844/SINX/" "" "" { lpm_counter:q_rtl_0|alt_counter_f10ke:wysi_counter|q[0] } "NODE_NAME" } "" } } { "alt_counter_f10ke.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/alt_counter_f10ke.tdf" 271 2 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(4.000 ns) + CELL(2.300 ns) 6.300 ns Mux~695 2 COMB LC1_B24 1 " "Info: 2: + IC(4.000 ns) + CELL(2.300 ns) = 6.300 ns; Loc. = LC1_B24; Fanout = 1; COMB Node = 'Mux~695'" {  } { { "E:/EDA/DDS/10k844/SINX/db/singt3_cmp.qrpt" "" { Report "E:/EDA/DDS/10k844/SINX/db/singt3_cmp.qrpt" Compiler "singt3" "UNKNOWN" "V1" "E:/EDA/DDS/10k844/SINX/db/singt3.quartus_db" { Floorplan "E:/EDA/DDS/10k844/SINX/" "" "6.300 ns" { lpm_counter:q_rtl_0|alt_counter_f10ke:wysi_counter|q[0] Mux~695 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.800 ns) + CELL(2.300 ns) 11.400 ns Mux~697 3 COMB LC7_B5 1 " "Info: 3: + IC(2.800 ns) + CELL(2.300 ns) = 11.400 ns; Loc. = LC7_B5; Fanout = 1; COMB Node = 'Mux~697'" {  } { { "E:/EDA/DDS/10k844/SINX/db/singt3_cmp.qrpt" "" { Report "E:/EDA/DDS/10k844/SINX/db/singt3_cmp.qrpt" Compiler "singt3" "UNKNOWN" "V1" "E:/EDA/DDS/10k844/SINX/db/singt3.quartus_db" { Floorplan "E:/EDA/DDS/10k844/SINX/" "" "5.100 ns" { Mux~695 Mux~697 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.600 ns) + CELL(2.300 ns) 14.300 ns Mux~699 4 COMB LC8_B5 1 " "Info: 4: + IC(0.600 ns) + CELL(2.300 ns) = 14.300 ns; Loc. = LC8_B5; Fanout = 1; COMB Node = 'Mux~699'" {  } { { "E:/EDA/DDS/10k844/SINX/db/singt3_cmp.qrpt" "" { Report "E:/EDA/DDS/10k844/SINX/db/singt3_cmp.qrpt" Compiler "singt3" "UNKNOWN" "V1" "E:/EDA/DDS/10k844/SINX/db/singt3.quartus_db" { Floorplan "E:/EDA/DDS/10k844/SINX/" "" "2.900 ns" { Mux~697 Mux~699 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.600 ns) + CELL(2.300 ns) 17.200 ns Mux~700 5 COMB LC2_B5 1 " "Info: 5: + IC(0.600 ns) + CELL(2.300 ns) = 17.200 ns; Loc. = LC2_B5; Fanout = 1; COMB Node = 'Mux~700'" {  } { { "E:/EDA/DDS/10k844/SINX/db/singt3_cmp.qrpt" "" { Report "E:/EDA/DDS/10k844/SINX/db/singt3_cmp.qrpt" Compiler "singt3" "UNKNOWN" "V1" "E:/EDA/DDS/10k844/SINX/db/singt3.quartus_db" { Floorplan "E:/EDA/DDS/10k844/SINX/" "" "2.900 ns" { Mux~699 Mux~700 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.400 ns) + CELL(5.100 ns) 24.700 ns dout\[3\] 6 PIN PIN_22 0 " "Info: 6: + IC(2.400 ns) + CELL(5.100 ns) = 24.700 ns; Loc. = PIN_22; Fanout = 0; PIN Node = 'dout\[3\]'" {  } { { "E:/EDA/DDS/10k844/SINX/db/singt3_cmp.qrpt" "" { Report "E:/EDA/DDS/10k844/SINX/db/singt3_cmp.qrpt" Compiler "singt3" "UNKNOWN" "V1" "E:/EDA/DDS/10k844/SINX/db/singt3.quartus_db" { Floorplan "E:/EDA/DDS/10k844/SINX/" "" "7.500 ns" { Mux~700 dout[3] } "NODE_NAME" } "" } } { "singt3.vhd" "" { Text "E:/EDA/DDS/10k844/SINX/singt3.vhd" 7 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "14.300 ns 57.89 % " "Info: Total cell delay = 14.300 ns ( 57.89 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "10.400 ns 42.11 % " "Info: Total interconnect delay = 10.400 ns ( 42.11 % )" {  } {  } 0}  } { { "E:/EDA/DDS/10k844/SINX/db/singt3_cmp.qrpt" "" { Report "E:/EDA/DDS/10k844/SINX/db/singt3_cmp.qrpt" Compiler "singt3" "UNKNOWN" "V1" "E:/EDA/DDS/10k844/SINX/db/singt3.quartus_db" { Floorplan "E:/EDA/DDS/10k844/SINX/" "" "24.700 ns" { lpm_counter:q_rtl_0|alt_counter_f10ke:wysi_counter|q[0] Mux~695 Mux~697 Mux~699 Mux~700 dout[3] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "24.700 ns" { lpm_counter:q_rtl_0|alt_counter_f10ke:wysi_counter|q[0] Mux~695 Mux~697 Mux~699 Mux~700 dout[3] } { 0.000ns 4.000ns 2.800ns 0.600ns 0.600ns 2.400ns } { 0.000ns 2.300ns 2.300ns 2.300ns 2.300ns 5.100ns } } }  } 0}  } { { "E:/EDA/DDS/10k844/SINX/db/singt3_cmp.qrpt" "" { Report "E:/EDA/DDS/10k844/SINX/db/singt3_cmp.qrpt" Compiler "singt3" "UNKNOWN" "V1" "E:/EDA/DDS/10k844/SINX/db/singt3.quartus_db" { Floorplan "E:/EDA/DDS/10k844/SINX/" "" "5.300 ns" { clk lpm_counter:q_rtl_0|alt_counter_f10ke:wysi_counter|q[0] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "5.300 ns" { clk clk~out lpm_counter:q_rtl_0|alt_counter_f10ke:wysi_counter|q[0] } { 0.000ns 0.000ns 2.500ns } { 0.000ns 2.800ns 0.000ns } } } { "E:/EDA/DDS/10k844/SINX/db/singt3_cmp.qrpt" "" { Report "E:/EDA/DDS/10k844/SINX/db/singt3_cmp.qrpt" Compiler "singt3" "UNKNOWN" "V1" "E:/EDA/DDS/10k844/SINX/db/singt3.quartus_db" { Floorplan "E:/EDA/DDS/10k844/SINX/" "" "24.700 ns" { lpm_counter:q_rtl_0|alt_counter_f10ke:wysi_counter|q[0] Mux~695 Mux~697 Mux~699 Mux~700 dout[3] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "24.700 ns" { lpm_counter:q_rtl_0|alt_counter_f10ke:wysi_counter|q[0] Mux~695 Mux~697 Mux~699 Mux~700 dout[3] } { 0.000ns 4.000ns 2.800ns 0.600ns 0.600ns 2.400ns } { 0.000ns 2.300ns 2.300ns 2.300ns 2.300ns 5.100ns } } }  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 1  Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Fri Apr 14 19:15:49 2006 " "Info: Processing ended: Fri Apr 14 19:15:49 2006" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Info: Elapsed time: 00:00:03" {  } {  } 0}  } {  } 0}