init_cnt8b.tan.qmsg

来自「在EDA开发软件QuartusII上利用VHDL语言实现DDS信号发生器」· QMSG 代码 · 共 12 行 · 第 1/3 页

{ "Info" "ITDB_FULL_TCO_RESULT" "CLK FOUT\[5\] lpm_counter:CNT8_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[5\] 14.800 ns register " "Info: tco from clock \"CLK\" to destination pin \"FOUT\[5\]\" through register \"lpm_counter:CNT8_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[5\]\" is 14.800 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK source 5.300 ns + Longest register " "Info: + Longest clock path from clock \"CLK\" to source register is 5.300 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.800 ns) 2.800 ns CLK 1 CLK PIN_43 16 " "Info: 1: + IC(0.000 ns) + CELL(2.800 ns) = 2.800 ns; Loc. = PIN_43; Fanout = 16; CLK Node = 'CLK'" {  } { { "E:/EDA/DDS/Init_CNT8B/db/INIT_CNT8B_cmp.qrpt" "" { Report "E:/EDA/DDS/Init_CNT8B/db/INIT_CNT8B_cmp.qrpt" Compiler "INIT_CNT8B" "UNKNOWN" "V1" "E:/EDA/DDS/Init_CNT8B/db/INIT_CNT8B.quartus_db" { Floorplan "E:/EDA/DDS/Init_CNT8B/" "" "" { CLK } "NODE_NAME" } "" } } { "INIT_CNT8B.vhd" "" { Text "E:/EDA/DDS/Init_CNT8B/INIT_CNT8B.vhd" 6 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.500 ns) + CELL(0.000 ns) 5.300 ns lpm_counter:CNT8_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[5\] 2 REG LC6_A15 6 " "Info: 2: + IC(2.500 ns) + CELL(0.000 ns) = 5.300 ns; Loc. = LC6_A15; Fanout = 6; REG Node = 'lpm_counter:CNT8_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[5\]'" {  } { { "E:/EDA/DDS/Init_CNT8B/db/INIT_CNT8B_cmp.qrpt" "" { Report "E:/EDA/DDS/Init_CNT8B/db/INIT_CNT8B_cmp.qrpt" Compiler "INIT_CNT8B" "UNKNOWN" "V1" "E:/EDA/DDS/Init_CNT8B/db/INIT_CNT8B.quartus_db" { Floorplan "E:/EDA/DDS/Init_CNT8B/" "" "2.500 ns" { CLK lpm_counter:CNT8_rtl_0|alt_counter_f10ke:wysi_counter|q[5] } "NODE_NAME" } "" } } { "alt_counter_f10ke.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/alt_counter_f10ke.tdf" 271 2 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.800 ns 52.83 % " "Info: Total cell delay = 2.800 ns ( 52.83 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.500 ns 47.17 % " "Info: Total interconnect delay = 2.500 ns ( 47.17 % )" {  } {  } 0}  } { { "E:/EDA/DDS/Init_CNT8B/db/INIT_CNT8B_cmp.qrpt" "" { Report "E:/EDA/DDS/Init_CNT8B/db/INIT_CNT8B_cmp.qrpt" Compiler "INIT_CNT8B" "UNKNOWN" "V1" "E:/EDA/DDS/Init_CNT8B/db/INIT_CNT8B.quartus_db" { Floorplan "E:/EDA/DDS/Init_CNT8B/" "" "5.300 ns" { CLK lpm_counter:CNT8_rtl_0|alt_counter_f10ke:wysi_counter|q[5] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "5.300 ns" { CLK CLK~out lpm_counter:CNT8_rtl_0|alt_counter_f10ke:wysi_counter|q[5] } { 0.000ns 0.000ns 2.500ns } { 0.000ns 2.800ns 0.000ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.100 ns + " "Info: + Micro clock to output delay of source is 1.100 ns" {  } { { "alt_counter_f10ke.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/alt_counter_f10ke.tdf" 271 2 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "8.400 ns + Longest register pin " "Info: + Longest register to pin delay is 8.400 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns lpm_counter:CNT8_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[5\] 1 REG LC6_A15 6 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC6_A15; Fanout = 6; REG Node = 'lpm_counter:CNT8_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[5\]'" {  } { { "E:/EDA/DDS/Init_CNT8B/db/INIT_CNT8B_cmp.qrpt" "" { Report "E:/EDA/DDS/Init_CNT8B/db/INIT_CNT8B_cmp.qrpt" Compiler "INIT_CNT8B" "UNKNOWN" "V1" "E:/EDA/DDS/Init_CNT8B/db/INIT_CNT8B.quartus_db" { Floorplan "E:/EDA/DDS/Init_CNT8B/" "" "" { lpm_counter:CNT8_rtl_0|alt_counter_f10ke:wysi_counter|q[5] } "NODE_NAME" } "" } } { "alt_counter_f10ke.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/alt_counter_f10ke.tdf" 271 2 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.300 ns) + CELL(5.100 ns) 8.400 ns FOUT\[5\] 2 PIN PIN_24 0 " "Info: 2: + IC(3.300 ns) + CELL(5.100 ns) = 8.400 ns; Loc. = PIN_24; Fanout = 0; PIN Node = 'FOUT\[5\]'" {  } { { "E:/EDA/DDS/Init_CNT8B/db/INIT_CNT8B_cmp.qrpt" "" { Report "E:/EDA/DDS/Init_CNT8B/db/INIT_CNT8B_cmp.qrpt" Compiler "INIT_CNT8B" "UNKNOWN" "V1" "E:/EDA/DDS/Init_CNT8B/db/INIT_CNT8B.quartus_db" { Floorplan "E:/EDA/DDS/Init_CNT8B/" "" "8.400 ns" { lpm_counter:CNT8_rtl_0|alt_counter_f10ke:wysi_counter|q[5] FOUT[5] } "NODE_NAME" } "" } } { "INIT_CNT8B.vhd" "" { Text "E:/EDA/DDS/Init_CNT8B/INIT_CNT8B.vhd" 8 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "5.100 ns 60.71 % " "Info: Total cell delay = 5.100 ns ( 60.71 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.300 ns 39.29 % " "Info: Total interconnect delay = 3.300 ns ( 39.29 % )" {  } {  } 0}  } { { "E:/EDA/DDS/Init_CNT8B/db/INIT_CNT8B_cmp.qrpt" "" { Report "E:/EDA/DDS/Init_CNT8B/db/INIT_CNT8B_cmp.qrpt" Compiler "INIT_CNT8B" "UNKNOWN" "V1" "E:/EDA/DDS/Init_CNT8B/db/INIT_CNT8B.quartus_db" { Floorplan "E:/EDA/DDS/Init_CNT8B/" "" "8.400 ns" { lpm_counter:CNT8_rtl_0|alt_counter_f10ke:wysi_counter|q[5] FOUT[5] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "8.400 ns" { lpm_counter:CNT8_rtl_0|alt_counter_f10ke:wysi_counter|q[5] FOUT[5] } { 0.000ns 3.300ns } { 0.000ns 5.100ns } } }  } 0}  } { { "E:/EDA/DDS/Init_CNT8B/db/INIT_CNT8B_cmp.qrpt" "" { Report "E:/EDA/DDS/Init_CNT8B/db/INIT_CNT8B_cmp.qrpt" Compiler "INIT_CNT8B" "UNKNOWN" "V1" "E:/EDA/DDS/Init_CNT8B/db/INIT_CNT8B.quartus_db" { Floorplan "E:/EDA/DDS/Init_CNT8B/" "" "5.300 ns" { CLK lpm_counter:CNT8_rtl_0|alt_counter_f10ke:wysi_counter|q[5] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "5.300 ns" { CLK CLK~out lpm_counter:CNT8_rtl_0|alt_counter_f10ke:wysi_counter|q[5] } { 0.000ns 0.000ns 2.500ns } { 0.000ns 2.800ns 0.000ns } } } { "E:/EDA/DDS/Init_CNT8B/db/INIT_CNT8B_cmp.qrpt" "" { Report "E:/EDA/DDS/Init_CNT8B/db/INIT_CNT8B_cmp.qrpt" Compiler "INIT_CNT8B" "UNKNOWN" "V1" "E:/EDA/DDS/Init_CNT8B/db/INIT_CNT8B.quartus_db" { Floorplan "E:/EDA/DDS/Init_CNT8B/" "" "8.400 ns" { lpm_counter:CNT8_rtl_0|alt_counter_f10ke:wysi_counter|q[5] FOUT[5] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "8.400 ns" { lpm_counter:CNT8_rtl_0|alt_counter_f10ke:wysi_counter|q[5] FOUT[5] } { 0.000ns 3.300ns } { 0.000ns 5.100ns } } }  } 0}
{ "Info" "ITDB_TH_RESULT" "lpm_counter:CNT8_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[4\] DATA\[4\] CLK 0.800 ns register " "Info: th for register \"lpm_counter:CNT8_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[4\]\" (data pin = \"DATA\[4\]\", clock pin = \"CLK\") is 0.800 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK destination 5.300 ns + Longest register " "Info: + Longest clock path from clock \"CLK\" to destination register is 5.300 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.800 ns) 2.800 ns CLK 1 CLK PIN_43 16 " "Info: 1: + IC(0.000 ns) + CELL(2.800 ns) = 2.800 ns; Loc. = PIN_43; Fanout = 16; CLK Node = 'CLK'" {  } { { "E:/EDA/DDS/Init_CNT8B/db/INIT_CNT8B_cmp.qrpt" "" { Report "E:/EDA/DDS/Init_CNT8B/db/INIT_CNT8B_cmp.qrpt" Compiler "INIT_CNT8B" "UNKNOWN" "V1" "E:/EDA/DDS/Init_CNT8B/db/INIT_CNT8B.quartus_db" { Floorplan "E:/EDA/DDS/Init_CNT8B/" "" "" { CLK } "NODE_NAME" } "" } } { "INIT_CNT8B.vhd" "" { Text "E:/EDA/DDS/Init_CNT8B/INIT_CNT8B.vhd" 6 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.500 ns) + CELL(0.000 ns) 5.300 ns lpm_counter:CNT8_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[4\] 2 REG LC5_A15 6 " "Info: 2: + IC(2.500 ns) + CELL(0.000 ns) = 5.300 ns; Loc. = LC5_A15; Fanout = 6; REG Node = 'lpm_counter:CNT8_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[4\]'" {  } { { "E:/EDA/DDS/Init_CNT8B/db/INIT_CNT8B_cmp.qrpt" "" { Report "E:/EDA/DDS/Init_CNT8B/db/INIT_CNT8B_cmp.qrpt" Compiler "INIT_CNT8B" "UNKNOWN" "V1" "E:/EDA/DDS/Init_CNT8B/db/INIT_CNT8B.quartus_db" { Floorplan "E:/EDA/DDS/Init_CNT8B/" "" "2.500 ns" { CLK lpm_counter:CNT8_rtl_0|alt_counter_f10ke:wysi_counter|q[4] } "NODE_NAME" } "" } } { "alt_counter_f10ke.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/alt_counter_f10ke.tdf" 271 2 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.800 ns 52.83 % " "Info: Total cell delay = 2.800 ns ( 52.83 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.500 ns 47.17 % " "Info: Total interconnect delay = 2.500 ns ( 47.17 % )" {  } {  } 0}  } { { "E:/EDA/DDS/Init_CNT8B/db/INIT_CNT8B_cmp.qrpt" "" { Report "E:/EDA/DDS/Init_CNT8B/db/INIT_CNT8B_cmp.qrpt" Compiler "INIT_CNT8B" "UNKNOWN" "V1" "E:/EDA/DDS/Init_CNT8B/db/INIT_CNT8B.quartus_db" { Floorplan "E:/EDA/DDS/Init_CNT8B/" "" "5.300 ns" { CLK lpm_counter:CNT8_rtl_0|alt_counter_f10ke:wysi_counter|q[4] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "5.300 ns" { CLK CLK~out lpm_counter:CNT8_rtl_0|alt_counter_f10ke:wysi_counter|q[4] } { 0.000ns 0.000ns 2.500ns } { 0.000ns 2.800ns 0.000ns } } }  } 0} { "Info" "ITDB_FULL_TH_DELAY" "1.600 ns + " "Info: + Micro hold delay of destination is 1.600 ns" {  } { { "alt_counter_f10ke.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/alt_counter_f10ke.tdf" 271 2 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.100 ns - Shortest pin register " "Info: - Shortest pin to register delay is 6.100 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.800 ns) 2.800 ns DATA\[4\] 1 PIN PIN_1 2 " "Info: 1: + IC(0.000 ns) + CELL(2.800 ns) = 2.800 ns; Loc. = PIN_1; Fanout = 2; PIN Node = 'DATA\[4\]'" {  } { { "E:/EDA/DDS/Init_CNT8B/db/INIT_CNT8B_cmp.qrpt" "" { Report "E:/EDA/DDS/Init_CNT8B/db/INIT_CNT8B_cmp.qrpt" Compiler "INIT_CNT8B" "UNKNOWN" "V1" "E:/EDA/DDS/Init_CNT8B/db/INIT_CNT8B.quartus_db" { Floorplan "E:/EDA/DDS/Init_CNT8B/" "" "" { DATA[4] } "NODE_NAME" } "" } } { "INIT_CNT8B.vhd" "" { Text "E:/EDA/DDS/Init_CNT8B/INIT_CNT8B.vhd" 7 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.600 ns) + CELL(1.700 ns) 6.100 ns lpm_counter:CNT8_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[4\] 2 REG LC5_A15 6 " "Info: 2: + IC(1.600 ns) + CELL(1.700 ns) = 6.100 ns; Loc. = LC5_A15; Fanout = 6; REG Node = 'lpm_counter:CNT8_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[4\]'" {  } { { "E:/EDA/DDS/Init_CNT8B/db/INIT_CNT8B_cmp.qrpt" "" { Report "E:/EDA/DDS/Init_CNT8B/db/INIT_CNT8B_cmp.qrpt" Compiler "INIT_CNT8B" "UNKNOWN" "V1" "E:/EDA/DDS/Init_CNT8B/db/INIT_CNT8B.quartus_db" { Floorplan "E:/EDA/DDS/Init_CNT8B/" "" "3.300 ns" { DATA[4] lpm_counter:CNT8_rtl_0|alt_counter_f10ke:wysi_counter|q[4] } "NODE_NAME" } "" } } { "alt_counter_f10ke.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/alt_counter_f10ke.tdf" 271 2 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.500 ns 73.77 % " "Info: Total cell delay = 4.500 ns ( 73.77 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.600 ns 26.23 % " "Info: Total interconnect delay = 1.600 ns ( 26.23 % )" {  } {  } 0}  } { { "E:/EDA/DDS/Init_CNT8B/db/INIT_CNT8B_cmp.qrpt" "" { Report "E:/EDA/DDS/Init_CNT8B/db/INIT_CNT8B_cmp.qrpt" Compiler "INIT_CNT8B" "UNKNOWN" "V1" "E:/EDA/DDS/Init_CNT8B/db/INIT_CNT8B.quartus_db" { Floorplan "E:/EDA/DDS/Init_CNT8B/" "" "6.100 ns" { DATA[4] lpm_counter:CNT8_rtl_0|alt_counter_f10ke:wysi_counter|q[4] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "6.100 ns" { DATA[4] DATA[4]~out lpm_counter:CNT8_rtl_0|alt_counter_f10ke:wysi_counter|q[4] } { 0.000ns 0.000ns 1.600ns } { 0.000ns 2.800ns 1.700ns } } }  } 0}  } { { "E:/EDA/DDS/Init_CNT8B/db/INIT_CNT8B_cmp.qrpt" "" { Report "E:/EDA/DDS/Init_CNT8B/db/INIT_CNT8B_cmp.qrpt" Compiler "INIT_CNT8B" "UNKNOWN" "V1" "E:/EDA/DDS/Init_CNT8B/db/INIT_CNT8B.quartus_db" { Floorplan "E:/EDA/DDS/Init_CNT8B/" "" "5.300 ns" { CLK lpm_counter:CNT8_rtl_0|alt_counter_f10ke:wysi_counter|q[4] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "5.300 ns" { CLK CLK~out lpm_counter:CNT8_rtl_0|alt_counter_f10ke:wysi_counter|q[4] } { 0.000ns 0.000ns 2.500ns } { 0.000ns 2.800ns 0.000ns } } } { "E:/EDA/DDS/Init_CNT8B/db/INIT_CNT8B_cmp.qrpt" "" { Report "E:/EDA/DDS/Init_CNT8B/db/INIT_CNT8B_cmp.qrpt" Compiler "INIT_CNT8B" "UNKNOWN" "V1" "E:/EDA/DDS/Init_CNT8B/db/INIT_CNT8B.quartus_db" { Floorplan "E:/EDA/DDS/Init_CNT8B/" "" "6.100 ns" { DATA[4] lpm_counter:CNT8_rtl_0|alt_counter_f10ke:wysi_counter|q[4] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "6.100 ns" { DATA[4] DATA[4]~out lpm_counter:CNT8_rtl_0|alt_counter_f10ke:wysi_counter|q[4] } { 0.000ns 0.000ns 1.600ns } { 0.000ns 2.800ns 1.700ns } } }  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 1  Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Sun Apr 09 21:01:30 2006 " "Info: Processing ended: Sun Apr 09 21:01:30 2006" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" {  } {  } 0}  } {  } 0}