init_cnt8b.tan.qmsg

来自「在EDA开发软件QuartusII上利用VHDL语言实现DDS信号发生器」· QMSG 代码 · 共 12 行 · 第 1/3 页

{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "CLK " "Info: Assuming node \"CLK\" is an undefined clock" {  } { { "INIT_CNT8B.vhd" "" { Text "E:/EDA/DDS/Init_CNT8B/INIT_CNT8B.vhd" 6 -1 0 } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "CLK" } } } }  } 0}  } {  } 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "CLK register lpm_counter:CNT8_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[0\] register lpm_counter:CNT8_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[7\] 49.75 MHz 20.1 ns Internal " "Info: Clock \"CLK\" has Internal fmax of 49.75 MHz between source register \"lpm_counter:CNT8_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[0\]\" and destination register \"lpm_counter:CNT8_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[7\]\" (period= 20.1 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "16.500 ns + Longest register register " "Info: + Longest register to register delay is 16.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns lpm_counter:CNT8_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[0\] 1 REG LC1_A15 6 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC1_A15; Fanout = 6; REG Node = 'lpm_counter:CNT8_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[0\]'" {  } { { "E:/EDA/DDS/Init_CNT8B/db/INIT_CNT8B_cmp.qrpt" "" { Report "E:/EDA/DDS/Init_CNT8B/db/INIT_CNT8B_cmp.qrpt" Compiler "INIT_CNT8B" "UNKNOWN" "V1" "E:/EDA/DDS/Init_CNT8B/db/INIT_CNT8B.quartus_db" { Floorplan "E:/EDA/DDS/Init_CNT8B/" "" "" { lpm_counter:CNT8_rtl_0|alt_counter_f10ke:wysi_counter|q[0] } "NODE_NAME" } "" } } { "alt_counter_f10ke.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/alt_counter_f10ke.tdf" 271 2 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.200 ns) + CELL(1.200 ns) 3.400 ns lpm_add_sub:add_rtl_1\|addcore:adder\|a_csnbuffer:result_node\|cout\[0\] 2 COMB LC1_A14 2 " "Info: 2: + IC(2.200 ns) + CELL(1.200 ns) = 3.400 ns; Loc. = LC1_A14; Fanout = 2; COMB Node = 'lpm_add_sub:add_rtl_1\|addcore:adder\|a_csnbuffer:result_node\|cout\[0\]'" {  } { { "E:/EDA/DDS/Init_CNT8B/db/INIT_CNT8B_cmp.qrpt" "" { Report "E:/EDA/DDS/Init_CNT8B/db/INIT_CNT8B_cmp.qrpt" Compiler "INIT_CNT8B" "UNKNOWN" "V1" "E:/EDA/DDS/Init_CNT8B/db/INIT_CNT8B.quartus_db" { Floorplan "E:/EDA/DDS/Init_CNT8B/" "" "3.400 ns" { lpm_counter:CNT8_rtl_0|alt_counter_f10ke:wysi_counter|q[0] lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[0] } "NODE_NAME" } "" } } { "a_csnbuffer.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/a_csnbuffer.tdf" 18 2 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.300 ns) 3.700 ns lpm_add_sub:add_rtl_1\|addcore:adder\|a_csnbuffer:result_node\|cout\[1\] 3 COMB LC2_A14 2 " "Info: 3: + IC(0.000 ns) + CELL(0.300 ns) = 3.700 ns; Loc. = LC2_A14; Fanout = 2; COMB Node = 'lpm_add_sub:add_rtl_1\|addcore:adder\|a_csnbuffer:result_node\|cout\[1\]'" {  } { { "E:/EDA/DDS/Init_CNT8B/db/INIT_CNT8B_cmp.qrpt" "" { Report "E:/EDA/DDS/Init_CNT8B/db/INIT_CNT8B_cmp.qrpt" Compiler "INIT_CNT8B" "UNKNOWN" "V1" "E:/EDA/DDS/Init_CNT8B/db/INIT_CNT8B.quartus_db" { Floorplan "E:/EDA/DDS/Init_CNT8B/" "" "0.300 ns" { lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[0] lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[1] } "NODE_NAME" } "" } } { "a_csnbuffer.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/a_csnbuffer.tdf" 18 2 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.300 ns) 4.000 ns lpm_add_sub:add_rtl_1\|addcore:adder\|a_csnbuffer:result_node\|cout\[2\] 4 COMB LC3_A14 2 " "Info: 4: + IC(0.000 ns) + CELL(0.300 ns) = 4.000 ns; Loc. = LC3_A14; Fanout = 2; COMB Node = 'lpm_add_sub:add_rtl_1\|addcore:adder\|a_csnbuffer:result_node\|cout\[2\]'" {  } { { "E:/EDA/DDS/Init_CNT8B/db/INIT_CNT8B_cmp.qrpt" "" { Report "E:/EDA/DDS/Init_CNT8B/db/INIT_CNT8B_cmp.qrpt" Compiler "INIT_CNT8B" "UNKNOWN" "V1" "E:/EDA/DDS/Init_CNT8B/db/INIT_CNT8B.quartus_db" { Floorplan "E:/EDA/DDS/Init_CNT8B/" "" "0.300 ns" { lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[1] lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[2] } "NODE_NAME" } "" } } { "a_csnbuffer.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/a_csnbuffer.tdf" 18 2 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.300 ns) 4.300 ns lpm_add_sub:add_rtl_1\|addcore:adder\|a_csnbuffer:result_node\|cout\[3\] 5 COMB LC4_A14 2 " "Info: 5: + IC(0.000 ns) + CELL(0.300 ns) = 4.300 ns; Loc. = LC4_A14; Fanout = 2; COMB Node = 'lpm_add_sub:add_rtl_1\|addcore:adder\|a_csnbuffer:result_node\|cout\[3\]'" {  } { { "E:/EDA/DDS/Init_CNT8B/db/INIT_CNT8B_cmp.qrpt" "" { Report "E:/EDA/DDS/Init_CNT8B/db/INIT_CNT8B_cmp.qrpt" Compiler "INIT_CNT8B" "UNKNOWN" "V1" "E:/EDA/DDS/Init_CNT8B/db/INIT_CNT8B.quartus_db" { Floorplan "E:/EDA/DDS/Init_CNT8B/" "" "0.300 ns" { lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[2] lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[3] } "NODE_NAME" } "" } } { "a_csnbuffer.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/a_csnbuffer.tdf" 18 2 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.300 ns) 4.600 ns lpm_add_sub:add_rtl_1\|addcore:adder\|a_csnbuffer:result_node\|cout\[4\] 6 COMB LC5_A14 2 " "Info: 6: + IC(0.000 ns) + CELL(0.300 ns) = 4.600 ns; Loc. = LC5_A14; Fanout = 2; COMB Node = 'lpm_add_sub:add_rtl_1\|addcore:adder\|a_csnbuffer:result_node\|cout\[4\]'" {  } { { "E:/EDA/DDS/Init_CNT8B/db/INIT_CNT8B_cmp.qrpt" "" { Report "E:/EDA/DDS/Init_CNT8B/db/INIT_CNT8B_cmp.qrpt" Compiler "INIT_CNT8B" "UNKNOWN" "V1" "E:/EDA/DDS/Init_CNT8B/db/INIT_CNT8B.quartus_db" { Floorplan "E:/EDA/DDS/Init_CNT8B/" "" "0.300 ns" { lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[3] lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[4] } "NODE_NAME" } "" } } { "a_csnbuffer.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/a_csnbuffer.tdf" 18 2 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.300 ns) 4.900 ns lpm_add_sub:add_rtl_1\|addcore:adder\|a_csnbuffer:result_node\|cout\[5\] 7 COMB LC6_A14 2 " "Info: 7: + IC(0.000 ns) + CELL(0.300 ns) = 4.900 ns; Loc. = LC6_A14; Fanout = 2; COMB Node = 'lpm_add_sub:add_rtl_1\|addcore:adder\|a_csnbuffer:result_node\|cout\[5\]'" {  } { { "E:/EDA/DDS/Init_CNT8B/db/INIT_CNT8B_cmp.qrpt" "" { Report "E:/EDA/DDS/Init_CNT8B/db/INIT_CNT8B_cmp.qrpt" Compiler "INIT_CNT8B" "UNKNOWN" "V1" "E:/EDA/DDS/Init_CNT8B/db/INIT_CNT8B.quartus_db" { Floorplan "E:/EDA/DDS/Init_CNT8B/" "" "0.300 ns" { lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[4] lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[5] } "NODE_NAME" } "" } } { "a_csnbuffer.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/a_csnbuffer.tdf" 18 2 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.300 ns) 6.200 ns lpm_add_sub:add_rtl_1\|addcore:adder\|a_csnbuffer:result_node\|cs_buffer\[6\] 8 COMB LC7_A14 1 " "Info: 8: + IC(0.000 ns) + CELL(1.300 ns) = 6.200 ns; Loc. = LC7_A14; Fanout = 1; COMB Node = 'lpm_add_sub:add_rtl_1\|addcore:adder\|a_csnbuffer:result_node\|cs_buffer\[6\]'" {  } { { "E:/EDA/DDS/Init_CNT8B/db/INIT_CNT8B_cmp.qrpt" "" { Report "E:/EDA/DDS/Init_CNT8B/db/INIT_CNT8B_cmp.qrpt" Compiler "INIT_CNT8B" "UNKNOWN" "V1" "E:/EDA/DDS/Init_CNT8B/db/INIT_CNT8B.quartus_db" { Floorplan "E:/EDA/DDS/Init_CNT8B/" "" "1.300 ns" { lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[5] lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cs_buffer[6] } "NODE_NAME" } "" } } { "a_csnbuffer.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/a_csnbuffer.tdf" 25 13 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.200 ns) + CELL(2.300 ns) 10.700 ns reduce_nor~49 9 COMB LC7_A13 2 " "Info: 9: + IC(2.200 ns) + CELL(2.300 ns) = 10.700 ns; Loc. = LC7_A13; Fanout = 2; COMB Node = 'reduce_nor~49'" {  } { { "E:/EDA/DDS/Init_CNT8B/db/INIT_CNT8B_cmp.qrpt" "" { Report "E:/EDA/DDS/Init_CNT8B/db/INIT_CNT8B_cmp.qrpt" Compiler "INIT_CNT8B" "UNKNOWN" "V1" "E:/EDA/DDS/Init_CNT8B/db/INIT_CNT8B.quartus_db" { Floorplan "E:/EDA/DDS/Init_CNT8B/" "" "4.500 ns" { lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cs_buffer[6] reduce_nor~49 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.600 ns) + CELL(1.800 ns) 13.100 ns reduce_nor~51 10 COMB LC1_A13 15 " "Info: 10: + IC(0.600 ns) + CELL(1.800 ns) = 13.100 ns; Loc. = LC1_A13; Fanout = 15; COMB Node = 'reduce_nor~51'" {  } { { "E:/EDA/DDS/Init_CNT8B/db/INIT_CNT8B_cmp.qrpt" "" { Report "E:/EDA/DDS/Init_CNT8B/db/INIT_CNT8B_cmp.qrpt" Compiler "INIT_CNT8B" "UNKNOWN" "V1" "E:/EDA/DDS/Init_CNT8B/db/INIT_CNT8B.quartus_db" { Floorplan "E:/EDA/DDS/Init_CNT8B/" "" "2.400 ns" { reduce_nor~49 reduce_nor~51 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.200 ns) + CELL(1.200 ns) 16.500 ns lpm_counter:CNT8_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[7\] 11 REG LC8_A15 3 " "Info: 11: + IC(2.200 ns) + CELL(1.200 ns) = 16.500 ns; Loc. = LC8_A15; Fanout = 3; REG Node = 'lpm_counter:CNT8_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[7\]'" {  } { { "E:/EDA/DDS/Init_CNT8B/db/INIT_CNT8B_cmp.qrpt" "" { Report "E:/EDA/DDS/Init_CNT8B/db/INIT_CNT8B_cmp.qrpt" Compiler "INIT_CNT8B" "UNKNOWN" "V1" "E:/EDA/DDS/Init_CNT8B/db/INIT_CNT8B.quartus_db" { Floorplan "E:/EDA/DDS/Init_CNT8B/" "" "3.400 ns" { reduce_nor~51 lpm_counter:CNT8_rtl_0|alt_counter_f10ke:wysi_counter|q[7] } "NODE_NAME" } "" } } { "alt_counter_f10ke.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/alt_counter_f10ke.tdf" 271 2 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "9.300 ns 56.36 % " "Info: Total cell delay = 9.300 ns ( 56.36 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "7.200 ns 43.64 % " "Info: Total interconnect delay = 7.200 ns ( 43.64 % )" {  } {  } 0}  } { { "E:/EDA/DDS/Init_CNT8B/db/INIT_CNT8B_cmp.qrpt" "" { Report "E:/EDA/DDS/Init_CNT8B/db/INIT_CNT8B_cmp.qrpt" Compiler "INIT_CNT8B" "UNKNOWN" "V1" "E:/EDA/DDS/Init_CNT8B/db/INIT_CNT8B.quartus_db" { Floorplan "E:/EDA/DDS/Init_CNT8B/" "" "16.500 ns" { lpm_counter:CNT8_rtl_0|alt_counter_f10ke:wysi_counter|q[0] lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[0] lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[1] lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[2] lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[3] lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[4] lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[5] lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cs_buffer[6] reduce_nor~49 reduce_nor~51 lpm_counter:CNT8_rtl_0|alt_counter_f10ke:wysi_counter|q[7] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "16.500 ns" { lpm_counter:CNT8_rtl_0|alt_counter_f10ke:wysi_counter|q[0] lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[0] lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[1] lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[2] lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[3] lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[4] lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[5] lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cs_buffer[6] reduce_nor~49 reduce_nor~51 lpm_counter:CNT8_rtl_0|alt_counter_f10ke:wysi_counter|q[7] } { 0.000ns 2.200ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 2.200ns 0.600ns 2.200ns } { 0.000ns 1.200ns 0.300ns 0.300ns 0.300ns 0.300ns 0.300ns 1.300ns 2.300ns 1.800ns 1.200ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK destination 5.300 ns + Shortest register " "Info: + Shortest clock path from clock \"CLK\" to destination register is 5.300 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.800 ns) 2.800 ns CLK 1 CLK PIN_43 16 " "Info: 1: + IC(0.000 ns) + CELL(2.800 ns) = 2.800 ns; Loc. = PIN_43; Fanout = 16; CLK Node = 'CLK'" {  } { { "E:/EDA/DDS/Init_CNT8B/db/INIT_CNT8B_cmp.qrpt" "" { Report "E:/EDA/DDS/Init_CNT8B/db/INIT_CNT8B_cmp.qrpt" Compiler "INIT_CNT8B" "UNKNOWN" "V1" "E:/EDA/DDS/Init_CNT8B/db/INIT_CNT8B.quartus_db" { Floorplan "E:/EDA/DDS/Init_CNT8B/" "" "" { CLK } "NODE_NAME" } "" } } { "INIT_CNT8B.vhd" "" { Text "E:/EDA/DDS/Init_CNT8B/INIT_CNT8B.vhd" 6 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.500 ns) + CELL(0.000 ns) 5.300 ns lpm_counter:CNT8_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[7\] 2 REG LC8_A15 3 " "Info: 2: + IC(2.500 ns) + CELL(0.000 ns) = 5.300 ns; Loc. = LC8_A15; Fanout = 3; REG Node = 'lpm_counter:CNT8_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[7\]'" {  } { { "E:/EDA/DDS/Init_CNT8B/db/INIT_CNT8B_cmp.qrpt" "" { Report "E:/EDA/DDS/Init_CNT8B/db/INIT_CNT8B_cmp.qrpt" Compiler "INIT_CNT8B" "UNKNOWN" "V1" "E:/EDA/DDS/Init_CNT8B/db/INIT_CNT8B.quartus_db" { Floorplan "E:/EDA/DDS/Init_CNT8B/" "" "2.500 ns" { CLK lpm_counter:CNT8_rtl_0|alt_counter_f10ke:wysi_counter|q[7] } "NODE_NAME" } "" } } { "alt_counter_f10ke.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/alt_counter_f10ke.tdf" 271 2 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.800 ns 52.83 % " "Info: Total cell delay = 2.800 ns ( 52.83 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.500 ns 47.17 % " "Info: Total interconnect delay = 2.500 ns ( 47.17 % )" {  } {  } 0}  } { { "E:/EDA/DDS/Init_CNT8B/db/INIT_CNT8B_cmp.qrpt" "" { Report "E:/EDA/DDS/Init_CNT8B/db/INIT_CNT8B_cmp.qrpt" Compiler "INIT_CNT8B" "UNKNOWN" "V1" "E:/EDA/DDS/Init_CNT8B/db/INIT_CNT8B.quartus_db" { Floorplan "E:/EDA/DDS/Init_CNT8B/" "" "5.300 ns" { CLK lpm_counter:CNT8_rtl_0|alt_counter_f10ke:wysi_counter|q[7] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "5.300 ns" { CLK CLK~out lpm_counter:CNT8_rtl_0|alt_counter_f10ke:wysi_counter|q[7] } { 0.000ns 0.000ns 2.500ns } { 0.000ns 2.800ns 0.000ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK source 5.300 ns - Longest register " "Info: - Longest clock path from clock \"CLK\" to source register is 5.300 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.800 ns) 2.800 ns CLK 1 CLK PIN_43 16 " "Info: 1: + IC(0.000 ns) + CELL(2.800 ns) = 2.800 ns; Loc. = PIN_43; Fanout = 16; CLK Node = 'CLK'" {  } { { "E:/EDA/DDS/Init_CNT8B/db/INIT_CNT8B_cmp.qrpt" "" { Report "E:/EDA/DDS/Init_CNT8B/db/INIT_CNT8B_cmp.qrpt" Compiler "INIT_CNT8B" "UNKNOWN" "V1" "E:/EDA/DDS/Init_CNT8B/db/INIT_CNT8B.quartus_db" { Floorplan "E:/EDA/DDS/Init_CNT8B/" "" "" { CLK } "NODE_NAME" } "" } } { "INIT_CNT8B.vhd" "" { Text "E:/EDA/DDS/Init_CNT8B/INIT_CNT8B.vhd" 6 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.500 ns) + CELL(0.000 ns) 5.300 ns lpm_counter:CNT8_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[0\] 2 REG LC1_A15 6 " "Info: 2: + IC(2.500 ns) + CELL(0.000 ns) = 5.300 ns; Loc. = LC1_A15; Fanout = 6; REG Node = 'lpm_counter:CNT8_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[0\]'" {  } { { "E:/EDA/DDS/Init_CNT8B/db/INIT_CNT8B_cmp.qrpt" "" { Report "E:/EDA/DDS/Init_CNT8B/db/INIT_CNT8B_cmp.qrpt" Compiler "INIT_CNT8B" "UNKNOWN" "V1" "E:/EDA/DDS/Init_CNT8B/db/INIT_CNT8B.quartus_db" { Floorplan "E:/EDA/DDS/Init_CNT8B/" "" "2.500 ns" { CLK lpm_counter:CNT8_rtl_0|alt_counter_f10ke:wysi_counter|q[0] } "NODE_NAME" } "" } } { "alt_counter_f10ke.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/alt_counter_f10ke.tdf" 271 2 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.800 ns 52.83 % " "Info: Total cell delay = 2.800 ns ( 52.83 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.500 ns 47.17 % " "Info: Total interconnect delay = 2.500 ns ( 47.17 % )" {  } {  } 0}  } { { "E:/EDA/DDS/Init_CNT8B/db/INIT_CNT8B_cmp.qrpt" "" { Report "E:/EDA/DDS/Init_CNT8B/db/INIT_CNT8B_cmp.qrpt" Compiler "INIT_CNT8B" "UNKNOWN" "V1" "E:/EDA/DDS/Init_CNT8B/db/INIT_CNT8B.quartus_db" { Floorplan "E:/EDA/DDS/Init_CNT8B/" "" "5.300 ns" { CLK lpm_counter:CNT8_rtl_0|alt_counter_f10ke:wysi_counter|q[0] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "5.300 ns" { CLK CLK~out lpm_counter:CNT8_rtl_0|alt_counter_f10ke:wysi_counter|q[0] } { 0.000ns 0.000ns 2.500ns } { 0.000ns 2.800ns 0.000ns } } }  } 0}  } { { "E:/EDA/DDS/Init_CNT8B/db/INIT_CNT8B_cmp.qrpt" "" { Report "E:/EDA/DDS/Init_CNT8B/db/INIT_CNT8B_cmp.qrpt" Compiler "INIT_CNT8B" "UNKNOWN" "V1" "E:/EDA/DDS/Init_CNT8B/db/INIT_CNT8B.quartus_db" { Floorplan "E:/EDA/DDS/Init_CNT8B/" "" "5.300 ns" { CLK lpm_counter:CNT8_rtl_0|alt_counter_f10ke:wysi_counter|q[7] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "5.300 ns" { CLK CLK~out lpm_counter:CNT8_rtl_0|alt_counter_f10ke:wysi_counter|q[7] } { 0.000ns 0.000ns 2.500ns } { 0.000ns 2.800ns 0.000ns } } } { "E:/EDA/DDS/Init_CNT8B/db/INIT_CNT8B_cmp.qrpt" "" { Report "E:/EDA/DDS/Init_CNT8B/db/INIT_CNT8B_cmp.qrpt" Compiler "INIT_CNT8B" "UNKNOWN" "V1" "E:/EDA/DDS/Init_CNT8B/db/INIT_CNT8B.quartus_db" { Floorplan "E:/EDA/DDS/Init_CNT8B/" "" "5.300 ns" { CLK lpm_counter:CNT8_rtl_0|alt_counter_f10ke:wysi_counter|q[0] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "5.300 ns" { CLK CLK~out lpm_counter:CNT8_rtl_0|alt_counter_f10ke:wysi_counter|q[0] } { 0.000ns 0.000ns 2.500ns } { 0.000ns 2.800ns 0.000ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.100 ns + " "Info: + Micro clock to output delay of source is 1.100 ns" {  } { { "alt_counter_f10ke.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/alt_counter_f10ke.tdf" 271 2 0 } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "2.500 ns + " "Info: + Micro setup delay of destination is 2.500 ns" {  } { { "alt_counter_f10ke.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/alt_counter_f10ke.tdf" 271 2 0 } }  } 0}  } { { "E:/EDA/DDS/Init_CNT8B/db/INIT_CNT8B_cmp.qrpt" "" { Report "E:/EDA/DDS/Init_CNT8B/db/INIT_CNT8B_cmp.qrpt" Compiler "INIT_CNT8B" "UNKNOWN" "V1" "E:/EDA/DDS/Init_CNT8B/db/INIT_CNT8B.quartus_db" { Floorplan "E:/EDA/DDS/Init_CNT8B/" "" "16.500 ns" { lpm_counter:CNT8_rtl_0|alt_counter_f10ke:wysi_counter|q[0] lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[0] lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[1] lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[2] lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[3] lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[4] lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[5] lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cs_buffer[6] reduce_nor~49 reduce_nor~51 lpm_counter:CNT8_rtl_0|alt_counter_f10ke:wysi_counter|q[7] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "16.500 ns" { lpm_counter:CNT8_rtl_0|alt_counter_f10ke:wysi_counter|q[0] lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[0] lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[1] lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[2] lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[3] lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[4] lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[5] lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cs_buffer[6] reduce_nor~49 reduce_nor~51 lpm_counter:CNT8_rtl_0|alt_counter_f10ke:wysi_counter|q[7] } { 0.000ns 2.200ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 2.200ns 0.600ns 2.200ns } { 0.000ns 1.200ns 0.300ns 0.300ns 0.300ns 0.300ns 0.300ns 1.300ns 2.300ns 1.800ns 1.200ns } } } { "E:/EDA/DDS/Init_CNT8B/db/INIT_CNT8B_cmp.qrpt" "" { Report "E:/EDA/DDS/Init_CNT8B/db/INIT_CNT8B_cmp.qrpt" Compiler "INIT_CNT8B" "UNKNOWN" "V1" "E:/EDA/DDS/Init_CNT8B/db/INIT_CNT8B.quartus_db" { Floorplan "E:/EDA/DDS/Init_CNT8B/" "" "5.300 ns" { CLK lpm_counter:CNT8_rtl_0|alt_counter_f10ke:wysi_counter|q[7] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "5.300 ns" { CLK CLK~out lpm_counter:CNT8_rtl_0|alt_counter_f10ke:wysi_counter|q[7] } { 0.000ns 0.000ns 2.500ns } { 0.000ns 2.800ns 0.000ns } } } { "E:/EDA/DDS/Init_CNT8B/db/INIT_CNT8B_cmp.qrpt" "" { Report "E:/EDA/DDS/Init_CNT8B/db/INIT_CNT8B_cmp.qrpt" Compiler "INIT_CNT8B" "UNKNOWN" "V1" "E:/EDA/DDS/Init_CNT8B/db/INIT_CNT8B.quartus_db" { Floorplan "E:/EDA/DDS/Init_CNT8B/" "" "5.300 ns" { CLK lpm_counter:CNT8_rtl_0|alt_counter_f10ke:wysi_counter|q[0] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "5.300 ns" { CLK CLK~out lpm_counter:CNT8_rtl_0|alt_counter_f10ke:wysi_counter|q[0] } { 0.000ns 0.000ns 2.500ns } { 0.000ns 2.800ns 0.000ns } } }  } 0}
{ "Info" "ITDB_TSU_RESULT" "lpm_counter:CNT8_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[6\] DATA\[6\] CLK 5.200 ns register " "Info: tsu for register \"lpm_counter:CNT8_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[6\]\" (data pin = \"DATA\[6\]\", clock pin = \"CLK\") is 5.200 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "8.000 ns + Longest pin register " "Info: + Longest pin to register delay is 8.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.500 ns) 3.500 ns DATA\[6\] 1 PIN PIN_18 2 " "Info: 1: + IC(0.000 ns) + CELL(3.500 ns) = 3.500 ns; Loc. = PIN_18; Fanout = 2; PIN Node = 'DATA\[6\]'" {  } { { "E:/EDA/DDS/Init_CNT8B/db/INIT_CNT8B_cmp.qrpt" "" { Report "E:/EDA/DDS/Init_CNT8B/db/INIT_CNT8B_cmp.qrpt" Compiler "INIT_CNT8B" "UNKNOWN" "V1" "E:/EDA/DDS/Init_CNT8B/db/INIT_CNT8B.quartus_db" { Floorplan "E:/EDA/DDS/Init_CNT8B/" "" "" { DATA[6] } "NODE_NAME" } "" } } { "INIT_CNT8B.vhd" "" { Text "E:/EDA/DDS/Init_CNT8B/INIT_CNT8B.vhd" 7 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.800 ns) + CELL(1.700 ns) 8.000 ns lpm_counter:CNT8_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[6\] 2 REG LC7_A15 6 " "Info: 2: + IC(2.800 ns) + CELL(1.700 ns) = 8.000 ns; Loc. = LC7_A15; Fanout = 6; REG Node = 'lpm_counter:CNT8_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[6\]'" {  } { { "E:/EDA/DDS/Init_CNT8B/db/INIT_CNT8B_cmp.qrpt" "" { Report "E:/EDA/DDS/Init_CNT8B/db/INIT_CNT8B_cmp.qrpt" Compiler "INIT_CNT8B" "UNKNOWN" "V1" "E:/EDA/DDS/Init_CNT8B/db/INIT_CNT8B.quartus_db" { Floorplan "E:/EDA/DDS/Init_CNT8B/" "" "4.500 ns" { DATA[6] lpm_counter:CNT8_rtl_0|alt_counter_f10ke:wysi_counter|q[6] } "NODE_NAME" } "" } } { "alt_counter_f10ke.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/alt_counter_f10ke.tdf" 271 2 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "5.200 ns 65.00 % " "Info: Total cell delay = 5.200 ns ( 65.00 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.800 ns 35.00 % " "Info: Total interconnect delay = 2.800 ns ( 35.00 % )" {  } {  } 0}  } { { "E:/EDA/DDS/Init_CNT8B/db/INIT_CNT8B_cmp.qrpt" "" { Report "E:/EDA/DDS/Init_CNT8B/db/INIT_CNT8B_cmp.qrpt" Compiler "INIT_CNT8B" "UNKNOWN" "V1" "E:/EDA/DDS/Init_CNT8B/db/INIT_CNT8B.quartus_db" { Floorplan "E:/EDA/DDS/Init_CNT8B/" "" "8.000 ns" { DATA[6] lpm_counter:CNT8_rtl_0|alt_counter_f10ke:wysi_counter|q[6] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "8.000 ns" { DATA[6] DATA[6]~out lpm_counter:CNT8_rtl_0|alt_counter_f10ke:wysi_counter|q[6] } { 0.000ns 0.000ns 2.800ns } { 0.000ns 3.500ns 1.700ns } } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "2.500 ns + " "Info: + Micro setup delay of destination is 2.500 ns" {  } { { "alt_counter_f10ke.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/alt_counter_f10ke.tdf" 271 2 0 } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK destination 5.300 ns - Shortest register " "Info: - Shortest clock path from clock \"CLK\" to destination register is 5.300 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.800 ns) 2.800 ns CLK 1 CLK PIN_43 16 " "Info: 1: + IC(0.000 ns) + CELL(2.800 ns) = 2.800 ns; Loc. = PIN_43; Fanout = 16; CLK Node = 'CLK'" {  } { { "E:/EDA/DDS/Init_CNT8B/db/INIT_CNT8B_cmp.qrpt" "" { Report "E:/EDA/DDS/Init_CNT8B/db/INIT_CNT8B_cmp.qrpt" Compiler "INIT_CNT8B" "UNKNOWN" "V1" "E:/EDA/DDS/Init_CNT8B/db/INIT_CNT8B.quartus_db" { Floorplan "E:/EDA/DDS/Init_CNT8B/" "" "" { CLK } "NODE_NAME" } "" } } { "INIT_CNT8B.vhd" "" { Text "E:/EDA/DDS/Init_CNT8B/INIT_CNT8B.vhd" 6 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.500 ns) + CELL(0.000 ns) 5.300 ns lpm_counter:CNT8_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[6\] 2 REG LC7_A15 6 " "Info: 2: + IC(2.500 ns) + CELL(0.000 ns) = 5.300 ns; Loc. = LC7_A15; Fanout = 6; REG Node = 'lpm_counter:CNT8_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[6\]'" {  } { { "E:/EDA/DDS/Init_CNT8B/db/INIT_CNT8B_cmp.qrpt" "" { Report "E:/EDA/DDS/Init_CNT8B/db/INIT_CNT8B_cmp.qrpt" Compiler "INIT_CNT8B" "UNKNOWN" "V1" "E:/EDA/DDS/Init_CNT8B/db/INIT_CNT8B.quartus_db" { Floorplan "E:/EDA/DDS/Init_CNT8B/" "" "2.500 ns" { CLK lpm_counter:CNT8_rtl_0|alt_counter_f10ke:wysi_counter|q[6] } "NODE_NAME" } "" } } { "alt_counter_f10ke.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/alt_counter_f10ke.tdf" 271 2 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.800 ns 52.83 % " "Info: Total cell delay = 2.800 ns ( 52.83 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.500 ns 47.17 % " "Info: Total interconnect delay = 2.500 ns ( 47.17 % )" {  } {  } 0}  } { { "E:/EDA/DDS/Init_CNT8B/db/INIT_CNT8B_cmp.qrpt" "" { Report "E:/EDA/DDS/Init_CNT8B/db/INIT_CNT8B_cmp.qrpt" Compiler "INIT_CNT8B" "UNKNOWN" "V1" "E:/EDA/DDS/Init_CNT8B/db/INIT_CNT8B.quartus_db" { Floorplan "E:/EDA/DDS/Init_CNT8B/" "" "5.300 ns" { CLK lpm_counter:CNT8_rtl_0|alt_counter_f10ke:wysi_counter|q[6] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "5.300 ns" { CLK CLK~out lpm_counter:CNT8_rtl_0|alt_counter_f10ke:wysi_counter|q[6] } { 0.000ns 0.000ns 2.500ns } { 0.000ns 2.800ns 0.000ns } } }  } 0}  } { { "E:/EDA/DDS/Init_CNT8B/db/INIT_CNT8B_cmp.qrpt" "" { Report "E:/EDA/DDS/Init_CNT8B/db/INIT_CNT8B_cmp.qrpt" Compiler "INIT_CNT8B" "UNKNOWN" "V1" "E:/EDA/DDS/Init_CNT8B/db/INIT_CNT8B.quartus_db" { Floorplan "E:/EDA/DDS/Init_CNT8B/" "" "8.000 ns" { DATA[6] lpm_counter:CNT8_rtl_0|alt_counter_f10ke:wysi_counter|q[6] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "8.000 ns" { DATA[6] DATA[6]~out lpm_counter:CNT8_rtl_0|alt_counter_f10ke:wysi_counter|q[6] } { 0.000ns 0.000ns 2.800ns } { 0.000ns 3.500ns 1.700ns } } } { "E:/EDA/DDS/Init_CNT8B/db/INIT_CNT8B_cmp.qrpt" "" { Report "E:/EDA/DDS/Init_CNT8B/db/INIT_CNT8B_cmp.qrpt" Compiler "INIT_CNT8B" "UNKNOWN" "V1" "E:/EDA/DDS/Init_CNT8B/db/INIT_CNT8B.quartus_db" { Floorplan "E:/EDA/DDS/Init_CNT8B/" "" "5.300 ns" { CLK lpm_counter:CNT8_rtl_0|alt_counter_f10ke:wysi_counter|q[6] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "5.300 ns" { CLK CLK~out lpm_counter:CNT8_rtl_0|alt_counter_f10ke:wysi_counter|q[6] } { 0.000ns 0.000ns 2.500ns } { 0.000ns 2.800ns 0.000ns } } }  } 0}