divf16_sinx.tan.qmsg

来自「在EDA开发软件QuartusII上利用VHDL语言实现DDS信号发生器」· QMSG 代码 · 共 13 行 · 第 1/3 页

{ "Info" "ITDB_TH_RESULT" "divf:u1\|lpm_counter:CNT4_rtl_1\|alt_counter_f10ke:wysi_counter\|q\[2\] datain\[2\] clkin 0.800 ns register " "Info: th for register \"divf:u1\|lpm_counter:CNT4_rtl_1\|alt_counter_f10ke:wysi_counter\|q\[2\]\" (data pin = \"datain\[2\]\", clock pin = \"clkin\") is 0.800 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clkin destination 5.300 ns + Longest register " "Info: + Longest clock path from clock \"clkin\" to destination register is 5.300 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.800 ns) 2.800 ns clkin 1 CLK PIN_43 8 " "Info: 1: + IC(0.000 ns) + CELL(2.800 ns) = 2.800 ns; Loc. = PIN_43; Fanout = 8; CLK Node = 'clkin'" {  } { { "E:/EDA/DDS/10k844/divf16_sinx/db/divf16_sinx_cmp.qrpt" "" { Report "E:/EDA/DDS/10k844/divf16_sinx/db/divf16_sinx_cmp.qrpt" Compiler "divf16_sinx" "UNKNOWN" "V1" "E:/EDA/DDS/10k844/divf16_sinx/db/divf16_sinx.quartus_db" { Floorplan "E:/EDA/DDS/10k844/divf16_sinx/" "" "" { clkin } "NODE_NAME" } "" } } { "divf16_sinx.vhd" "" { Text "E:/EDA/DDS/10k844/divf16_sinx/divf16_sinx.vhd" 6 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.500 ns) + CELL(0.000 ns) 5.300 ns divf:u1\|lpm_counter:CNT4_rtl_1\|alt_counter_f10ke:wysi_counter\|q\[2\] 2 REG LC6_C6 5 " "Info: 2: + IC(2.500 ns) + CELL(0.000 ns) = 5.300 ns; Loc. = LC6_C6; Fanout = 5; REG Node = 'divf:u1\|lpm_counter:CNT4_rtl_1\|alt_counter_f10ke:wysi_counter\|q\[2\]'" {  } { { "E:/EDA/DDS/10k844/divf16_sinx/db/divf16_sinx_cmp.qrpt" "" { Report "E:/EDA/DDS/10k844/divf16_sinx/db/divf16_sinx_cmp.qrpt" Compiler "divf16_sinx" "UNKNOWN" "V1" "E:/EDA/DDS/10k844/divf16_sinx/db/divf16_sinx.quartus_db" { Floorplan "E:/EDA/DDS/10k844/divf16_sinx/" "" "2.500 ns" { clkin divf:u1|lpm_counter:CNT4_rtl_1|alt_counter_f10ke:wysi_counter|q[2] } "NODE_NAME" } "" } } { "alt_counter_f10ke.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/alt_counter_f10ke.tdf" 271 2 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.800 ns 52.83 % " "Info: Total cell delay = 2.800 ns ( 52.83 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.500 ns 47.17 % " "Info: Total interconnect delay = 2.500 ns ( 47.17 % )" {  } {  } 0}  } { { "E:/EDA/DDS/10k844/divf16_sinx/db/divf16_sinx_cmp.qrpt" "" { Report "E:/EDA/DDS/10k844/divf16_sinx/db/divf16_sinx_cmp.qrpt" Compiler "divf16_sinx" "UNKNOWN" "V1" "E:/EDA/DDS/10k844/divf16_sinx/db/divf16_sinx.quartus_db" { Floorplan "E:/EDA/DDS/10k844/divf16_sinx/" "" "5.300 ns" { clkin divf:u1|lpm_counter:CNT4_rtl_1|alt_counter_f10ke:wysi_counter|q[2] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "5.300 ns" { clkin clkin~out divf:u1|lpm_counter:CNT4_rtl_1|alt_counter_f10ke:wysi_counter|q[2] } { 0.000ns 0.000ns 2.500ns } { 0.000ns 2.800ns 0.000ns } } }  } 0} { "Info" "ITDB_FULL_TH_DELAY" "1.600 ns + " "Info: + Micro hold delay of destination is 1.600 ns" {  } { { "alt_counter_f10ke.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/alt_counter_f10ke.tdf" 271 2 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.100 ns - Shortest pin register " "Info: - Shortest pin to register delay is 6.100 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.800 ns) 2.800 ns datain\[2\] 1 PIN PIN_44 2 " "Info: 1: + IC(0.000 ns) + CELL(2.800 ns) = 2.800 ns; Loc. = PIN_44; Fanout = 2; PIN Node = 'datain\[2\]'" {  } { { "E:/EDA/DDS/10k844/divf16_sinx/db/divf16_sinx_cmp.qrpt" "" { Report "E:/EDA/DDS/10k844/divf16_sinx/db/divf16_sinx_cmp.qrpt" Compiler "divf16_sinx" "UNKNOWN" "V1" "E:/EDA/DDS/10k844/divf16_sinx/db/divf16_sinx.quartus_db" { Floorplan "E:/EDA/DDS/10k844/divf16_sinx/" "" "" { datain[2] } "NODE_NAME" } "" } } { "divf16_sinx.vhd" "" { Text "E:/EDA/DDS/10k844/divf16_sinx/divf16_sinx.vhd" 7 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.600 ns) + CELL(1.700 ns) 6.100 ns divf:u1\|lpm_counter:CNT4_rtl_1\|alt_counter_f10ke:wysi_counter\|q\[2\] 2 REG LC6_C6 5 " "Info: 2: + IC(1.600 ns) + CELL(1.700 ns) = 6.100 ns; Loc. = LC6_C6; Fanout = 5; REG Node = 'divf:u1\|lpm_counter:CNT4_rtl_1\|alt_counter_f10ke:wysi_counter\|q\[2\]'" {  } { { "E:/EDA/DDS/10k844/divf16_sinx/db/divf16_sinx_cmp.qrpt" "" { Report "E:/EDA/DDS/10k844/divf16_sinx/db/divf16_sinx_cmp.qrpt" Compiler "divf16_sinx" "UNKNOWN" "V1" "E:/EDA/DDS/10k844/divf16_sinx/db/divf16_sinx.quartus_db" { Floorplan "E:/EDA/DDS/10k844/divf16_sinx/" "" "3.300 ns" { datain[2] divf:u1|lpm_counter:CNT4_rtl_1|alt_counter_f10ke:wysi_counter|q[2] } "NODE_NAME" } "" } } { "alt_counter_f10ke.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/alt_counter_f10ke.tdf" 271 2 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.500 ns 73.77 % " "Info: Total cell delay = 4.500 ns ( 73.77 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.600 ns 26.23 % " "Info: Total interconnect delay = 1.600 ns ( 26.23 % )" {  } {  } 0}  } { { "E:/EDA/DDS/10k844/divf16_sinx/db/divf16_sinx_cmp.qrpt" "" { Report "E:/EDA/DDS/10k844/divf16_sinx/db/divf16_sinx_cmp.qrpt" Compiler "divf16_sinx" "UNKNOWN" "V1" "E:/EDA/DDS/10k844/divf16_sinx/db/divf16_sinx.quartus_db" { Floorplan "E:/EDA/DDS/10k844/divf16_sinx/" "" "6.100 ns" { datain[2] divf:u1|lpm_counter:CNT4_rtl_1|alt_counter_f10ke:wysi_counter|q[2] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "6.100 ns" { datain[2] datain[2]~out divf:u1|lpm_counter:CNT4_rtl_1|alt_counter_f10ke:wysi_counter|q[2] } { 0.000ns 0.000ns 1.600ns } { 0.000ns 2.800ns 1.700ns } } }  } 0}  } { { "E:/EDA/DDS/10k844/divf16_sinx/db/divf16_sinx_cmp.qrpt" "" { Report "E:/EDA/DDS/10k844/divf16_sinx/db/divf16_sinx_cmp.qrpt" Compiler "divf16_sinx" "UNKNOWN" "V1" "E:/EDA/DDS/10k844/divf16_sinx/db/divf16_sinx.quartus_db" { Floorplan "E:/EDA/DDS/10k844/divf16_sinx/" "" "5.300 ns" { clkin divf:u1|lpm_counter:CNT4_rtl_1|alt_counter_f10ke:wysi_counter|q[2] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "5.300 ns" { clkin clkin~out divf:u1|lpm_counter:CNT4_rtl_1|alt_counter_f10ke:wysi_counter|q[2] } { 0.000ns 0.000ns 2.500ns } { 0.000ns 2.800ns 0.000ns } } } { "E:/EDA/DDS/10k844/divf16_sinx/db/divf16_sinx_cmp.qrpt" "" { Report "E:/EDA/DDS/10k844/divf16_sinx/db/divf16_sinx_cmp.qrpt" Compiler "divf16_sinx" "UNKNOWN" "V1" "E:/EDA/DDS/10k844/divf16_sinx/db/divf16_sinx.quartus_db" { Floorplan "E:/EDA/DDS/10k844/divf16_sinx/" "" "6.100 ns" { datain[2] divf:u1|lpm_counter:CNT4_rtl_1|alt_counter_f10ke:wysi_counter|q[2] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "6.100 ns" { datain[2] datain[2]~out divf:u1|lpm_counter:CNT4_rtl_1|alt_counter_f10ke:wysi_counter|q[2] } { 0.000ns 0.000ns 1.600ns } { 0.000ns 2.800ns 1.700ns } } }  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 2 s Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Fri Apr 14 21:04:39 2006 " "Info: Processing ended: Fri Apr 14 21:04:39 2006" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Info: Elapsed time: 00:00:03" {  } {  } 0}  } {  } 0}