divf16_sinx.tan.qmsg

来自「在EDA开发软件QuartusII上利用VHDL语言实现DDS信号发生器」· QMSG 代码 · 共 13 行 · 第 1/3 页
QMSG
13 行
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clkin " "Info: Assuming node \"clkin\" is an undefined clock" {  } { { "divf16_sinx.vhd" "" { Text "E:/EDA/DDS/10k844/divf16_sinx/divf16_sinx.vhd" 6 -1 0 } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "clkin" } } } }  } 0}  } {  } 0}
{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "1 " "Warning: Found 1 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "divf:u1\|COUT " "Info: Detected ripple clock \"divf:u1\|COUT\" as buffer" {  } { { "divf.vhd" "" { Text "E:/EDA/DDS/10k844/divf16_sinx/divf.vhd" 9 -1 0 } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "divf:u1\|COUT" } } } }  } 0}  } {  } 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clkin register singt3:u2\|lpm_counter:q_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[4\] register singt3:u2\|lpm_counter:q_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[6\] 65.36 MHz 15.3 ns Internal " "Info: Clock \"clkin\" has Internal fmax of 65.36 MHz between source register \"singt3:u2\|lpm_counter:q_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[4\]\" and destination register \"singt3:u2\|lpm_counter:q_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[6\]\" (period= 15.3 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "11.700 ns + Longest register register " "Info: + Longest register to register delay is 11.700 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns singt3:u2\|lpm_counter:q_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[4\] 1 REG LC5_B14 31 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC5_B14; Fanout = 31; REG Node = 'singt3:u2\|lpm_counter:q_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[4\]'" {  } { { "E:/EDA/DDS/10k844/divf16_sinx/db/divf16_sinx_cmp.qrpt" "" { Report "E:/EDA/DDS/10k844/divf16_sinx/db/divf16_sinx_cmp.qrpt" Compiler "divf16_sinx" "UNKNOWN" "V1" "E:/EDA/DDS/10k844/divf16_sinx/db/divf16_sinx.quartus_db" { Floorplan "E:/EDA/DDS/10k844/divf16_sinx/" "" "" { singt3:u2|lpm_counter:q_rtl_0|alt_counter_f10ke:wysi_counter|q[4] } "NODE_NAME" } "" } } { "alt_counter_f10ke.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/alt_counter_f10ke.tdf" 271 2 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.200 ns) + CELL(1.700 ns) 3.900 ns singt3:u2\|LessThan~60 2 COMB LC7_B13 1 " "Info: 2: + IC(2.200 ns) + CELL(1.700 ns) = 3.900 ns; Loc. = LC7_B13; Fanout = 1; COMB Node = 'singt3:u2\|LessThan~60'" {  } { { "E:/EDA/DDS/10k844/divf16_sinx/db/divf16_sinx_cmp.qrpt" "" { Report "E:/EDA/DDS/10k844/divf16_sinx/db/divf16_sinx_cmp.qrpt" Compiler "divf16_sinx" "UNKNOWN" "V1" "E:/EDA/DDS/10k844/divf16_sinx/db/divf16_sinx.quartus_db" { Floorplan "E:/EDA/DDS/10k844/divf16_sinx/" "" "3.900 ns" { singt3:u2|lpm_counter:q_rtl_0|alt_counter_f10ke:wysi_counter|q[4] singt3:u2|LessThan~60 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.500 ns) 5.400 ns singt3:u2\|LessThan~56 3 COMB LC8_B13 1 " "Info: 3: + IC(0.000 ns) + CELL(1.500 ns) = 5.400 ns; Loc. = LC8_B13; Fanout = 1; COMB Node = 'singt3:u2\|LessThan~56'" {  } { { "E:/EDA/DDS/10k844/divf16_sinx/db/divf16_sinx_cmp.qrpt" "" { Report "E:/EDA/DDS/10k844/divf16_sinx/db/divf16_sinx_cmp.qrpt" Compiler "divf16_sinx" "UNKNOWN" "V1" "E:/EDA/DDS/10k844/divf16_sinx/db/divf16_sinx.quartus_db" { Floorplan "E:/EDA/DDS/10k844/divf16_sinx/" "" "1.500 ns" { singt3:u2|LessThan~60 singt3:u2|LessThan~56 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.200 ns) + CELL(1.800 ns) 9.400 ns singt3:u2\|LessThan~58 4 COMB LC8_B14 11 " "Info: 4: + IC(2.200 ns) + CELL(1.800 ns) = 9.400 ns; Loc. = LC8_B14; Fanout = 11; COMB Node = 'singt3:u2\|LessThan~58'" {  } { { "E:/EDA/DDS/10k844/divf16_sinx/db/divf16_sinx_cmp.qrpt" "" { Report "E:/EDA/DDS/10k844/divf16_sinx/db/divf16_sinx_cmp.qrpt" Compiler "divf16_sinx" "UNKNOWN" "V1" "E:/EDA/DDS/10k844/divf16_sinx/db/divf16_sinx.quartus_db" { Floorplan "E:/EDA/DDS/10k844/divf16_sinx/" "" "4.000 ns" { singt3:u2|LessThan~56 singt3:u2|LessThan~58 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.600 ns) + CELL(1.700 ns) 11.700 ns singt3:u2\|lpm_counter:q_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[6\] 5 REG LC7_B14 10 " "Info: 5: + IC(0.600 ns) + CELL(1.700 ns) = 11.700 ns; Loc. = LC7_B14; Fanout = 10; REG Node = 'singt3:u2\|lpm_counter:q_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[6\]'" {  } { { "E:/EDA/DDS/10k844/divf16_sinx/db/divf16_sinx_cmp.qrpt" "" { Report "E:/EDA/DDS/10k844/divf16_sinx/db/divf16_sinx_cmp.qrpt" Compiler "divf16_sinx" "UNKNOWN" "V1" "E:/EDA/DDS/10k844/divf16_sinx/db/divf16_sinx.quartus_db" { Floorplan "E:/EDA/DDS/10k844/divf16_sinx/" "" "2.300 ns" { singt3:u2|LessThan~58 singt3:u2|lpm_counter:q_rtl_0|alt_counter_f10ke:wysi_counter|q[6] } "NODE_NAME" } "" } } { "alt_counter_f10ke.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/alt_counter_f10ke.tdf" 271 2 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "6.700 ns 57.26 % " "Info: Total cell delay = 6.700 ns ( 57.26 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.000 ns 42.74 % " "Info: Total interconnect delay = 5.000 ns ( 42.74 % )" {  } {  } 0}  } { { "E:/EDA/DDS/10k844/divf16_sinx/db/divf16_sinx_cmp.qrpt" "" { Report "E:/EDA/DDS/10k844/divf16_sinx/db/divf16_sinx_cmp.qrpt" Compiler "divf16_sinx" "UNKNOWN" "V1" "E:/EDA/DDS/10k844/divf16_sinx/db/divf16_sinx.quartus_db" { Floorplan "E:/EDA/DDS/10k844/divf16_sinx/" "" "11.700 ns" { singt3:u2|lpm_counter:q_rtl_0|alt_counter_f10ke:wysi_counter|q[4] singt3:u2|LessThan~60 singt3:u2|LessThan~56 singt3:u2|LessThan~58 singt3:u2|lpm_counter:q_rtl_0|alt_counter_f10ke:wysi_counter|q[6] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "11.700 ns" { singt3:u2|lpm_counter:q_rtl_0|alt_counter_f10ke:wysi_counter|q[4] singt3:u2|LessThan~60 singt3:u2|LessThan~56 singt3:u2|LessThan~58 singt3:u2|lpm_counter:q_rtl_0|alt_counter_f10ke:wysi_counter|q[6] } { 0.000ns 2.200ns 0.000ns 2.200ns 0.600ns } { 0.000ns 1.700ns 1.500ns 1.800ns 1.700ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clkin destination 11.900 ns + Shortest register " "Info: + Shortest clock path from clock \"clkin\" to destination register is 11.900 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.800 ns) 2.800 ns clkin 1 CLK PIN_43 8 " "Info: 1: + IC(0.000 ns) + CELL(2.800 ns) = 2.800 ns; Loc. = PIN_43; Fanout = 8; CLK Node = 'clkin'" {  } { { "E:/EDA/DDS/10k844/divf16_sinx/db/divf16_sinx_cmp.qrpt" "" { Report "E:/EDA/DDS/10k844/divf16_sinx/db/divf16_sinx_cmp.qrpt" Compiler "divf16_sinx" "UNKNOWN" "V1" "E:/EDA/DDS/10k844/divf16_sinx/db/divf16_sinx.quartus_db" { Floorplan "E:/EDA/DDS/10k844/divf16_sinx/" "" "" { clkin } "NODE_NAME" } "" } } { "divf16_sinx.vhd" "" { Text "E:/EDA/DDS/10k844/divf16_sinx/divf16_sinx.vhd" 6 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.500 ns) + CELL(1.100 ns) 6.400 ns divf:u1\|COUT 2 REG LC1_C6 11 " "Info: 2: + IC(2.500 ns) + CELL(1.100 ns) = 6.400 ns; Loc. = LC1_C6; Fanout = 11; REG Node = 'divf:u1\|COUT'" {  } { { "E:/EDA/DDS/10k844/divf16_sinx/db/divf16_sinx_cmp.qrpt" "" { Report "E:/EDA/DDS/10k844/divf16_sinx/db/divf16_sinx_cmp.qrpt" Compiler "divf16_sinx" "UNKNOWN" "V1" "E:/EDA/DDS/10k844/divf16_sinx/db/divf16_sinx.quartus_db" { Floorplan "E:/EDA/DDS/10k844/divf16_sinx/" "" "3.600 ns" { clkin divf:u1|COUT } "NODE_NAME" } "" } } { "divf.vhd" "" { Text "E:/EDA/DDS/10k844/divf16_sinx/divf.vhd" 9 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(5.500 ns) + CELL(0.000 ns) 11.900 ns singt3:u2\|lpm_counter:q_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[6\] 3 REG LC7_B14 10 " "Info: 3: + IC(5.500 ns) + CELL(0.000 ns) = 11.900 ns; Loc. = LC7_B14; Fanout = 10; REG Node = 'singt3:u2\|lpm_counter:q_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[6\]'" {  } { { "E:/EDA/DDS/10k844/divf16_sinx/db/divf16_sinx_cmp.qrpt" "" { Report "E:/EDA/DDS/10k844/divf16_sinx/db/divf16_sinx_cmp.qrpt" Compiler "divf16_sinx" "UNKNOWN" "V1" "E:/EDA/DDS/10k844/divf16_sinx/db/divf16_sinx.quartus_db" { Floorplan "E:/EDA/DDS/10k844/divf16_sinx/" "" "5.500 ns" { divf:u1|COUT singt3:u2|lpm_counter:q_rtl_0|alt_counter_f10ke:wysi_counter|q[6] } "NODE_NAME" } "" } } { "alt_counter_f10ke.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/alt_counter_f10ke.tdf" 271 2 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.900 ns 32.77 % " "Info: Total cell delay = 3.900 ns ( 32.77 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "8.000 ns 67.23 % " "Info: Total interconnect delay = 8.000 ns ( 67.23 % )" {  } {  } 0}  } { { "E:/EDA/DDS/10k844/divf16_sinx/db/divf16_sinx_cmp.qrpt" "" { Report "E:/EDA/DDS/10k844/divf16_sinx/db/divf16_sinx_cmp.qrpt" Compiler "divf16_sinx" "UNKNOWN" "V1" "E:/EDA/DDS/10k844/divf16_sinx/db/divf16_sinx.quartus_db" { Floorplan "E:/EDA/DDS/10k844/divf16_sinx/" "" "11.900 ns" { clkin divf:u1|COUT singt3:u2|lpm_counter:q_rtl_0|alt_counter_f10ke:wysi_counter|q[6] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "11.900 ns" { clkin clkin~out divf:u1|COUT singt3:u2|lpm_counter:q_rtl_0|alt_counter_f10ke:wysi_counter|q[6] } { 0.000ns 0.000ns 2.500ns 5.500ns } { 0.000ns 2.800ns 1.100ns 0.000ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clkin source 11.900 ns - Longest register " "Info: - Longest clock path from clock \"clkin\" to source register is 11.900 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.800 ns) 2.800 ns clkin 1 CLK PIN_43 8 " "Info: 1: + IC(0.000 ns) + CELL(2.800 ns) = 2.800 ns; Loc. = PIN_43; Fanout = 8; CLK Node = 'clkin'" {  } { { "E:/EDA/DDS/10k844/divf16_sinx/db/divf16_sinx_cmp.qrpt" "" { Report "E:/EDA/DDS/10k844/divf16_sinx/db/divf16_sinx_cmp.qrpt" Compiler "divf16_sinx" "UNKNOWN" "V1" "E:/EDA/DDS/10k844/divf16_sinx/db/divf16_sinx.quartus_db" { Floorplan "E:/EDA/DDS/10k844/divf16_sinx/" "" "" { clkin } "NODE_NAME" } "" } } { "divf16_sinx.vhd" "" { Text "E:/EDA/DDS/10k844/divf16_sinx/divf16_sinx.vhd" 6 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.500 ns) + CELL(1.100 ns) 6.400 ns divf:u1\|COUT 2 REG LC1_C6 11 " "Info: 2: + IC(2.500 ns) + CELL(1.100 ns) = 6.400 ns; Loc. = LC1_C6; Fanout = 11; REG Node = 'divf:u1\|COUT'" {  } { { "E:/EDA/DDS/10k844/divf16_sinx/db/divf16_sinx_cmp.qrpt" "" { Report "E:/EDA/DDS/10k844/divf16_sinx/db/divf16_sinx_cmp.qrpt" Compiler "divf16_sinx" "UNKNOWN" "V1" "E:/EDA/DDS/10k844/divf16_sinx/db/divf16_sinx.quartus_db" { Floorplan "E:/EDA/DDS/10k844/divf16_sinx/" "" "3.600 ns" { clkin divf:u1|COUT } "NODE_NAME" } "" } } { "divf.vhd" "" { Text "E:/EDA/DDS/10k844/divf16_sinx/divf.vhd" 9 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(5.500 ns) + CELL(0.000 ns) 11.900 ns singt3:u2\|lpm_counter:q_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[4\] 3 REG LC5_B14 31 " "Info: 3: + IC(5.500 ns) + CELL(0.000 ns) = 11.900 ns; Loc. = LC5_B14; Fanout = 31; REG Node = 'singt3:u2\|lpm_counter:q_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[4\]'" {  } { { "E:/EDA/DDS/10k844/divf16_sinx/db/divf16_sinx_cmp.qrpt" "" { Report "E:/EDA/DDS/10k844/divf16_sinx/db/divf16_sinx_cmp.qrpt" Compiler "divf16_sinx" "UNKNOWN" "V1" "E:/EDA/DDS/10k844/divf16_sinx/db/divf16_sinx.quartus_db" { Floorplan "E:/EDA/DDS/10k844/divf16_sinx/" "" "5.500 ns" { divf:u1|COUT singt3:u2|lpm_counter:q_rtl_0|alt_counter_f10ke:wysi_counter|q[4] } "NODE_NAME" } "" } } { "alt_counter_f10ke.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/alt_counter_f10ke.tdf" 271 2 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.900 ns 32.77 % " "Info: Total cell delay = 3.900 ns ( 32.77 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "8.000 ns 67.23 % " "Info: Total interconnect delay = 8.000 ns ( 67.23 % )" {  } {  } 0}  } { { "E:/EDA/DDS/10k844/divf16_sinx/db/divf16_sinx_cmp.qrpt" "" { Report "E:/EDA/DDS/10k844/divf16_sinx/db/divf16_sinx_cmp.qrpt" Compiler "divf16_sinx" "UNKNOWN" "V1" "E:/EDA/DDS/10k844/divf16_sinx/db/divf16_sinx.quartus_db" { Floorplan "E:/EDA/DDS/10k844/divf16_sinx/" "" "11.900 ns" { clkin divf:u1|COUT singt3:u2|lpm_counter:q_rtl_0|alt_counter_f10ke:wysi_counter|q[4] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "11.900 ns" { clkin clkin~out divf:u1|COUT singt3:u2|lpm_counter:q_rtl_0|alt_counter_f10ke:wysi_counter|q[4] } { 0.000ns 0.000ns 2.500ns 5.500ns } { 0.000ns 2.800ns 1.100ns 0.000ns } } }  } 0}  } { { "E:/EDA/DDS/10k844/divf16_sinx/db/divf16_sinx_cmp.qrpt" "" { Report "E:/EDA/DDS/10k844/divf16_sinx/db/divf16_sinx_cmp.qrpt" Compiler "divf16_sinx" "UNKNOWN" "V1" "E:/EDA/DDS/10k844/divf16_sinx/db/divf16_sinx.quartus_db" { Floorplan "E:/EDA/DDS/10k844/divf16_sinx/" "" "11.900 ns" { clkin divf:u1|COUT singt3:u2|lpm_counter:q_rtl_0|alt_counter_f10ke:wysi_counter|q[6] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "11.900 ns" { clkin clkin~out divf:u1|COUT singt3:u2|lpm_counter:q_rtl_0|alt_counter_f10ke:wysi_counter|q[6] } { 0.000ns 0.000ns 2.500ns 5.500ns } { 0.000ns 2.800ns 1.100ns 0.000ns } } } { "E:/EDA/DDS/10k844/divf16_sinx/db/divf16_sinx_cmp.qrpt" "" { Report "E:/EDA/DDS/10k844/divf16_sinx/db/divf16_sinx_cmp.qrpt" Compiler "divf16_sinx" "UNKNOWN" "V1" "E:/EDA/DDS/10k844/divf16_sinx/db/divf16_sinx.quartus_db" { Floorplan "E:/EDA/DDS/10k844/divf16_sinx/" "" "11.900 ns" { clkin divf:u1|COUT singt3:u2|lpm_counter:q_rtl_0|alt_counter_f10ke:wysi_counter|q[4] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "11.900 ns" { clkin clkin~out divf:u1|COUT singt3:u2|lpm_counter:q_rtl_0|alt_counter_f10ke:wysi_counter|q[4] } { 0.000ns 0.000ns 2.500ns 5.500ns } { 0.000ns 2.800ns 1.100ns 0.000ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.100 ns + " "Info: + Micro clock to output delay of source is 1.100 ns" {  } { { "alt_counter_f10ke.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/alt_counter_f10ke.tdf" 271 2 0 } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "2.500 ns + " "Info: + Micro setup delay of destination is 2.500 ns" {  } { { "alt_counter_f10ke.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/alt_counter_f10ke.tdf" 271 2 0 } }  } 0}  } { { "E:/EDA/DDS/10k844/divf16_sinx/db/divf16_sinx_cmp.qrpt" "" { Report "E:/EDA/DDS/10k844/divf16_sinx/db/divf16_sinx_cmp.qrpt" Compiler "divf16_sinx" "UNKNOWN" "V1" "E:/EDA/DDS/10k844/divf16_sinx/db/divf16_sinx.quartus_db" { Floorplan "E:/EDA/DDS/10k844/divf16_sinx/" "" "11.700 ns" { singt3:u2|lpm_counter:q_rtl_0|alt_counter_f10ke:wysi_counter|q[4] singt3:u2|LessThan~60 singt3:u2|LessThan~56 singt3:u2|LessThan~58 singt3:u2|lpm_counter:q_rtl_0|alt_counter_f10ke:wysi_counter|q[6] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "11.700 ns" { singt3:u2|lpm_counter:q_rtl_0|alt_counter_f10ke:wysi_counter|q[4] singt3:u2|LessThan~60 singt3:u2|LessThan~56 singt3:u2|LessThan~58 singt3:u2|lpm_counter:q_rtl_0|alt_counter_f10ke:wysi_counter|q[6] } { 0.000ns 2.200ns 0.000ns 2.200ns 0.600ns } { 0.000ns 1.700ns 1.500ns 1.800ns 1.700ns } } } { "E:/EDA/DDS/10k844/divf16_sinx/db/divf16_sinx_cmp.qrpt" "" { Report "E:/EDA/DDS/10k844/divf16_sinx/db/divf16_sinx_cmp.qrpt" Compiler "divf16_sinx" "UNKNOWN" "V1" "E:/EDA/DDS/10k844/divf16_sinx/db/divf16_sinx.quartus_db" { Floorplan "E:/EDA/DDS/10k844/divf16_sinx/" "" "11.900 ns" { clkin divf:u1|COUT singt3:u2|lpm_counter:q_rtl_0|alt_counter_f10ke:wysi_counter|q[6] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "11.900 ns" { clkin clkin~out divf:u1|COUT singt3:u2|lpm_counter:q_rtl_0|alt_counter_f10ke:wysi_counter|q[6] } { 0.000ns 0.000ns 2.500ns 5.500ns } { 0.000ns 2.800ns 1.100ns 0.000ns } } } { "E:/EDA/DDS/10k844/divf16_sinx/db/divf16_sinx_cmp.qrpt" "" { Report "E:/EDA/DDS/10k844/divf16_sinx/db/divf16_sinx_cmp.qrpt" Compiler "divf16_sinx" "UNKNOWN" "V1" "E:/EDA/DDS/10k844/divf16_sinx/db/divf16_sinx.quartus_db" { Floorplan "E:/EDA/DDS/10k844/divf16_sinx/" "" "11.900 ns" { clkin divf:u1|COUT singt3:u2|lpm_counter:q_rtl_0|alt_counter_f10ke:wysi_counter|q[4] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "11.900 ns" { clkin clkin~out divf:u1|COUT singt3:u2|lpm_counter:q_rtl_0|alt_counter_f10ke:wysi_counter|q[4] } { 0.000ns 0.000ns 2.500ns 5.500ns } { 0.000ns 2.800ns 1.100ns 0.000ns } } }  } 0}
{ "Info" "ITDB_TSU_RESULT" "divf:u1\|lpm_counter:CNT4_rtl_1\|alt_counter_f10ke:wysi_counter\|q\[2\] datain\[2\] clkin 3.300 ns register " "Info: tsu for register \"divf:u1\|lpm_counter:CNT4_rtl_1\|alt_counter_f10ke:wysi_counter\|q\[2\]\" (data pin = \"datain\[2\]\", clock pin = \"clkin\") is 3.300 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.100 ns + Longest pin register " "Info: + Longest pin to register delay is 6.100 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.800 ns) 2.800 ns datain\[2\] 1 PIN PIN_44 2 " "Info: 1: + IC(0.000 ns) + CELL(2.800 ns) = 2.800 ns; Loc. = PIN_44; Fanout = 2; PIN Node = 'datain\[2\]'" {  } { { "E:/EDA/DDS/10k844/divf16_sinx/db/divf16_sinx_cmp.qrpt" "" { Report "E:/EDA/DDS/10k844/divf16_sinx/db/divf16_sinx_cmp.qrpt" Compiler "divf16_sinx" "UNKNOWN" "V1" "E:/EDA/DDS/10k844/divf16_sinx/db/divf16_sinx.quartus_db" { Floorplan "E:/EDA/DDS/10k844/divf16_sinx/" "" "" { datain[2] } "NODE_NAME" } "" } } { "divf16_sinx.vhd" "" { Text "E:/EDA/DDS/10k844/divf16_sinx/divf16_sinx.vhd" 7 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.600 ns) + CELL(1.700 ns) 6.100 ns divf:u1\|lpm_counter:CNT4_rtl_1\|alt_counter_f10ke:wysi_counter\|q\[2\] 2 REG LC6_C6 5 " "Info: 2: + IC(1.600 ns) + CELL(1.700 ns) = 6.100 ns; Loc. = LC6_C6; Fanout = 5; REG Node = 'divf:u1\|lpm_counter:CNT4_rtl_1\|alt_counter_f10ke:wysi_counter\|q\[2\]'" {  } { { "E:/EDA/DDS/10k844/divf16_sinx/db/divf16_sinx_cmp.qrpt" "" { Report "E:/EDA/DDS/10k844/divf16_sinx/db/divf16_sinx_cmp.qrpt" Compiler "divf16_sinx" "UNKNOWN" "V1" "E:/EDA/DDS/10k844/divf16_sinx/db/divf16_sinx.quartus_db" { Floorplan "E:/EDA/DDS/10k844/divf16_sinx/" "" "3.300 ns" { datain[2] divf:u1|lpm_counter:CNT4_rtl_1|alt_counter_f10ke:wysi_counter|q[2] } "NODE_NAME" } "" } } { "alt_counter_f10ke.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/alt_counter_f10ke.tdf" 271 2 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.500 ns 73.77 % " "Info: Total cell delay = 4.500 ns ( 73.77 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.600 ns 26.23 % " "Info: Total interconnect delay = 1.600 ns ( 26.23 % )" {  } {  } 0}  } { { "E:/EDA/DDS/10k844/divf16_sinx/db/divf16_sinx_cmp.qrpt" "" { Report "E:/EDA/DDS/10k844/divf16_sinx/db/divf16_sinx_cmp.qrpt" Compiler "divf16_sinx" "UNKNOWN" "V1" "E:/EDA/DDS/10k844/divf16_sinx/db/divf16_sinx.quartus_db" { Floorplan "E:/EDA/DDS/10k844/divf16_sinx/" "" "6.100 ns" { datain[2] divf:u1|lpm_counter:CNT4_rtl_1|alt_counter_f10ke:wysi_counter|q[2] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "6.100 ns" { datain[2] datain[2]~out divf:u1|lpm_counter:CNT4_rtl_1|alt_counter_f10ke:wysi_counter|q[2] } { 0.000ns 0.000ns 1.600ns } { 0.000ns 2.800ns 1.700ns } } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "2.500 ns + " "Info: + Micro setup delay of destination is 2.500 ns" {  } { { "alt_counter_f10ke.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/alt_counter_f10ke.tdf" 271 2 0 } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clkin destination 5.300 ns - Shortest register " "Info: - Shortest clock path from clock \"clkin\" to destination register is 5.300 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.800 ns) 2.800 ns clkin 1 CLK PIN_43 8 " "Info: 1: + IC(0.000 ns) + CELL(2.800 ns) = 2.800 ns; Loc. = PIN_43; Fanout = 8; CLK Node = 'clkin'" {  } { { "E:/EDA/DDS/10k844/divf16_sinx/db/divf16_sinx_cmp.qrpt" "" { Report "E:/EDA/DDS/10k844/divf16_sinx/db/divf16_sinx_cmp.qrpt" Compiler "divf16_sinx" "UNKNOWN" "V1" "E:/EDA/DDS/10k844/divf16_sinx/db/divf16_sinx.quartus_db" { Floorplan "E:/EDA/DDS/10k844/divf16_sinx/" "" "" { clkin } "NODE_NAME" } "" } } { "divf16_sinx.vhd" "" { Text "E:/EDA/DDS/10k844/divf16_sinx/divf16_sinx.vhd" 6 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.500 ns) + CELL(0.000 ns) 5.300 ns divf:u1\|lpm_counter:CNT4_rtl_1\|alt_counter_f10ke:wysi_counter\|q\[2\] 2 REG LC6_C6 5 " "Info: 2: + IC(2.500 ns) + CELL(0.000 ns) = 5.300 ns; Loc. = LC6_C6; Fanout = 5; REG Node = 'divf:u1\|lpm_counter:CNT4_rtl_1\|alt_counter_f10ke:wysi_counter\|q\[2\]'" {  } { { "E:/EDA/DDS/10k844/divf16_sinx/db/divf16_sinx_cmp.qrpt" "" { Report "E:/EDA/DDS/10k844/divf16_sinx/db/divf16_sinx_cmp.qrpt" Compiler "divf16_sinx" "UNKNOWN" "V1" "E:/EDA/DDS/10k844/divf16_sinx/db/divf16_sinx.quartus_db" { Floorplan "E:/EDA/DDS/10k844/divf16_sinx/" "" "2.500 ns" { clkin divf:u1|lpm_counter:CNT4_rtl_1|alt_counter_f10ke:wysi_counter|q[2] } "NODE_NAME" } "" } } { "alt_counter_f10ke.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/alt_counter_f10ke.tdf" 271 2 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.800 ns 52.83 % " "Info: Total cell delay = 2.800 ns ( 52.83 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.500 ns 47.17 % " "Info: Total interconnect delay = 2.500 ns ( 47.17 % )" {  } {  } 0}  } { { "E:/EDA/DDS/10k844/divf16_sinx/db/divf16_sinx_cmp.qrpt" "" { Report "E:/EDA/DDS/10k844/divf16_sinx/db/divf16_sinx_cmp.qrpt" Compiler "divf16_sinx" "UNKNOWN" "V1" "E:/EDA/DDS/10k844/divf16_sinx/db/divf16_sinx.quartus_db" { Floorplan "E:/EDA/DDS/10k844/divf16_sinx/" "" "5.300 ns" { clkin divf:u1|lpm_counter:CNT4_rtl_1|alt_counter_f10ke:wysi_counter|q[2] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "5.300 ns" { clkin clkin~out divf:u1|lpm_counter:CNT4_rtl_1|alt_counter_f10ke:wysi_counter|q[2] } { 0.000ns 0.000ns 2.500ns } { 0.000ns 2.800ns 0.000ns } } }  } 0}  } { { "E:/EDA/DDS/10k844/divf16_sinx/db/divf16_sinx_cmp.qrpt" "" { Report "E:/EDA/DDS/10k844/divf16_sinx/db/divf16_sinx_cmp.qrpt" Compiler "divf16_sinx" "UNKNOWN" "V1" "E:/EDA/DDS/10k844/divf16_sinx/db/divf16_sinx.quartus_db" { Floorplan "E:/EDA/DDS/10k844/divf16_sinx/" "" "6.100 ns" { datain[2] divf:u1|lpm_counter:CNT4_rtl_1|alt_counter_f10ke:wysi_counter|q[2] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "6.100 ns" { datain[2] datain[2]~out divf:u1|lpm_counter:CNT4_rtl_1|alt_counter_f10ke:wysi_counter|q[2] } { 0.000ns 0.000ns 1.600ns } { 0.000ns 2.800ns 1.700ns } } } { "E:/EDA/DDS/10k844/divf16_sinx/db/divf16_sinx_cmp.qrpt" "" { Report "E:/EDA/DDS/10k844/divf16_sinx/db/divf16_sinx_cmp.qrpt" Compiler "divf16_sinx" "UNKNOWN" "V1" "E:/EDA/DDS/10k844/divf16_sinx/db/divf16_sinx.quartus_db" { Floorplan "E:/EDA/DDS/10k844/divf16_sinx/" "" "5.300 ns" { clkin divf:u1|lpm_counter:CNT4_rtl_1|alt_counter_f10ke:wysi_counter|q[2] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "5.300 ns" { clkin clkin~out divf:u1|lpm_counter:CNT4_rtl_1|alt_counter_f10ke:wysi_counter|q[2] } { 0.000ns 0.000ns 2.500ns } { 0.000ns 2.800ns 0.000ns } } }  } 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clkin daout\[3\] singt3:u2\|lpm_counter:q_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[0\] 37.000 ns register " "Info: tco from clock \"clkin\" to destination pin \"daout\[3\]\" through register \"singt3:u2\|lpm_counter:q_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[0\]\" is 37.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clkin source 11.900 ns + Longest register " "Info: + Longest clock path from clock \"clkin\" to source register is 11.900 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.800 ns) 2.800 ns clkin 1 CLK PIN_43 8 " "Info: 1: + IC(0.000 ns) + CELL(2.800 ns) = 2.800 ns; Loc. = PIN_43; Fanout = 8; CLK Node = 'clkin'" {  } { { "E:/EDA/DDS/10k844/divf16_sinx/db/divf16_sinx_cmp.qrpt" "" { Report "E:/EDA/DDS/10k844/divf16_sinx/db/divf16_sinx_cmp.qrpt" Compiler "divf16_sinx" "UNKNOWN" "V1" "E:/EDA/DDS/10k844/divf16_sinx/db/divf16_sinx.quartus_db" { Floorplan "E:/EDA/DDS/10k844/divf16_sinx/" "" "" { clkin } "NODE_NAME" } "" } } { "divf16_sinx.vhd" "" { Text "E:/EDA/DDS/10k844/divf16_sinx/divf16_sinx.vhd" 6 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.500 ns) + CELL(1.100 ns) 6.400 ns divf:u1\|COUT 2 REG LC1_C6 11 " "Info: 2: + IC(2.500 ns) + CELL(1.100 ns) = 6.400 ns; Loc. = LC1_C6; Fanout = 11; REG Node = 'divf:u1\|COUT'" {  } { { "E:/EDA/DDS/10k844/divf16_sinx/db/divf16_sinx_cmp.qrpt" "" { Report "E:/EDA/DDS/10k844/divf16_sinx/db/divf16_sinx_cmp.qrpt" Compiler "divf16_sinx" "UNKNOWN" "V1" "E:/EDA/DDS/10k844/divf16_sinx/db/divf16_sinx.quartus_db" { Floorplan "E:/EDA/DDS/10k844/divf16_sinx/" "" "3.600 ns" { clkin divf:u1|COUT } "NODE_NAME" } "" } } { "divf.vhd" "" { Text "E:/EDA/DDS/10k844/divf16_sinx/divf.vhd" 9 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(5.500 ns) + CELL(0.000 ns) 11.900 ns singt3:u2\|lpm_counter:q_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[0\] 3 REG LC1_B14 51 " "Info: 3: + IC(5.500 ns) + CELL(0.000 ns) = 11.900 ns; Loc. = LC1_B14; Fanout = 51; REG Node = 'singt3:u2\|lpm_counter:q_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[0\]'" {  } { { "E:/EDA/DDS/10k844/divf16_sinx/db/divf16_sinx_cmp.qrpt" "" { Report "E:/EDA/DDS/10k844/divf16_sinx/db/divf16_sinx_cmp.qrpt" Compiler "divf16_sinx" "UNKNOWN" "V1" "E:/EDA/DDS/10k844/divf16_sinx/db/divf16_sinx.quartus_db" { Floorplan "E:/EDA/DDS/10k844/divf16_sinx/" "" "5.500 ns" { divf:u1|COUT singt3:u2|lpm_counter:q_rtl_0|alt_counter_f10ke:wysi_counter|q[0] } "NODE_NAME" } "" } } { "alt_counter_f10ke.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/alt_counter_f10ke.tdf" 271 2 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.900 ns 32.77 % " "Info: Total cell delay = 3.900 ns ( 32.77 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "8.000 ns 67.23 % " "Info: Total interconnect delay = 8.000 ns ( 67.23 % )" {  } {  } 0}  } { { "E:/EDA/DDS/10k844/divf16_sinx/db/divf16_sinx_cmp.qrpt" "" { Report "E:/EDA/DDS/10k844/divf16_sinx/db/divf16_sinx_cmp.qrpt" Compiler "divf16_sinx" "UNKNOWN" "V1" "E:/EDA/DDS/10k844/divf16_sinx/db/divf16_sinx.quartus_db" { Floorplan "E:/EDA/DDS/10k844/divf16_sinx/" "" "11.900 ns" { clkin divf:u1|COUT singt3:u2|lpm_counter:q_rtl_0|alt_counter_f10ke:wysi_counter|q[0] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "11.900 ns" { clkin clkin~out divf:u1|COUT singt3:u2|lpm_counter:q_rtl_0|alt_counter_f10ke:wysi_counter|q[0] } { 0.000ns 0.000ns 2.500ns 5.500ns } { 0.000ns 2.800ns 1.100ns 0.000ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.100 ns + " "Info: + Micro clock to output delay of source is 1.100 ns" {  } { { "alt_counter_f10ke.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/alt_counter_f10ke.tdf" 271 2 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "24.000 ns + Longest register pin " "Info: + Longest register to pin delay is 24.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns singt3:u2\|lpm_counter:q_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[0\] 1 REG LC1_B14 51 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC1_B14; Fanout = 51; REG Node = 'singt3:u2\|lpm_counter:q_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[0\]'" {  } { { "E:/EDA/DDS/10k844/divf16_sinx/db/divf16_sinx_cmp.qrpt" "" { Report "E:/EDA/DDS/10k844/divf16_sinx/db/divf16_sinx_cmp.qrpt" Compiler "divf16_sinx" "UNKNOWN" "V1" "E:/EDA/DDS/10k844/divf16_sinx/db/divf16_sinx.quartus_db" { Floorplan "E:/EDA/DDS/10k844/divf16_sinx/" "" "" { singt3:u2|lpm_counter:q_rtl_0|alt_counter_f10ke:wysi_counter|q[0] } "NODE_NAME" } "" } } { "alt_counter_f10ke.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/alt_counter_f10ke.tdf" 271 2 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.800 ns) + CELL(2.300 ns) 6.100 ns singt3:u2\|dout\[3\]~687 2 COMB LC5_A17 1 " "Info: 2: + IC(3.800 ns) + CELL(2.300 ns) = 6.100 ns; Loc. = LC5_A17; Fanout = 1; COMB Node = 'singt3:u2\|dout\[3\]~687'" {  } { { "E:/EDA/DDS/10k844/divf16_sinx/db/divf16_sinx_cmp.qrpt" "" { Report "E:/EDA/DDS/10k844/divf16_sinx/db/divf16_sinx_cmp.qrpt" Compiler "divf16_sinx" "UNKNOWN" "V1" "E:/EDA/DDS/10k844/divf16_sinx/db/divf16_sinx.quartus_db" { Floorplan "E:/EDA/DDS/10k844/divf16_sinx/" "" "6.100 ns" { singt3:u2|lpm_counter:q_rtl_0|alt_counter_f10ke:wysi_counter|q[0] singt3:u2|dout[3]~687 } "NODE_NAME" } "" } } { "singt3.vhd" "" { Text "E:/EDA/DDS/10k844/divf16_sinx/singt3.vhd" 7 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.600 ns) + CELL(2.300 ns) 9.000 ns singt3:u2\|dout\[3\]~689 3 COMB LC7_A17 1 " "Info: 3: + IC(0.600 ns) + CELL(2.300 ns) = 9.000 ns; Loc. = LC7_A17; Fanout = 1; COMB Node = 'singt3:u2\|dout\[3\]~689'" {  } { { "E:/EDA/DDS/10k844/divf16_sinx/db/divf16_sinx_cmp.qrpt" "" { Report "E:/EDA/DDS/10k844/divf16_sinx/db/divf16_sinx_cmp.qrpt" Compiler "divf16_sinx" "UNKNOWN" "V1" "E:/EDA/DDS/10k844/divf16_sinx/db/divf16_sinx.quartus_db" { Floorplan "E:/EDA/DDS/10k844/divf16_sinx/" "" "2.900 ns" { singt3:u2|dout[3]~687 singt3:u2|dout[3]~689 } "NODE_NAME" } "" } } { "singt3.vhd" "" { Text "E:/EDA/DDS/10k844/divf16_sinx/singt3.vhd" 7 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.600 ns) + CELL(2.300 ns) 11.900 ns singt3:u2\|dout\[3\]~691 4 COMB LC3_A17 1 " "Info: 4: + IC(0.600 ns) + CELL(2.300 ns) = 11.900 ns; Loc. = LC3_A17; Fanout = 1; COMB Node = 'singt3:u2\|dout\[3\]~691'" {  } { { "E:/EDA/DDS/10k844/divf16_sinx/db/divf16_sinx_cmp.qrpt" "" { Report "E:/EDA/DDS/10k844/divf16_sinx/db/divf16_sinx_cmp.qrpt" Compiler "divf16_sinx" "UNKNOWN" "V1" "E:/EDA/DDS/10k844/divf16_sinx/db/divf16_sinx.quartus_db" { Floorplan "E:/EDA/DDS/10k844/divf16_sinx/" "" "2.900 ns" { singt3:u2|dout[3]~689 singt3:u2|dout[3]~691 } "NODE_NAME" } "" } } { "singt3.vhd" "" { Text "E:/EDA/DDS/10k844/divf16_sinx/singt3.vhd" 7 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.100 ns) + CELL(2.300 ns) 17.300 ns singt3:u2\|dout\[3\]~692 5 COMB LC4_C18 1 " "Info: 5: + IC(3.100 ns) + CELL(2.300 ns) = 17.300 ns; Loc. = LC4_C18; Fanout = 1; COMB Node = 'singt3:u2\|dout\[3\]~692'" {  } { { "E:/EDA/DDS/10k844/divf16_sinx/db/divf16_sinx_cmp.qrpt" "" { Report "E:/EDA/DDS/10k844/divf16_sinx/db/divf16_sinx_cmp.qrpt" Compiler "divf16_sinx" "UNKNOWN" "V1" "E:/EDA/DDS/10k844/divf16_sinx/db/divf16_sinx.quartus_db" { Floorplan "E:/EDA/DDS/10k844/divf16_sinx/" "" "5.400 ns" { singt3:u2|dout[3]~691 singt3:u2|dout[3]~692 } "NODE_NAME" } "" } } { "singt3.vhd" "" { Text "E:/EDA/DDS/10k844/divf16_sinx/singt3.vhd" 7 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.600 ns) + CELL(5.100 ns) 24.000 ns daout\[3\] 6 PIN PIN_60 0 " "Info: 6: + IC(1.600 ns) + CELL(5.100 ns) = 24.000 ns; Loc. = PIN_60; Fanout = 0; PIN Node = 'daout\[3\]'" {  } { { "E:/EDA/DDS/10k844/divf16_sinx/db/divf16_sinx_cmp.qrpt" "" { Report "E:/EDA/DDS/10k844/divf16_sinx/db/divf16_sinx_cmp.qrpt" Compiler "divf16_sinx" "UNKNOWN" "V1" "E:/EDA/DDS/10k844/divf16_sinx/db/divf16_sinx.quartus_db" { Floorplan "E:/EDA/DDS/10k844/divf16_sinx/" "" "6.700 ns" { singt3:u2|dout[3]~692 daout[3] } "NODE_NAME" } "" } } { "divf16_sinx.vhd" "" { Text "E:/EDA/DDS/10k844/divf16_sinx/divf16_sinx.vhd" 8 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "14.300 ns 59.58 % " "Info: Total cell delay = 14.300 ns ( 59.58 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "9.700 ns 40.42 % " "Info: Total interconnect delay = 9.700 ns ( 40.42 % )" {  } {  } 0}  } { { "E:/EDA/DDS/10k844/divf16_sinx/db/divf16_sinx_cmp.qrpt" "" { Report "E:/EDA/DDS/10k844/divf16_sinx/db/divf16_sinx_cmp.qrpt" Compiler "divf16_sinx" "UNKNOWN" "V1" "E:/EDA/DDS/10k844/divf16_sinx/db/divf16_sinx.quartus_db" { Floorplan "E:/EDA/DDS/10k844/divf16_sinx/" "" "24.000 ns" { singt3:u2|lpm_counter:q_rtl_0|alt_counter_f10ke:wysi_counter|q[0] singt3:u2|dout[3]~687 singt3:u2|dout[3]~689 singt3:u2|dout[3]~691 singt3:u2|dout[3]~692 daout[3] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "24.000 ns" { singt3:u2|lpm_counter:q_rtl_0|alt_counter_f10ke:wysi_counter|q[0] singt3:u2|dout[3]~687 singt3:u2|dout[3]~689 singt3:u2|dout[3]~691 singt3:u2|dout[3]~692 daout[3] } { 0.000ns 3.800ns 0.600ns 0.600ns 3.100ns 1.600ns } { 0.000ns 2.300ns 2.300ns 2.300ns 2.300ns 5.100ns } } }  } 0}  } { { "E:/EDA/DDS/10k844/divf16_sinx/db/divf16_sinx_cmp.qrpt" "" { Report "E:/EDA/DDS/10k844/divf16_sinx/db/divf16_sinx_cmp.qrpt" Compiler "divf16_sinx" "UNKNOWN" "V1" "E:/EDA/DDS/10k844/divf16_sinx/db/divf16_sinx.quartus_db" { Floorplan "E:/EDA/DDS/10k844/divf16_sinx/" "" "11.900 ns" { clkin divf:u1|COUT singt3:u2|lpm_counter:q_rtl_0|alt_counter_f10ke:wysi_counter|q[0] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "11.900 ns" { clkin clkin~out divf:u1|COUT singt3:u2|lpm_counter:q_rtl_0|alt_counter_f10ke:wysi_counter|q[0] } { 0.000ns 0.000ns 2.500ns 5.500ns } { 0.000ns 2.800ns 1.100ns 0.000ns } } } { "E:/EDA/DDS/10k844/divf16_sinx/db/divf16_sinx_cmp.qrpt" "" { Report "E:/EDA/DDS/10k844/divf16_sinx/db/divf16_sinx_cmp.qrpt" Compiler "divf16_sinx" "UNKNOWN" "V1" "E:/EDA/DDS/10k844/divf16_sinx/db/divf16_sinx.quartus_db" { Floorplan "E:/EDA/DDS/10k844/divf16_sinx/" "" "24.000 ns" { singt3:u2|lpm_counter:q_rtl_0|alt_counter_f10ke:wysi_counter|q[0] singt3:u2|dout[3]~687 singt3:u2|dout[3]~689 singt3:u2|dout[3]~691 singt3:u2|dout[3]~692 daout[3] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "24.000 ns" { singt3:u2|lpm_counter:q_rtl_0|alt_counter_f10ke:wysi_counter|q[0] singt3:u2|dout[3]~687 singt3:u2|dout[3]~689 singt3:u2|dout[3]~691 singt3:u2|dout[3]~692 daout[3] } { 0.000ns 3.800ns 0.600ns 0.600ns 3.100ns 1.600ns } { 0.000ns 2.300ns 2.300ns 2.300ns 2.300ns 5.100ns } } }  } 0}
divf16_sinx.tan.qmsg - 源码说明

本页面展示了「在EDA开发软件QuartusII上利用VHDL语言实现DDS信号发生器」中的 divf16_sinx.tan.qmsg 源码文件，采用 QMSG 编程语言编写，共 13 行代码。您可以在线阅读完整代码内容，也可以返回资源详情页下载完整源码包进行本地学习和开发。
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