divf_rom_sinx.vhd

来自「在EDA开发软件QuartusII上利用VHDL语言实现DDS信号发生器」· VHDL 代码 · 共 30 行

library ieee;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITY divf_rom_sinx IS
    PORT ( clkin: IN STD_LOGIC;
           datain:in std_logic_vector(3 downto 0); -- 初值
            f: out std_logic;           -- 频率显示出口
           Dadata: OUT STD_LOGIC_VECTOR(7 DOWNTO 0) );-- DA数据
END;

ARCHITECTURE behav OF divf_rom_sinx IS

component divf
    port(  CLK: IN  STD_LOGIC;
           DATA: IN STD_LOGIC_VECTOR(3 DOWNTO 0);
           FOUT: OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
           COUT: OUT STD_LOGIC  );
end component;

COMPONENT sinx_rom
    PORT ( CLK: IN STD_LOGIC;
           cout: out std_logic;
           DOUT: OUT STD_LOGIC_VECTOR(7 DOWNTO 0) );
END COMPONENT;
SIGNAL varif: STD_LOGIC;
BEGIN
u1:divf PORT MAP( clk=>clkin,data=>datain,cout=>varif );
u2:sinx_rom port map( clk=>varif,dout=>dadata,cout=>f );
END;