sinx_rom.tan.qmsg

来自「在EDA开发软件QuartusII上利用VHDL语言实现DDS信号发生器」· QMSG 代码 · 共 10 行 · 第 1/2 页

{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "CLK " "Info: Assuming node \"CLK\" is an undefined clock" {  } { { "sinx_rom.vhd" "" { Text "E:/EDA/DDS/10k844/sinx_rom/rom_sinx/sinx_rom.vhd" 6 -1 0 } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "CLK" } } } }  } 0}  } {  } 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "CLK register lpm_counter:Q_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[3\] register lpm_counter:Q_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[6\] 69.44 MHz 14.4 ns Internal " "Info: Clock \"CLK\" has Internal fmax of 69.44 MHz between source register \"lpm_counter:Q_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[3\]\" and destination register \"lpm_counter:Q_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[6\]\" (period= 14.4 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "10.800 ns + Longest register register " "Info: + Longest register to register delay is 10.800 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns lpm_counter:Q_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[3\] 1 REG LC4_A14 12 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC4_A14; Fanout = 12; REG Node = 'lpm_counter:Q_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[3\]'" {  } { { "E:/EDA/DDS/10k844/sinx_rom/rom_sinx/db/sinx_rom_cmp.qrpt" "" { Report "E:/EDA/DDS/10k844/sinx_rom/rom_sinx/db/sinx_rom_cmp.qrpt" Compiler "sinx_rom" "UNKNOWN" "V1" "E:/EDA/DDS/10k844/sinx_rom/rom_sinx/db/sinx_rom.quartus_db" { Floorplan "E:/EDA/DDS/10k844/sinx_rom/rom_sinx/" "" "" { lpm_counter:Q_rtl_0|alt_counter_f10ke:wysi_counter|q[3] } "NODE_NAME" } "" } } { "alt_counter_f10ke.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/alt_counter_f10ke.tdf" 271 2 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.200 ns) + CELL(2.300 ns) 4.500 ns LessThan~63 2 COMB LC2_A13 2 " "Info: 2: + IC(2.200 ns) + CELL(2.300 ns) = 4.500 ns; Loc. = LC2_A13; Fanout = 2; COMB Node = 'LessThan~63'" {  } { { "E:/EDA/DDS/10k844/sinx_rom/rom_sinx/db/sinx_rom_cmp.qrpt" "" { Report "E:/EDA/DDS/10k844/sinx_rom/rom_sinx/db/sinx_rom_cmp.qrpt" Compiler "sinx_rom" "UNKNOWN" "V1" "E:/EDA/DDS/10k844/sinx_rom/rom_sinx/db/sinx_rom.quartus_db" { Floorplan "E:/EDA/DDS/10k844/sinx_rom/rom_sinx/" "" "4.500 ns" { lpm_counter:Q_rtl_0|alt_counter_f10ke:wysi_counter|q[3] LessThan~63 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.200 ns) + CELL(1.800 ns) 8.500 ns LessThan~64 3 COMB LC8_A14 13 " "Info: 3: + IC(2.200 ns) + CELL(1.800 ns) = 8.500 ns; Loc. = LC8_A14; Fanout = 13; COMB Node = 'LessThan~64'" {  } { { "E:/EDA/DDS/10k844/sinx_rom/rom_sinx/db/sinx_rom_cmp.qrpt" "" { Report "E:/EDA/DDS/10k844/sinx_rom/rom_sinx/db/sinx_rom_cmp.qrpt" Compiler "sinx_rom" "UNKNOWN" "V1" "E:/EDA/DDS/10k844/sinx_rom/rom_sinx/db/sinx_rom.quartus_db" { Floorplan "E:/EDA/DDS/10k844/sinx_rom/rom_sinx/" "" "4.000 ns" { LessThan~63 LessThan~64 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.600 ns) + CELL(1.700 ns) 10.800 ns lpm_counter:Q_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[6\] 4 REG LC7_A14 10 " "Info: 4: + IC(0.600 ns) + CELL(1.700 ns) = 10.800 ns; Loc. = LC7_A14; Fanout = 10; REG Node = 'lpm_counter:Q_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[6\]'" {  } { { "E:/EDA/DDS/10k844/sinx_rom/rom_sinx/db/sinx_rom_cmp.qrpt" "" { Report "E:/EDA/DDS/10k844/sinx_rom/rom_sinx/db/sinx_rom_cmp.qrpt" Compiler "sinx_rom" "UNKNOWN" "V1" "E:/EDA/DDS/10k844/sinx_rom/rom_sinx/db/sinx_rom.quartus_db" { Floorplan "E:/EDA/DDS/10k844/sinx_rom/rom_sinx/" "" "2.300 ns" { LessThan~64 lpm_counter:Q_rtl_0|alt_counter_f10ke:wysi_counter|q[6] } "NODE_NAME" } "" } } { "alt_counter_f10ke.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/alt_counter_f10ke.tdf" 271 2 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "5.800 ns 53.70 % " "Info: Total cell delay = 5.800 ns ( 53.70 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.000 ns 46.30 % " "Info: Total interconnect delay = 5.000 ns ( 46.30 % )" {  } {  } 0}  } { { "E:/EDA/DDS/10k844/sinx_rom/rom_sinx/db/sinx_rom_cmp.qrpt" "" { Report "E:/EDA/DDS/10k844/sinx_rom/rom_sinx/db/sinx_rom_cmp.qrpt" Compiler "sinx_rom" "UNKNOWN" "V1" "E:/EDA/DDS/10k844/sinx_rom/rom_sinx/db/sinx_rom.quartus_db" { Floorplan "E:/EDA/DDS/10k844/sinx_rom/rom_sinx/" "" "10.800 ns" { lpm_counter:Q_rtl_0|alt_counter_f10ke:wysi_counter|q[3] LessThan~63 LessThan~64 lpm_counter:Q_rtl_0|alt_counter_f10ke:wysi_counter|q[6] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "10.800 ns" { lpm_counter:Q_rtl_0|alt_counter_f10ke:wysi_counter|q[3] LessThan~63 LessThan~64 lpm_counter:Q_rtl_0|alt_counter_f10ke:wysi_counter|q[6] } { 0.000ns 2.200ns 2.200ns 0.600ns } { 0.000ns 2.300ns 1.800ns 1.700ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK destination 5.300 ns + Shortest register " "Info: + Shortest clock path from clock \"CLK\" to destination register is 5.300 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.800 ns) 2.800 ns CLK 1 CLK PIN_43 70 " "Info: 1: + IC(0.000 ns) + CELL(2.800 ns) = 2.800 ns; Loc. = PIN_43; Fanout = 70; CLK Node = 'CLK'" {  } { { "E:/EDA/DDS/10k844/sinx_rom/rom_sinx/db/sinx_rom_cmp.qrpt" "" { Report "E:/EDA/DDS/10k844/sinx_rom/rom_sinx/db/sinx_rom_cmp.qrpt" Compiler "sinx_rom" "UNKNOWN" "V1" "E:/EDA/DDS/10k844/sinx_rom/rom_sinx/db/sinx_rom.quartus_db" { Floorplan "E:/EDA/DDS/10k844/sinx_rom/rom_sinx/" "" "" { CLK } "NODE_NAME" } "" } } { "sinx_rom.vhd" "" { Text "E:/EDA/DDS/10k844/sinx_rom/rom_sinx/sinx_rom.vhd" 6 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.500 ns) + CELL(0.000 ns) 5.300 ns lpm_counter:Q_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[6\] 2 REG LC7_A14 10 " "Info: 2: + IC(2.500 ns) + CELL(0.000 ns) = 5.300 ns; Loc. = LC7_A14; Fanout = 10; REG Node = 'lpm_counter:Q_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[6\]'" {  } { { "E:/EDA/DDS/10k844/sinx_rom/rom_sinx/db/sinx_rom_cmp.qrpt" "" { Report "E:/EDA/DDS/10k844/sinx_rom/rom_sinx/db/sinx_rom_cmp.qrpt" Compiler "sinx_rom" "UNKNOWN" "V1" "E:/EDA/DDS/10k844/sinx_rom/rom_sinx/db/sinx_rom.quartus_db" { Floorplan "E:/EDA/DDS/10k844/sinx_rom/rom_sinx/" "" "2.500 ns" { CLK lpm_counter:Q_rtl_0|alt_counter_f10ke:wysi_counter|q[6] } "NODE_NAME" } "" } } { "alt_counter_f10ke.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/alt_counter_f10ke.tdf" 271 2 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.800 ns 52.83 % " "Info: Total cell delay = 2.800 ns ( 52.83 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.500 ns 47.17 % " "Info: Total interconnect delay = 2.500 ns ( 47.17 % )" {  } {  } 0}  } { { "E:/EDA/DDS/10k844/sinx_rom/rom_sinx/db/sinx_rom_cmp.qrpt" "" { Report "E:/EDA/DDS/10k844/sinx_rom/rom_sinx/db/sinx_rom_cmp.qrpt" Compiler "sinx_rom" "UNKNOWN" "V1" "E:/EDA/DDS/10k844/sinx_rom/rom_sinx/db/sinx_rom.quartus_db" { Floorplan "E:/EDA/DDS/10k844/sinx_rom/rom_sinx/" "" "5.300 ns" { CLK lpm_counter:Q_rtl_0|alt_counter_f10ke:wysi_counter|q[6] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "5.300 ns" { CLK CLK~out lpm_counter:Q_rtl_0|alt_counter_f10ke:wysi_counter|q[6] } { 0.000ns 0.000ns 2.500ns } { 0.000ns 2.800ns 0.000ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK source 5.300 ns - Longest register " "Info: - Longest clock path from clock \"CLK\" to source register is 5.300 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.800 ns) 2.800 ns CLK 1 CLK PIN_43 70 " "Info: 1: + IC(0.000 ns) + CELL(2.800 ns) = 2.800 ns; Loc. = PIN_43; Fanout = 70; CLK Node = 'CLK'" {  } { { "E:/EDA/DDS/10k844/sinx_rom/rom_sinx/db/sinx_rom_cmp.qrpt" "" { Report "E:/EDA/DDS/10k844/sinx_rom/rom_sinx/db/sinx_rom_cmp.qrpt" Compiler "sinx_rom" "UNKNOWN" "V1" "E:/EDA/DDS/10k844/sinx_rom/rom_sinx/db/sinx_rom.quartus_db" { Floorplan "E:/EDA/DDS/10k844/sinx_rom/rom_sinx/" "" "" { CLK } "NODE_NAME" } "" } } { "sinx_rom.vhd" "" { Text "E:/EDA/DDS/10k844/sinx_rom/rom_sinx/sinx_rom.vhd" 6 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.500 ns) + CELL(0.000 ns) 5.300 ns lpm_counter:Q_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[3\] 2 REG LC4_A14 12 " "Info: 2: + IC(2.500 ns) + CELL(0.000 ns) = 5.300 ns; Loc. = LC4_A14; Fanout = 12; REG Node = 'lpm_counter:Q_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[3\]'" {  } { { "E:/EDA/DDS/10k844/sinx_rom/rom_sinx/db/sinx_rom_cmp.qrpt" "" { Report "E:/EDA/DDS/10k844/sinx_rom/rom_sinx/db/sinx_rom_cmp.qrpt" Compiler "sinx_rom" "UNKNOWN" "V1" "E:/EDA/DDS/10k844/sinx_rom/rom_sinx/db/sinx_rom.quartus_db" { Floorplan "E:/EDA/DDS/10k844/sinx_rom/rom_sinx/" "" "2.500 ns" { CLK lpm_counter:Q_rtl_0|alt_counter_f10ke:wysi_counter|q[3] } "NODE_NAME" } "" } } { "alt_counter_f10ke.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/alt_counter_f10ke.tdf" 271 2 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.800 ns 52.83 % " "Info: Total cell delay = 2.800 ns ( 52.83 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.500 ns 47.17 % " "Info: Total interconnect delay = 2.500 ns ( 47.17 % )" {  } {  } 0}  } { { "E:/EDA/DDS/10k844/sinx_rom/rom_sinx/db/sinx_rom_cmp.qrpt" "" { Report "E:/EDA/DDS/10k844/sinx_rom/rom_sinx/db/sinx_rom_cmp.qrpt" Compiler "sinx_rom" "UNKNOWN" "V1" "E:/EDA/DDS/10k844/sinx_rom/rom_sinx/db/sinx_rom.quartus_db" { Floorplan "E:/EDA/DDS/10k844/sinx_rom/rom_sinx/" "" "5.300 ns" { CLK lpm_counter:Q_rtl_0|alt_counter_f10ke:wysi_counter|q[3] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "5.300 ns" { CLK CLK~out lpm_counter:Q_rtl_0|alt_counter_f10ke:wysi_counter|q[3] } { 0.000ns 0.000ns 2.500ns } { 0.000ns 2.800ns 0.000ns } } }  } 0}  } { { "E:/EDA/DDS/10k844/sinx_rom/rom_sinx/db/sinx_rom_cmp.qrpt" "" { Report "E:/EDA/DDS/10k844/sinx_rom/rom_sinx/db/sinx_rom_cmp.qrpt" Compiler "sinx_rom" "UNKNOWN" "V1" "E:/EDA/DDS/10k844/sinx_rom/rom_sinx/db/sinx_rom.quartus_db" { Floorplan "E:/EDA/DDS/10k844/sinx_rom/rom_sinx/" "" "5.300 ns" { CLK lpm_counter:Q_rtl_0|alt_counter_f10ke:wysi_counter|q[6] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "5.300 ns" { CLK CLK~out lpm_counter:Q_rtl_0|alt_counter_f10ke:wysi_counter|q[6] } { 0.000ns 0.000ns 2.500ns } { 0.000ns 2.800ns 0.000ns } } } { "E:/EDA/DDS/10k844/sinx_rom/rom_sinx/db/sinx_rom_cmp.qrpt" "" { Report "E:/EDA/DDS/10k844/sinx_rom/rom_sinx/db/sinx_rom_cmp.qrpt" Compiler "sinx_rom" "UNKNOWN" "V1" "E:/EDA/DDS/10k844/sinx_rom/rom_sinx/db/sinx_rom.quartus_db" { Floorplan "E:/EDA/DDS/10k844/sinx_rom/rom_sinx/" "" "5.300 ns" { CLK lpm_counter:Q_rtl_0|alt_counter_f10ke:wysi_counter|q[3] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "5.300 ns" { CLK CLK~out lpm_counter:Q_rtl_0|alt_counter_f10ke:wysi_counter|q[3] } { 0.000ns 0.000ns 2.500ns } { 0.000ns 2.800ns 0.000ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.100 ns + " "Info: + Micro clock to output delay of source is 1.100 ns" {  } { { "alt_counter_f10ke.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/alt_counter_f10ke.tdf" 271 2 0 } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "2.500 ns + " "Info: + Micro setup delay of destination is 2.500 ns" {  } { { "alt_counter_f10ke.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/alt_counter_f10ke.tdf" 271 2 0 } }  } 0}  } { { "E:/EDA/DDS/10k844/sinx_rom/rom_sinx/db/sinx_rom_cmp.qrpt" "" { Report "E:/EDA/DDS/10k844/sinx_rom/rom_sinx/db/sinx_rom_cmp.qrpt" Compiler "sinx_rom" "UNKNOWN" "V1" "E:/EDA/DDS/10k844/sinx_rom/rom_sinx/db/sinx_rom.quartus_db" { Floorplan "E:/EDA/DDS/10k844/sinx_rom/rom_sinx/" "" "10.800 ns" { lpm_counter:Q_rtl_0|alt_counter_f10ke:wysi_counter|q[3] LessThan~63 LessThan~64 lpm_counter:Q_rtl_0|alt_counter_f10ke:wysi_counter|q[6] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "10.800 ns" { lpm_counter:Q_rtl_0|alt_counter_f10ke:wysi_counter|q[3] LessThan~63 LessThan~64 lpm_counter:Q_rtl_0|alt_counter_f10ke:wysi_counter|q[6] } { 0.000ns 2.200ns 2.200ns 0.600ns } { 0.000ns 2.300ns 1.800ns 1.700ns } } } { "E:/EDA/DDS/10k844/sinx_rom/rom_sinx/db/sinx_rom_cmp.qrpt" "" { Report "E:/EDA/DDS/10k844/sinx_rom/rom_sinx/db/sinx_rom_cmp.qrpt" Compiler "sinx_rom" "UNKNOWN" "V1" "E:/EDA/DDS/10k844/sinx_rom/rom_sinx/db/sinx_rom.quartus_db" { Floorplan "E:/EDA/DDS/10k844/sinx_rom/rom_sinx/" "" "5.300 ns" { CLK lpm_counter:Q_rtl_0|alt_counter_f10ke:wysi_counter|q[6] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "5.300 ns" { CLK CLK~out lpm_counter:Q_rtl_0|alt_counter_f10ke:wysi_counter|q[6] } { 0.000ns 0.000ns 2.500ns } { 0.000ns 2.800ns 0.000ns } } } { "E:/EDA/DDS/10k844/sinx_rom/rom_sinx/db/sinx_rom_cmp.qrpt" "" { Report "E:/EDA/DDS/10k844/sinx_rom/rom_sinx/db/sinx_rom_cmp.qrpt" Compiler "sinx_rom" "UNKNOWN" "V1" "E:/EDA/DDS/10k844/sinx_rom/rom_sinx/db/sinx_rom.quartus_db" { Floorplan "E:/EDA/DDS/10k844/sinx_rom/rom_sinx/" "" "5.300 ns" { CLK lpm_counter:Q_rtl_0|alt_counter_f10ke:wysi_counter|q[3] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "5.300 ns" { CLK CLK~out lpm_counter:Q_rtl_0|alt_counter_f10ke:wysi_counter|q[3] } { 0.000ns 0.000ns 2.500ns } { 0.000ns 2.800ns 0.000ns } } }  } 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "CLK DOUT\[7\] data_rom_10k:u1\|lpm_rom:lpm_rom_component\|altrom:srom\|q\[7\]~reg_ra0 29.400 ns memory " "Info: tco from clock \"CLK\" to destination pin \"DOUT\[7\]\" through memory \"data_rom_10k:u1\|lpm_rom:lpm_rom_component\|altrom:srom\|q\[7\]~reg_ra0\" is 29.400 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK source 5.300 ns + Longest memory " "Info: + Longest clock path from clock \"CLK\" to source memory is 5.300 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.800 ns) 2.800 ns CLK 1 CLK PIN_43 70 " "Info: 1: + IC(0.000 ns) + CELL(2.800 ns) = 2.800 ns; Loc. = PIN_43; Fanout = 70; CLK Node = 'CLK'" {  } { { "E:/EDA/DDS/10k844/sinx_rom/rom_sinx/db/sinx_rom_cmp.qrpt" "" { Report "E:/EDA/DDS/10k844/sinx_rom/rom_sinx/db/sinx_rom_cmp.qrpt" Compiler "sinx_rom" "UNKNOWN" "V1" "E:/EDA/DDS/10k844/sinx_rom/rom_sinx/db/sinx_rom.quartus_db" { Floorplan "E:/EDA/DDS/10k844/sinx_rom/rom_sinx/" "" "" { CLK } "NODE_NAME" } "" } } { "sinx_rom.vhd" "" { Text "E:/EDA/DDS/10k844/sinx_rom/rom_sinx/sinx_rom.vhd" 6 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.500 ns) + CELL(0.000 ns) 5.300 ns data_rom_10k:u1\|lpm_rom:lpm_rom_component\|altrom:srom\|q\[7\]~reg_ra0 2 MEM EC7_A 1 " "Info: 2: + IC(2.500 ns) + CELL(0.000 ns) = 5.300 ns; Loc. = EC7_A; Fanout = 1; MEM Node = 'data_rom_10k:u1\|lpm_rom:lpm_rom_component\|altrom:srom\|q\[7\]~reg_ra0'" {  } { { "E:/EDA/DDS/10k844/sinx_rom/rom_sinx/db/sinx_rom_cmp.qrpt" "" { Report "E:/EDA/DDS/10k844/sinx_rom/rom_sinx/db/sinx_rom_cmp.qrpt" Compiler "sinx_rom" "UNKNOWN" "V1" "E:/EDA/DDS/10k844/sinx_rom/rom_sinx/db/sinx_rom.quartus_db" { Floorplan "E:/EDA/DDS/10k844/sinx_rom/rom_sinx/" "" "2.500 ns" { CLK data_rom_10k:u1|lpm_rom:lpm_rom_component|altrom:srom|q[7]~reg_ra0 } "NODE_NAME" } "" } } { "altrom.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/altrom.tdf" 80 2 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.800 ns 52.83 % " "Info: Total cell delay = 2.800 ns ( 52.83 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.500 ns 47.17 % " "Info: Total interconnect delay = 2.500 ns ( 47.17 % )" {  } {  } 0}  } { { "E:/EDA/DDS/10k844/sinx_rom/rom_sinx/db/sinx_rom_cmp.qrpt" "" { Report "E:/EDA/DDS/10k844/sinx_rom/rom_sinx/db/sinx_rom_cmp.qrpt" Compiler "sinx_rom" "UNKNOWN" "V1" "E:/EDA/DDS/10k844/sinx_rom/rom_sinx/db/sinx_rom.quartus_db" { Floorplan "E:/EDA/DDS/10k844/sinx_rom/rom_sinx/" "" "5.300 ns" { CLK data_rom_10k:u1|lpm_rom:lpm_rom_component|altrom:srom|q[7]~reg_ra0 } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "5.300 ns" { CLK CLK~out data_rom_10k:u1|lpm_rom:lpm_rom_component|altrom:srom|q[7]~reg_ra0 } { 0.000ns 0.000ns 2.500ns } { 0.000ns 2.800ns 0.000ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.600 ns + " "Info: + Micro clock to output delay of source is 0.600 ns" {  } { { "altrom.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/altrom.tdf" 80 2 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "23.500 ns + Longest memory pin " "Info: + Longest memory to pin delay is 23.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns data_rom_10k:u1\|lpm_rom:lpm_rom_component\|altrom:srom\|q\[7\]~reg_ra0 1 MEM EC7_A 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = EC7_A; Fanout = 1; MEM Node = 'data_rom_10k:u1\|lpm_rom:lpm_rom_component\|altrom:srom\|q\[7\]~reg_ra0'" {  } { { "E:/EDA/DDS/10k844/sinx_rom/rom_sinx/db/sinx_rom_cmp.qrpt" "" { Report "E:/EDA/DDS/10k844/sinx_rom/rom_sinx/db/sinx_rom_cmp.qrpt" Compiler "sinx_rom" "UNKNOWN" "V1" "E:/EDA/DDS/10k844/sinx_rom/rom_sinx/db/sinx_rom.quartus_db" { Floorplan "E:/EDA/DDS/10k844/sinx_rom/rom_sinx/" "" "" { data_rom_10k:u1|lpm_rom:lpm_rom_component|altrom:srom|q[7]~reg_ra0 } "NODE_NAME" } "" } } { "altrom.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/altrom.tdf" 80 2 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(10.700 ns) 10.700 ns data_rom_10k:u1\|lpm_rom:lpm_rom_component\|altrom:srom\|q\[7\]~mem_cell_ra0 2 MEM EC7_A 1 " "Info: 2: + IC(0.000 ns) + CELL(10.700 ns) = 10.700 ns; Loc. = EC7_A; Fanout = 1; MEM Node = 'data_rom_10k:u1\|lpm_rom:lpm_rom_component\|altrom:srom\|q\[7\]~mem_cell_ra0'" {  } { { "E:/EDA/DDS/10k844/sinx_rom/rom_sinx/db/sinx_rom_cmp.qrpt" "" { Report "E:/EDA/DDS/10k844/sinx_rom/rom_sinx/db/sinx_rom_cmp.qrpt" Compiler "sinx_rom" "UNKNOWN" "V1" "E:/EDA/DDS/10k844/sinx_rom/rom_sinx/db/sinx_rom.quartus_db" { Floorplan "E:/EDA/DDS/10k844/sinx_rom/rom_sinx/" "" "10.700 ns" { data_rom_10k:u1|lpm_rom:lpm_rom_component|altrom:srom|q[7]~reg_ra0 data_rom_10k:u1|lpm_rom:lpm_rom_component|altrom:srom|q[7]~mem_cell_ra0 } "NODE_NAME" } "" } } { "altrom.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/altrom.tdf" 80 2 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.500 ns) 13.200 ns data_rom_10k:u1\|lpm_rom:lpm_rom_component\|altrom:srom\|q\[7\] 3 MEM EC7_A 1 " "Info: 3: + IC(0.000 ns) + CELL(2.500 ns) = 13.200 ns; Loc. = EC7_A; Fanout = 1; MEM Node = 'data_rom_10k:u1\|lpm_rom:lpm_rom_component\|altrom:srom\|q\[7\]'" {  } { { "E:/EDA/DDS/10k844/sinx_rom/rom_sinx/db/sinx_rom_cmp.qrpt" "" { Report "E:/EDA/DDS/10k844/sinx_rom/rom_sinx/db/sinx_rom_cmp.qrpt" Compiler "sinx_rom" "UNKNOWN" "V1" "E:/EDA/DDS/10k844/sinx_rom/rom_sinx/db/sinx_rom.quartus_db" { Floorplan "E:/EDA/DDS/10k844/sinx_rom/rom_sinx/" "" "2.500 ns" { data_rom_10k:u1|lpm_rom:lpm_rom_component|altrom:srom|q[7]~mem_cell_ra0 data_rom_10k:u1|lpm_rom:lpm_rom_component|altrom:srom|q[7] } "NODE_NAME" } "" } } { "altrom.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/altrom.tdf" 80 2 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(5.200 ns) + CELL(5.100 ns) 23.500 ns DOUT\[7\] 4 PIN PIN_60 0 " "Info: 4: + IC(5.200 ns) + CELL(5.100 ns) = 23.500 ns; Loc. = PIN_60; Fanout = 0; PIN Node = 'DOUT\[7\]'" {  } { { "E:/EDA/DDS/10k844/sinx_rom/rom_sinx/db/sinx_rom_cmp.qrpt" "" { Report "E:/EDA/DDS/10k844/sinx_rom/rom_sinx/db/sinx_rom_cmp.qrpt" Compiler "sinx_rom" "UNKNOWN" "V1" "E:/EDA/DDS/10k844/sinx_rom/rom_sinx/db/sinx_rom.quartus_db" { Floorplan "E:/EDA/DDS/10k844/sinx_rom/rom_sinx/" "" "10.300 ns" { data_rom_10k:u1|lpm_rom:lpm_rom_component|altrom:srom|q[7] DOUT[7] } "NODE_NAME" } "" } } { "sinx_rom.vhd" "" { Text "E:/EDA/DDS/10k844/sinx_rom/rom_sinx/sinx_rom.vhd" 8 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "18.300 ns 77.87 % " "Info: Total cell delay = 18.300 ns ( 77.87 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.200 ns 22.13 % " "Info: Total interconnect delay = 5.200 ns ( 22.13 % )" {  } {  } 0}  } { { "E:/EDA/DDS/10k844/sinx_rom/rom_sinx/db/sinx_rom_cmp.qrpt" "" { Report "E:/EDA/DDS/10k844/sinx_rom/rom_sinx/db/sinx_rom_cmp.qrpt" Compiler "sinx_rom" "UNKNOWN" "V1" "E:/EDA/DDS/10k844/sinx_rom/rom_sinx/db/sinx_rom.quartus_db" { Floorplan "E:/EDA/DDS/10k844/sinx_rom/rom_sinx/" "" "23.500 ns" { data_rom_10k:u1|lpm_rom:lpm_rom_component|altrom:srom|q[7]~reg_ra0 data_rom_10k:u1|lpm_rom:lpm_rom_component|altrom:srom|q[7]~mem_cell_ra0 data_rom_10k:u1|lpm_rom:lpm_rom_component|altrom:srom|q[7] DOUT[7] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "23.500 ns" { data_rom_10k:u1|lpm_rom:lpm_rom_component|altrom:srom|q[7]~reg_ra0 data_rom_10k:u1|lpm_rom:lpm_rom_component|altrom:srom|q[7]~mem_cell_ra0 data_rom_10k:u1|lpm_rom:lpm_rom_component|altrom:srom|q[7] DOUT[7] } { 0.000ns 0.000ns 0.000ns 5.200ns } { 0.000ns 10.700ns 2.500ns 5.100ns } } }  } 0}  } { { "E:/EDA/DDS/10k844/sinx_rom/rom_sinx/db/sinx_rom_cmp.qrpt" "" { Report "E:/EDA/DDS/10k844/sinx_rom/rom_sinx/db/sinx_rom_cmp.qrpt" Compiler "sinx_rom" "UNKNOWN" "V1" "E:/EDA/DDS/10k844/sinx_rom/rom_sinx/db/sinx_rom.quartus_db" { Floorplan "E:/EDA/DDS/10k844/sinx_rom/rom_sinx/" "" "5.300 ns" { CLK data_rom_10k:u1|lpm_rom:lpm_rom_component|altrom:srom|q[7]~reg_ra0 } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "5.300 ns" { CLK CLK~out data_rom_10k:u1|lpm_rom:lpm_rom_component|altrom:srom|q[7]~reg_ra0 } { 0.000ns 0.000ns 2.500ns } { 0.000ns 2.800ns 0.000ns } } } { "E:/EDA/DDS/10k844/sinx_rom/rom_sinx/db/sinx_rom_cmp.qrpt" "" { Report "E:/EDA/DDS/10k844/sinx_rom/rom_sinx/db/sinx_rom_cmp.qrpt" Compiler "sinx_rom" "UNKNOWN" "V1" "E:/EDA/DDS/10k844/sinx_rom/rom_sinx/db/sinx_rom.quartus_db" { Floorplan "E:/EDA/DDS/10k844/sinx_rom/rom_sinx/" "" "23.500 ns" { data_rom_10k:u1|lpm_rom:lpm_rom_component|altrom:srom|q[7]~reg_ra0 data_rom_10k:u1|lpm_rom:lpm_rom_component|altrom:srom|q[7]~mem_cell_ra0 data_rom_10k:u1|lpm_rom:lpm_rom_component|altrom:srom|q[7] DOUT[7] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "23.500 ns" { data_rom_10k:u1|lpm_rom:lpm_rom_component|altrom:srom|q[7]~reg_ra0 data_rom_10k:u1|lpm_rom:lpm_rom_component|altrom:srom|q[7]~mem_cell_ra0 data_rom_10k:u1|lpm_rom:lpm_rom_component|altrom:srom|q[7] DOUT[7] } { 0.000ns 0.000ns 0.000ns 5.200ns } { 0.000ns 10.700ns 2.500ns 5.100ns } } }  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 1  Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Sat Apr 15 21:19:55 2006 " "Info: Processing ended: Sat Apr 15 21:19:55 2006" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" {  } {  } 0}  } {  } 0}