sf_df_rom_sinx.tan.qmsg

来自「在EDA开发软件QuartusII上利用VHDL语言实现DDS信号发生器」· QMSG 代码 · 共 13 行 · 第 1/3 页

{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clkk " "Info: Assuming node \"clkk\" is an undefined clock" {  } { { "sf_df_rom_sinx.vhd" "" { Text "E:/EDA/DDS/10k844/sinx_rom/rom_sinx/sf_df_rom_sinx.vhd" 6 -1 0 } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "clkk" } } } }  } 0}  } {  } 0}
{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "1 " "Warning: Found 1 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "divf_rom_sinx:u2\|divf:u1\|COUT " "Info: Detected ripple clock \"divf_rom_sinx:u2\|divf:u1\|COUT\" as buffer" {  } { { "divf.vhd" "" { Text "E:/EDA/DDS/10k844/sinx_rom/rom_sinx/divf.vhd" 9 -1 0 } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "divf_rom_sinx:u2\|divf:u1\|COUT" } } } }  } 0}  } {  } 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clkk register divf_rom_sinx:u2\|sinx_rom:u2\|lpm_counter:Q_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[3\] register divf_rom_sinx:u2\|sinx_rom:u2\|lpm_counter:Q_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[6\] 69.44 MHz 14.4 ns Internal " "Info: Clock \"clkk\" has Internal fmax of 69.44 MHz between source register \"divf_rom_sinx:u2\|sinx_rom:u2\|lpm_counter:Q_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[3\]\" and destination register \"divf_rom_sinx:u2\|sinx_rom:u2\|lpm_counter:Q_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[6\]\" (period= 14.4 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "10.800 ns + Longest register register " "Info: + Longest register to register delay is 10.800 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns divf_rom_sinx:u2\|sinx_rom:u2\|lpm_counter:Q_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[3\] 1 REG LC4_A14 12 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC4_A14; Fanout = 12; REG Node = 'divf_rom_sinx:u2\|sinx_rom:u2\|lpm_counter:Q_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[3\]'" {  } { { "E:/EDA/DDS/10k844/sinx_rom/rom_sinx/db/sf_df_rom_sinx_cmp.qrpt" "" { Report "E:/EDA/DDS/10k844/sinx_rom/rom_sinx/db/sf_df_rom_sinx_cmp.qrpt" Compiler "sf_df_rom_sinx" "UNKNOWN" "V1" "E:/EDA/DDS/10k844/sinx_rom/rom_sinx/db/sf_df_rom_sinx.quartus_db" { Floorplan "E:/EDA/DDS/10k844/sinx_rom/rom_sinx/" "" "" { divf_rom_sinx:u2|sinx_rom:u2|lpm_counter:Q_rtl_0|alt_counter_f10ke:wysi_counter|q[3] } "NODE_NAME" } "" } } { "alt_counter_f10ke.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/alt_counter_f10ke.tdf" 271 2 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.200 ns) + CELL(2.300 ns) 4.500 ns divf_rom_sinx:u2\|sinx_rom:u2\|LessThan~63 2 COMB LC2_A13 2 " "Info: 2: + IC(2.200 ns) + CELL(2.300 ns) = 4.500 ns; Loc. = LC2_A13; Fanout = 2; COMB Node = 'divf_rom_sinx:u2\|sinx_rom:u2\|LessThan~63'" {  } { { "E:/EDA/DDS/10k844/sinx_rom/rom_sinx/db/sf_df_rom_sinx_cmp.qrpt" "" { Report "E:/EDA/DDS/10k844/sinx_rom/rom_sinx/db/sf_df_rom_sinx_cmp.qrpt" Compiler "sf_df_rom_sinx" "UNKNOWN" "V1" "E:/EDA/DDS/10k844/sinx_rom/rom_sinx/db/sf_df_rom_sinx.quartus_db" { Floorplan "E:/EDA/DDS/10k844/sinx_rom/rom_sinx/" "" "4.500 ns" { divf_rom_sinx:u2|sinx_rom:u2|lpm_counter:Q_rtl_0|alt_counter_f10ke:wysi_counter|q[3] divf_rom_sinx:u2|sinx_rom:u2|LessThan~63 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.200 ns) + CELL(1.800 ns) 8.500 ns divf_rom_sinx:u2\|sinx_rom:u2\|LessThan~64 3 COMB LC8_A14 13 " "Info: 3: + IC(2.200 ns) + CELL(1.800 ns) = 8.500 ns; Loc. = LC8_A14; Fanout = 13; COMB Node = 'divf_rom_sinx:u2\|sinx_rom:u2\|LessThan~64'" {  } { { "E:/EDA/DDS/10k844/sinx_rom/rom_sinx/db/sf_df_rom_sinx_cmp.qrpt" "" { Report "E:/EDA/DDS/10k844/sinx_rom/rom_sinx/db/sf_df_rom_sinx_cmp.qrpt" Compiler "sf_df_rom_sinx" "UNKNOWN" "V1" "E:/EDA/DDS/10k844/sinx_rom/rom_sinx/db/sf_df_rom_sinx.quartus_db" { Floorplan "E:/EDA/DDS/10k844/sinx_rom/rom_sinx/" "" "4.000 ns" { divf_rom_sinx:u2|sinx_rom:u2|LessThan~63 divf_rom_sinx:u2|sinx_rom:u2|LessThan~64 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.600 ns) + CELL(1.700 ns) 10.800 ns divf_rom_sinx:u2\|sinx_rom:u2\|lpm_counter:Q_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[6\] 4 REG LC7_A14 10 " "Info: 4: + IC(0.600 ns) + CELL(1.700 ns) = 10.800 ns; Loc. = LC7_A14; Fanout = 10; REG Node = 'divf_rom_sinx:u2\|sinx_rom:u2\|lpm_counter:Q_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[6\]'" {  } { { "E:/EDA/DDS/10k844/sinx_rom/rom_sinx/db/sf_df_rom_sinx_cmp.qrpt" "" { Report "E:/EDA/DDS/10k844/sinx_rom/rom_sinx/db/sf_df_rom_sinx_cmp.qrpt" Compiler "sf_df_rom_sinx" "UNKNOWN" "V1" "E:/EDA/DDS/10k844/sinx_rom/rom_sinx/db/sf_df_rom_sinx.quartus_db" { Floorplan "E:/EDA/DDS/10k844/sinx_rom/rom_sinx/" "" "2.300 ns" { divf_rom_sinx:u2|sinx_rom:u2|LessThan~64 divf_rom_sinx:u2|sinx_rom:u2|lpm_counter:Q_rtl_0|alt_counter_f10ke:wysi_counter|q[6] } "NODE_NAME" } "" } } { "alt_counter_f10ke.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/alt_counter_f10ke.tdf" 271 2 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "5.800 ns 53.70 % " "Info: Total cell delay = 5.800 ns ( 53.70 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.000 ns 46.30 % " "Info: Total interconnect delay = 5.000 ns ( 46.30 % )" {  } {  } 0}  } { { "E:/EDA/DDS/10k844/sinx_rom/rom_sinx/db/sf_df_rom_sinx_cmp.qrpt" "" { Report "E:/EDA/DDS/10k844/sinx_rom/rom_sinx/db/sf_df_rom_sinx_cmp.qrpt" Compiler "sf_df_rom_sinx" "UNKNOWN" "V1" "E:/EDA/DDS/10k844/sinx_rom/rom_sinx/db/sf_df_rom_sinx.quartus_db" { Floorplan "E:/EDA/DDS/10k844/sinx_rom/rom_sinx/" "" "10.800 ns" { divf_rom_sinx:u2|sinx_rom:u2|lpm_counter:Q_rtl_0|alt_counter_f10ke:wysi_counter|q[3] divf_rom_sinx:u2|sinx_rom:u2|LessThan~63 divf_rom_sinx:u2|sinx_rom:u2|LessThan~64 divf_rom_sinx:u2|sinx_rom:u2|lpm_counter:Q_rtl_0|alt_counter_f10ke:wysi_counter|q[6] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "10.800 ns" { divf_rom_sinx:u2|sinx_rom:u2|lpm_counter:Q_rtl_0|alt_counter_f10ke:wysi_counter|q[3] divf_rom_sinx:u2|sinx_rom:u2|LessThan~63 divf_rom_sinx:u2|sinx_rom:u2|LessThan~64 divf_rom_sinx:u2|sinx_rom:u2|lpm_counter:Q_rtl_0|alt_counter_f10ke:wysi_counter|q[6] } { 0.000ns 2.200ns 2.200ns 0.600ns } { 0.000ns 2.300ns 1.800ns 1.700ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clkk destination 10.900 ns + Shortest register " "Info: + Shortest clock path from clock \"clkk\" to destination register is 10.900 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.800 ns) 2.800 ns clkk 1 CLK PIN_43 15 " "Info: 1: + IC(0.000 ns) + CELL(2.800 ns) = 2.800 ns; Loc. = PIN_43; Fanout = 15; CLK Node = 'clkk'" {  } { { "E:/EDA/DDS/10k844/sinx_rom/rom_sinx/db/sf_df_rom_sinx_cmp.qrpt" "" { Report "E:/EDA/DDS/10k844/sinx_rom/rom_sinx/db/sf_df_rom_sinx_cmp.qrpt" Compiler "sf_df_rom_sinx" "UNKNOWN" "V1" "E:/EDA/DDS/10k844/sinx_rom/rom_sinx/db/sf_df_rom_sinx.quartus_db" { Floorplan "E:/EDA/DDS/10k844/sinx_rom/rom_sinx/" "" "" { clkk } "NODE_NAME" } "" } } { "sf_df_rom_sinx.vhd" "" { Text "E:/EDA/DDS/10k844/sinx_rom/rom_sinx/sf_df_rom_sinx.vhd" 6 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.500 ns) + CELL(1.100 ns) 6.400 ns divf_rom_sinx:u2\|divf:u1\|COUT 2 REG LC1_A8 70 " "Info: 2: + IC(2.500 ns) + CELL(1.100 ns) = 6.400 ns; Loc. = LC1_A8; Fanout = 70; REG Node = 'divf_rom_sinx:u2\|divf:u1\|COUT'" {  } { { "E:/EDA/DDS/10k844/sinx_rom/rom_sinx/db/sf_df_rom_sinx_cmp.qrpt" "" { Report "E:/EDA/DDS/10k844/sinx_rom/rom_sinx/db/sf_df_rom_sinx_cmp.qrpt" Compiler "sf_df_rom_sinx" "UNKNOWN" "V1" "E:/EDA/DDS/10k844/sinx_rom/rom_sinx/db/sf_df_rom_sinx.quartus_db" { Floorplan "E:/EDA/DDS/10k844/sinx_rom/rom_sinx/" "" "3.600 ns" { clkk divf_rom_sinx:u2|divf:u1|COUT } "NODE_NAME" } "" } } { "divf.vhd" "" { Text "E:/EDA/DDS/10k844/sinx_rom/rom_sinx/divf.vhd" 9 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(4.500 ns) + CELL(0.000 ns) 10.900 ns divf_rom_sinx:u2\|sinx_rom:u2\|lpm_counter:Q_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[6\] 3 REG LC7_A14 10 " "Info: 3: + IC(4.500 ns) + CELL(0.000 ns) = 10.900 ns; Loc. = LC7_A14; Fanout = 10; REG Node = 'divf_rom_sinx:u2\|sinx_rom:u2\|lpm_counter:Q_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[6\]'" {  } { { "E:/EDA/DDS/10k844/sinx_rom/rom_sinx/db/sf_df_rom_sinx_cmp.qrpt" "" { Report "E:/EDA/DDS/10k844/sinx_rom/rom_sinx/db/sf_df_rom_sinx_cmp.qrpt" Compiler "sf_df_rom_sinx" "UNKNOWN" "V1" "E:/EDA/DDS/10k844/sinx_rom/rom_sinx/db/sf_df_rom_sinx.quartus_db" { Floorplan "E:/EDA/DDS/10k844/sinx_rom/rom_sinx/" "" "4.500 ns" { divf_rom_sinx:u2|divf:u1|COUT divf_rom_sinx:u2|sinx_rom:u2|lpm_counter:Q_rtl_0|alt_counter_f10ke:wysi_counter|q[6] } "NODE_NAME" } "" } } { "alt_counter_f10ke.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/alt_counter_f10ke.tdf" 271 2 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.900 ns 35.78 % " "Info: Total cell delay = 3.900 ns ( 35.78 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "7.000 ns 64.22 % " "Info: Total interconnect delay = 7.000 ns ( 64.22 % )" {  } {  } 0}  } { { "E:/EDA/DDS/10k844/sinx_rom/rom_sinx/db/sf_df_rom_sinx_cmp.qrpt" "" { Report "E:/EDA/DDS/10k844/sinx_rom/rom_sinx/db/sf_df_rom_sinx_cmp.qrpt" Compiler "sf_df_rom_sinx" "UNKNOWN" "V1" "E:/EDA/DDS/10k844/sinx_rom/rom_sinx/db/sf_df_rom_sinx.quartus_db" { Floorplan "E:/EDA/DDS/10k844/sinx_rom/rom_sinx/" "" "10.900 ns" { clkk divf_rom_sinx:u2|divf:u1|COUT divf_rom_sinx:u2|sinx_rom:u2|lpm_counter:Q_rtl_0|alt_counter_f10ke:wysi_counter|q[6] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "10.900 ns" { clkk clkk~out divf_rom_sinx:u2|divf:u1|COUT divf_rom_sinx:u2|sinx_rom:u2|lpm_counter:Q_rtl_0|alt_counter_f10ke:wysi_counter|q[6] } { 0.000ns 0.000ns 2.500ns 4.500ns } { 0.000ns 2.800ns 1.100ns 0.000ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clkk source 10.900 ns - Longest register " "Info: - Longest clock path from clock \"clkk\" to source register is 10.900 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.800 ns) 2.800 ns clkk 1 CLK PIN_43 15 " "Info: 1: + IC(0.000 ns) + CELL(2.800 ns) = 2.800 ns; Loc. = PIN_43; Fanout = 15; CLK Node = 'clkk'" {  } { { "E:/EDA/DDS/10k844/sinx_rom/rom_sinx/db/sf_df_rom_sinx_cmp.qrpt" "" { Report "E:/EDA/DDS/10k844/sinx_rom/rom_sinx/db/sf_df_rom_sinx_cmp.qrpt" Compiler "sf_df_rom_sinx" "UNKNOWN" "V1" "E:/EDA/DDS/10k844/sinx_rom/rom_sinx/db/sf_df_rom_sinx.quartus_db" { Floorplan "E:/EDA/DDS/10k844/sinx_rom/rom_sinx/" "" "" { clkk } "NODE_NAME" } "" } } { "sf_df_rom_sinx.vhd" "" { Text "E:/EDA/DDS/10k844/sinx_rom/rom_sinx/sf_df_rom_sinx.vhd" 6 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.500 ns) + CELL(1.100 ns) 6.400 ns divf_rom_sinx:u2\|divf:u1\|COUT 2 REG LC1_A8 70 " "Info: 2: + IC(2.500 ns) + CELL(1.100 ns) = 6.400 ns; Loc. = LC1_A8; Fanout = 70; REG Node = 'divf_rom_sinx:u2\|divf:u1\|COUT'" {  } { { "E:/EDA/DDS/10k844/sinx_rom/rom_sinx/db/sf_df_rom_sinx_cmp.qrpt" "" { Report "E:/EDA/DDS/10k844/sinx_rom/rom_sinx/db/sf_df_rom_sinx_cmp.qrpt" Compiler "sf_df_rom_sinx" "UNKNOWN" "V1" "E:/EDA/DDS/10k844/sinx_rom/rom_sinx/db/sf_df_rom_sinx.quartus_db" { Floorplan "E:/EDA/DDS/10k844/sinx_rom/rom_sinx/" "" "3.600 ns" { clkk divf_rom_sinx:u2|divf:u1|COUT } "NODE_NAME" } "" } } { "divf.vhd" "" { Text "E:/EDA/DDS/10k844/sinx_rom/rom_sinx/divf.vhd" 9 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(4.500 ns) + CELL(0.000 ns) 10.900 ns divf_rom_sinx:u2\|sinx_rom:u2\|lpm_counter:Q_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[3\] 3 REG LC4_A14 12 " "Info: 3: + IC(4.500 ns) + CELL(0.000 ns) = 10.900 ns; Loc. = LC4_A14; Fanout = 12; REG Node = 'divf_rom_sinx:u2\|sinx_rom:u2\|lpm_counter:Q_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[3\]'" {  } { { "E:/EDA/DDS/10k844/sinx_rom/rom_sinx/db/sf_df_rom_sinx_cmp.qrpt" "" { Report "E:/EDA/DDS/10k844/sinx_rom/rom_sinx/db/sf_df_rom_sinx_cmp.qrpt" Compiler "sf_df_rom_sinx" "UNKNOWN" "V1" "E:/EDA/DDS/10k844/sinx_rom/rom_sinx/db/sf_df_rom_sinx.quartus_db" { Floorplan "E:/EDA/DDS/10k844/sinx_rom/rom_sinx/" "" "4.500 ns" { divf_rom_sinx:u2|divf:u1|COUT divf_rom_sinx:u2|sinx_rom:u2|lpm_counter:Q_rtl_0|alt_counter_f10ke:wysi_counter|q[3] } "NODE_NAME" } "" } } { "alt_counter_f10ke.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/alt_counter_f10ke.tdf" 271 2 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.900 ns 35.78 % " "Info: Total cell delay = 3.900 ns ( 35.78 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "7.000 ns 64.22 % " "Info: Total interconnect delay = 7.000 ns ( 64.22 % )" {  } {  } 0}  } { { "E:/EDA/DDS/10k844/sinx_rom/rom_sinx/db/sf_df_rom_sinx_cmp.qrpt" "" { Report "E:/EDA/DDS/10k844/sinx_rom/rom_sinx/db/sf_df_rom_sinx_cmp.qrpt" Compiler "sf_df_rom_sinx" "UNKNOWN" "V1" "E:/EDA/DDS/10k844/sinx_rom/rom_sinx/db/sf_df_rom_sinx.quartus_db" { Floorplan "E:/EDA/DDS/10k844/sinx_rom/rom_sinx/" "" "10.900 ns" { clkk divf_rom_sinx:u2|divf:u1|COUT divf_rom_sinx:u2|sinx_rom:u2|lpm_counter:Q_rtl_0|alt_counter_f10ke:wysi_counter|q[3] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "10.900 ns" { clkk clkk~out divf_rom_sinx:u2|divf:u1|COUT divf_rom_sinx:u2|sinx_rom:u2|lpm_counter:Q_rtl_0|alt_counter_f10ke:wysi_counter|q[3] } { 0.000ns 0.000ns 2.500ns 4.500ns } { 0.000ns 2.800ns 1.100ns 0.000ns } } }  } 0}  } { { "E:/EDA/DDS/10k844/sinx_rom/rom_sinx/db/sf_df_rom_sinx_cmp.qrpt" "" { Report "E:/EDA/DDS/10k844/sinx_rom/rom_sinx/db/sf_df_rom_sinx_cmp.qrpt" Compiler "sf_df_rom_sinx" "UNKNOWN" "V1" "E:/EDA/DDS/10k844/sinx_rom/rom_sinx/db/sf_df_rom_sinx.quartus_db" { Floorplan "E:/EDA/DDS/10k844/sinx_rom/rom_sinx/" "" "10.900 ns" { clkk divf_rom_sinx:u2|divf:u1|COUT divf_rom_sinx:u2|sinx_rom:u2|lpm_counter:Q_rtl_0|alt_counter_f10ke:wysi_counter|q[6] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "10.900 ns" { clkk clkk~out divf_rom_sinx:u2|divf:u1|COUT divf_rom_sinx:u2|sinx_rom:u2|lpm_counter:Q_rtl_0|alt_counter_f10ke:wysi_counter|q[6] } { 0.000ns 0.000ns 2.500ns 4.500ns } { 0.000ns 2.800ns 1.100ns 0.000ns } } } { "E:/EDA/DDS/10k844/sinx_rom/rom_sinx/db/sf_df_rom_sinx_cmp.qrpt" "" { Report "E:/EDA/DDS/10k844/sinx_rom/rom_sinx/db/sf_df_rom_sinx_cmp.qrpt" Compiler "sf_df_rom_sinx" "UNKNOWN" "V1" "E:/EDA/DDS/10k844/sinx_rom/rom_sinx/db/sf_df_rom_sinx.quartus_db" { Floorplan "E:/EDA/DDS/10k844/sinx_rom/rom_sinx/" "" "10.900 ns" { clkk divf_rom_sinx:u2|divf:u1|COUT divf_rom_sinx:u2|sinx_rom:u2|lpm_counter:Q_rtl_0|alt_counter_f10ke:wysi_counter|q[3] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "10.900 ns" { clkk clkk~out divf_rom_sinx:u2|divf:u1|COUT divf_rom_sinx:u2|sinx_rom:u2|lpm_counter:Q_rtl_0|alt_counter_f10ke:wysi_counter|q[3] } { 0.000ns 0.000ns 2.500ns 4.500ns } { 0.000ns 2.800ns 1.100ns 0.000ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.100 ns + " "Info: + Micro clock to output delay of source is 1.100 ns" {  } { { "alt_counter_f10ke.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/alt_counter_f10ke.tdf" 271 2 0 } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "2.500 ns + " "Info: + Micro setup delay of destination is 2.500 ns" {  } { { "alt_counter_f10ke.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/alt_counter_f10ke.tdf" 271 2 0 } }  } 0}  } { { "E:/EDA/DDS/10k844/sinx_rom/rom_sinx/db/sf_df_rom_sinx_cmp.qrpt" "" { Report "E:/EDA/DDS/10k844/sinx_rom/rom_sinx/db/sf_df_rom_sinx_cmp.qrpt" Compiler "sf_df_rom_sinx" "UNKNOWN" "V1" "E:/EDA/DDS/10k844/sinx_rom/rom_sinx/db/sf_df_rom_sinx.quartus_db" { Floorplan "E:/EDA/DDS/10k844/sinx_rom/rom_sinx/" "" "10.800 ns" { divf_rom_sinx:u2|sinx_rom:u2|lpm_counter:Q_rtl_0|alt_counter_f10ke:wysi_counter|q[3] divf_rom_sinx:u2|sinx_rom:u2|LessThan~63 divf_rom_sinx:u2|sinx_rom:u2|LessThan~64 divf_rom_sinx:u2|sinx_rom:u2|lpm_counter:Q_rtl_0|alt_counter_f10ke:wysi_counter|q[6] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "10.800 ns" { divf_rom_sinx:u2|sinx_rom:u2|lpm_counter:Q_rtl_0|alt_counter_f10ke:wysi_counter|q[3] divf_rom_sinx:u2|sinx_rom:u2|LessThan~63 divf_rom_sinx:u2|sinx_rom:u2|LessThan~64 divf_rom_sinx:u2|sinx_rom:u2|lpm_counter:Q_rtl_0|alt_counter_f10ke:wysi_counter|q[6] } { 0.000ns 2.200ns 2.200ns 0.600ns } { 0.000ns 2.300ns 1.800ns 1.700ns } } } { "E:/EDA/DDS/10k844/sinx_rom/rom_sinx/db/sf_df_rom_sinx_cmp.qrpt" "" { Report "E:/EDA/DDS/10k844/sinx_rom/rom_sinx/db/sf_df_rom_sinx_cmp.qrpt" Compiler "sf_df_rom_sinx" "UNKNOWN" "V1" "E:/EDA/DDS/10k844/sinx_rom/rom_sinx/db/sf_df_rom_sinx.quartus_db" { Floorplan "E:/EDA/DDS/10k844/sinx_rom/rom_sinx/" "" "10.900 ns" { clkk divf_rom_sinx:u2|divf:u1|COUT divf_rom_sinx:u2|sinx_rom:u2|lpm_counter:Q_rtl_0|alt_counter_f10ke:wysi_counter|q[6] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "10.900 ns" { clkk clkk~out divf_rom_sinx:u2|divf:u1|COUT divf_rom_sinx:u2|sinx_rom:u2|lpm_counter:Q_rtl_0|alt_counter_f10ke:wysi_counter|q[6] } { 0.000ns 0.000ns 2.500ns 4.500ns } { 0.000ns 2.800ns 1.100ns 0.000ns } } } { "E:/EDA/DDS/10k844/sinx_rom/rom_sinx/db/sf_df_rom_sinx_cmp.qrpt" "" { Report "E:/EDA/DDS/10k844/sinx_rom/rom_sinx/db/sf_df_rom_sinx_cmp.qrpt" Compiler "sf_df_rom_sinx" "UNKNOWN" "V1" "E:/EDA/DDS/10k844/sinx_rom/rom_sinx/db/sf_df_rom_sinx.quartus_db" { Floorplan "E:/EDA/DDS/10k844/sinx_rom/rom_sinx/" "" "10.900 ns" { clkk divf_rom_sinx:u2|divf:u1|COUT divf_rom_sinx:u2|sinx_rom:u2|lpm_counter:Q_rtl_0|alt_counter_f10ke:wysi_counter|q[3] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "10.900 ns" { clkk clkk~out divf_rom_sinx:u2|divf:u1|COUT divf_rom_sinx:u2|sinx_rom:u2|lpm_counter:Q_rtl_0|alt_counter_f10ke:wysi_counter|q[3] } { 0.000ns 0.000ns 2.500ns 4.500ns } { 0.000ns 2.800ns 1.100ns 0.000ns } } }  } 0}
{ "Info" "ITDB_TSU_RESULT" "SCANCNT4B:u1\|lpm_counter:CNT4_rtl_2\|alt_counter_f10ke:wysi_counter\|q\[3\] en clkk 3.300 ns register " "Info: tsu for register \"SCANCNT4B:u1\|lpm_counter:CNT4_rtl_2\|alt_counter_f10ke:wysi_counter\|q\[3\]\" (data pin = \"en\", clock pin = \"clkk\") is 3.300 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.100 ns + Longest pin register " "Info: + Longest pin to register delay is 6.100 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.800 ns) 2.800 ns en 1 PIN PIN_2 14 " "Info: 1: + IC(0.000 ns) + CELL(2.800 ns) = 2.800 ns; Loc. = PIN_2; Fanout = 14; PIN Node = 'en'" {  } { { "E:/EDA/DDS/10k844/sinx_rom/rom_sinx/db/sf_df_rom_sinx_cmp.qrpt" "" { Report "E:/EDA/DDS/10k844/sinx_rom/rom_sinx/db/sf_df_rom_sinx_cmp.qrpt" Compiler "sf_df_rom_sinx" "UNKNOWN" "V1" "E:/EDA/DDS/10k844/sinx_rom/rom_sinx/db/sf_df_rom_sinx.quartus_db" { Floorplan "E:/EDA/DDS/10k844/sinx_rom/rom_sinx/" "" "" { en } "NODE_NAME" } "" } } { "sf_df_rom_sinx.vhd" "" { Text "E:/EDA/DDS/10k844/sinx_rom/rom_sinx/sf_df_rom_sinx.vhd" 6 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.600 ns) + CELL(1.700 ns) 6.100 ns SCANCNT4B:u1\|lpm_counter:CNT4_rtl_2\|alt_counter_f10ke:wysi_counter\|q\[3\] 2 REG LC8_A9 2 " "Info: 2: + IC(1.600 ns) + CELL(1.700 ns) = 6.100 ns; Loc. = LC8_A9; Fanout = 2; REG Node = 'SCANCNT4B:u1\|lpm_counter:CNT4_rtl_2\|alt_counter_f10ke:wysi_counter\|q\[3\]'" {  } { { "E:/EDA/DDS/10k844/sinx_rom/rom_sinx/db/sf_df_rom_sinx_cmp.qrpt" "" { Report "E:/EDA/DDS/10k844/sinx_rom/rom_sinx/db/sf_df_rom_sinx_cmp.qrpt" Compiler "sf_df_rom_sinx" "UNKNOWN" "V1" "E:/EDA/DDS/10k844/sinx_rom/rom_sinx/db/sf_df_rom_sinx.quartus_db" { Floorplan "E:/EDA/DDS/10k844/sinx_rom/rom_sinx/" "" "3.300 ns" { en SCANCNT4B:u1|lpm_counter:CNT4_rtl_2|alt_counter_f10ke:wysi_counter|q[3] } "NODE_NAME" } "" } } { "alt_counter_f10ke.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/alt_counter_f10ke.tdf" 271 2 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.500 ns 73.77 % " "Info: Total cell delay = 4.500 ns ( 73.77 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.600 ns 26.23 % " "Info: Total interconnect delay = 1.600 ns ( 26.23 % )" {  } {  } 0}  } { { "E:/EDA/DDS/10k844/sinx_rom/rom_sinx/db/sf_df_rom_sinx_cmp.qrpt" "" { Report "E:/EDA/DDS/10k844/sinx_rom/rom_sinx/db/sf_df_rom_sinx_cmp.qrpt" Compiler "sf_df_rom_sinx" "UNKNOWN" "V1" "E:/EDA/DDS/10k844/sinx_rom/rom_sinx/db/sf_df_rom_sinx.quartus_db" { Floorplan "E:/EDA/DDS/10k844/sinx_rom/rom_sinx/" "" "6.100 ns" { en SCANCNT4B:u1|lpm_counter:CNT4_rtl_2|alt_counter_f10ke:wysi_counter|q[3] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "6.100 ns" { en en~out SCANCNT4B:u1|lpm_counter:CNT4_rtl_2|alt_counter_f10ke:wysi_counter|q[3] } { 0.000ns 0.000ns 1.600ns } { 0.000ns 2.800ns 1.700ns } } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "2.500 ns + " "Info: + Micro setup delay of destination is 2.500 ns" {  } { { "alt_counter_f10ke.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/alt_counter_f10ke.tdf" 271 2 0 } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clkk destination 5.300 ns - Shortest register " "Info: - Shortest clock path from clock \"clkk\" to destination register is 5.300 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.800 ns) 2.800 ns clkk 1 CLK PIN_43 15 " "Info: 1: + IC(0.000 ns) + CELL(2.800 ns) = 2.800 ns; Loc. = PIN_43; Fanout = 15; CLK Node = 'clkk'" {  } { { "E:/EDA/DDS/10k844/sinx_rom/rom_sinx/db/sf_df_rom_sinx_cmp.qrpt" "" { Report "E:/EDA/DDS/10k844/sinx_rom/rom_sinx/db/sf_df_rom_sinx_cmp.qrpt" Compiler "sf_df_rom_sinx" "UNKNOWN" "V1" "E:/EDA/DDS/10k844/sinx_rom/rom_sinx/db/sf_df_rom_sinx.quartus_db" { Floorplan "E:/EDA/DDS/10k844/sinx_rom/rom_sinx/" "" "" { clkk } "NODE_NAME" } "" } } { "sf_df_rom_sinx.vhd" "" { Text "E:/EDA/DDS/10k844/sinx_rom/rom_sinx/sf_df_rom_sinx.vhd" 6 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.500 ns) + CELL(0.000 ns) 5.300 ns SCANCNT4B:u1\|lpm_counter:CNT4_rtl_2\|alt_counter_f10ke:wysi_counter\|q\[3\] 2 REG LC8_A9 2 " "Info: 2: + IC(2.500 ns) + CELL(0.000 ns) = 5.300 ns; Loc. = LC8_A9; Fanout = 2; REG Node = 'SCANCNT4B:u1\|lpm_counter:CNT4_rtl_2\|alt_counter_f10ke:wysi_counter\|q\[3\]'" {  } { { "E:/EDA/DDS/10k844/sinx_rom/rom_sinx/db/sf_df_rom_sinx_cmp.qrpt" "" { Report "E:/EDA/DDS/10k844/sinx_rom/rom_sinx/db/sf_df_rom_sinx_cmp.qrpt" Compiler "sf_df_rom_sinx" "UNKNOWN" "V1" "E:/EDA/DDS/10k844/sinx_rom/rom_sinx/db/sf_df_rom_sinx.quartus_db" { Floorplan "E:/EDA/DDS/10k844/sinx_rom/rom_sinx/" "" "2.500 ns" { clkk SCANCNT4B:u1|lpm_counter:CNT4_rtl_2|alt_counter_f10ke:wysi_counter|q[3] } "NODE_NAME" } "" } } { "alt_counter_f10ke.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/alt_counter_f10ke.tdf" 271 2 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.800 ns 52.83 % " "Info: Total cell delay = 2.800 ns ( 52.83 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.500 ns 47.17 % " "Info: Total interconnect delay = 2.500 ns ( 47.17 % )" {  } {  } 0}  } { { "E:/EDA/DDS/10k844/sinx_rom/rom_sinx/db/sf_df_rom_sinx_cmp.qrpt" "" { Report "E:/EDA/DDS/10k844/sinx_rom/rom_sinx/db/sf_df_rom_sinx_cmp.qrpt" Compiler "sf_df_rom_sinx" "UNKNOWN" "V1" "E:/EDA/DDS/10k844/sinx_rom/rom_sinx/db/sf_df_rom_sinx.quartus_db" { Floorplan "E:/EDA/DDS/10k844/sinx_rom/rom_sinx/" "" "5.300 ns" { clkk SCANCNT4B:u1|lpm_counter:CNT4_rtl_2|alt_counter_f10ke:wysi_counter|q[3] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "5.300 ns" { clkk clkk~out SCANCNT4B:u1|lpm_counter:CNT4_rtl_2|alt_counter_f10ke:wysi_counter|q[3] } { 0.000ns 0.000ns 2.500ns } { 0.000ns 2.800ns 0.000ns } } }  } 0}  } { { "E:/EDA/DDS/10k844/sinx_rom/rom_sinx/db/sf_df_rom_sinx_cmp.qrpt" "" { Report "E:/EDA/DDS/10k844/sinx_rom/rom_sinx/db/sf_df_rom_sinx_cmp.qrpt" Compiler "sf_df_rom_sinx" "UNKNOWN" "V1" "E:/EDA/DDS/10k844/sinx_rom/rom_sinx/db/sf_df_rom_sinx.quartus_db" { Floorplan "E:/EDA/DDS/10k844/sinx_rom/rom_sinx/" "" "6.100 ns" { en SCANCNT4B:u1|lpm_counter:CNT4_rtl_2|alt_counter_f10ke:wysi_counter|q[3] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "6.100 ns" { en en~out SCANCNT4B:u1|lpm_counter:CNT4_rtl_2|alt_counter_f10ke:wysi_counter|q[3] } { 0.000ns 0.000ns 1.600ns } { 0.000ns 2.800ns 1.700ns } } } { "E:/EDA/DDS/10k844/sinx_rom/rom_sinx/db/sf_df_rom_sinx_cmp.qrpt" "" { Report "E:/EDA/DDS/10k844/sinx_rom/rom_sinx/db/sf_df_rom_sinx_cmp.qrpt" Compiler "sf_df_rom_sinx" "UNKNOWN" "V1" "E:/EDA/DDS/10k844/sinx_rom/rom_sinx/db/sf_df_rom_sinx.quartus_db" { Floorplan "E:/EDA/DDS/10k844/sinx_rom/rom_sinx/" "" "5.300 ns" { clkk SCANCNT4B:u1|lpm_counter:CNT4_rtl_2|alt_counter_f10ke:wysi_counter|q[3] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "5.300 ns" { clkk clkk~out SCANCNT4B:u1|lpm_counter:CNT4_rtl_2|alt_counter_f10ke:wysi_counter|q[3] } { 0.000ns 0.000ns 2.500ns } { 0.000ns 2.800ns 0.000ns } } }  } 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clkk Da_data\[4\] divf_rom_sinx:u2\|sinx_rom:u2\|data_rom_10k:u1\|lpm_rom:lpm_rom_component\|altrom:srom\|q\[4\]~reg_ra0 35.800 ns memory " "Info: tco from clock \"clkk\" to destination pin \"Da_data\[4\]\" through memory \"divf_rom_sinx:u2\|sinx_rom:u2\|data_rom_10k:u1\|lpm_rom:lpm_rom_component\|altrom:srom\|q\[4\]~reg_ra0\" is 35.800 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clkk source 10.900 ns + Longest memory " "Info: + Longest clock path from clock \"clkk\" to source memory is 10.900 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.800 ns) 2.800 ns clkk 1 CLK PIN_43 15 " "Info: 1: + IC(0.000 ns) + CELL(2.800 ns) = 2.800 ns; Loc. = PIN_43; Fanout = 15; CLK Node = 'clkk'" {  } { { "E:/EDA/DDS/10k844/sinx_rom/rom_sinx/db/sf_df_rom_sinx_cmp.qrpt" "" { Report "E:/EDA/DDS/10k844/sinx_rom/rom_sinx/db/sf_df_rom_sinx_cmp.qrpt" Compiler "sf_df_rom_sinx" "UNKNOWN" "V1" "E:/EDA/DDS/10k844/sinx_rom/rom_sinx/db/sf_df_rom_sinx.quartus_db" { Floorplan "E:/EDA/DDS/10k844/sinx_rom/rom_sinx/" "" "" { clkk } "NODE_NAME" } "" } } { "sf_df_rom_sinx.vhd" "" { Text "E:/EDA/DDS/10k844/sinx_rom/rom_sinx/sf_df_rom_sinx.vhd" 6 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.500 ns) + CELL(1.100 ns) 6.400 ns divf_rom_sinx:u2\|divf:u1\|COUT 2 REG LC1_A8 70 " "Info: 2: + IC(2.500 ns) + CELL(1.100 ns) = 6.400 ns; Loc. = LC1_A8; Fanout = 70; REG Node = 'divf_rom_sinx:u2\|divf:u1\|COUT'" {  } { { "E:/EDA/DDS/10k844/sinx_rom/rom_sinx/db/sf_df_rom_sinx_cmp.qrpt" "" { Report "E:/EDA/DDS/10k844/sinx_rom/rom_sinx/db/sf_df_rom_sinx_cmp.qrpt" Compiler "sf_df_rom_sinx" "UNKNOWN" "V1" "E:/EDA/DDS/10k844/sinx_rom/rom_sinx/db/sf_df_rom_sinx.quartus_db" { Floorplan "E:/EDA/DDS/10k844/sinx_rom/rom_sinx/" "" "3.600 ns" { clkk divf_rom_sinx:u2|divf:u1|COUT } "NODE_NAME" } "" } } { "divf.vhd" "" { Text "E:/EDA/DDS/10k844/sinx_rom/rom_sinx/divf.vhd" 9 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(4.500 ns) + CELL(0.000 ns) 10.900 ns divf_rom_sinx:u2\|sinx_rom:u2\|data_rom_10k:u1\|lpm_rom:lpm_rom_component\|altrom:srom\|q\[4\]~reg_ra0 3 MEM EC7_A 1 " "Info: 3: + IC(4.500 ns) + CELL(0.000 ns) = 10.900 ns; Loc. = EC7_A; Fanout = 1; MEM Node = 'divf_rom_sinx:u2\|sinx_rom:u2\|data_rom_10k:u1\|lpm_rom:lpm_rom_component\|altrom:srom\|q\[4\]~reg_ra0'" {  } { { "E:/EDA/DDS/10k844/sinx_rom/rom_sinx/db/sf_df_rom_sinx_cmp.qrpt" "" { Report "E:/EDA/DDS/10k844/sinx_rom/rom_sinx/db/sf_df_rom_sinx_cmp.qrpt" Compiler "sf_df_rom_sinx" "UNKNOWN" "V1" "E:/EDA/DDS/10k844/sinx_rom/rom_sinx/db/sf_df_rom_sinx.quartus_db" { Floorplan "E:/EDA/DDS/10k844/sinx_rom/rom_sinx/" "" "4.500 ns" { divf_rom_sinx:u2|divf:u1|COUT divf_rom_sinx:u2|sinx_rom:u2|data_rom_10k:u1|lpm_rom:lpm_rom_component|altrom:srom|q[4]~reg_ra0 } "NODE_NAME" } "" } } { "altrom.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/altrom.tdf" 80 2 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.900 ns 35.78 % " "Info: Total cell delay = 3.900 ns ( 35.78 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "7.000 ns 64.22 % " "Info: Total interconnect delay = 7.000 ns ( 64.22 % )" {  } {  } 0}  } { { "E:/EDA/DDS/10k844/sinx_rom/rom_sinx/db/sf_df_rom_sinx_cmp.qrpt" "" { Report "E:/EDA/DDS/10k844/sinx_rom/rom_sinx/db/sf_df_rom_sinx_cmp.qrpt" Compiler "sf_df_rom_sinx" "UNKNOWN" "V1" "E:/EDA/DDS/10k844/sinx_rom/rom_sinx/db/sf_df_rom_sinx.quartus_db" { Floorplan "E:/EDA/DDS/10k844/sinx_rom/rom_sinx/" "" "10.900 ns" { clkk divf_rom_sinx:u2|divf:u1|COUT divf_rom_sinx:u2|sinx_rom:u2|data_rom_10k:u1|lpm_rom:lpm_rom_component|altrom:srom|q[4]~reg_ra0 } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "10.900 ns" { clkk clkk~out divf_rom_sinx:u2|divf:u1|COUT divf_rom_sinx:u2|sinx_rom:u2|data_rom_10k:u1|lpm_rom:lpm_rom_component|altrom:srom|q[4]~reg_ra0 } { 0.000ns 0.000ns 2.500ns 4.500ns } { 0.000ns 2.800ns 1.100ns 0.000ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.600 ns + " "Info: + Micro clock to output delay of source is 0.600 ns" {  } { { "altrom.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/altrom.tdf" 80 2 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "24.300 ns + Longest memory pin " "Info: + Longest memory to pin delay is 24.300 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns divf_rom_sinx:u2\|sinx_rom:u2\|data_rom_10k:u1\|lpm_rom:lpm_rom_component\|altrom:srom\|q\[4\]~reg_ra0 1 MEM EC7_A 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = EC7_A; Fanout = 1; MEM Node = 'divf_rom_sinx:u2\|sinx_rom:u2\|data_rom_10k:u1\|lpm_rom:lpm_rom_component\|altrom:srom\|q\[4\]~reg_ra0'" {  } { { "E:/EDA/DDS/10k844/sinx_rom/rom_sinx/db/sf_df_rom_sinx_cmp.qrpt" "" { Report "E:/EDA/DDS/10k844/sinx_rom/rom_sinx/db/sf_df_rom_sinx_cmp.qrpt" Compiler "sf_df_rom_sinx" "UNKNOWN" "V1" "E:/EDA/DDS/10k844/sinx_rom/rom_sinx/db/sf_df_rom_sinx.quartus_db" { Floorplan "E:/EDA/DDS/10k844/sinx_rom/rom_sinx/" "" "" { divf_rom_sinx:u2|sinx_rom:u2|data_rom_10k:u1|lpm_rom:lpm_rom_component|altrom:srom|q[4]~reg_ra0 } "NODE_NAME" } "" } } { "altrom.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/altrom.tdf" 80 2 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(10.700 ns) 10.700 ns divf_rom_sinx:u2\|sinx_rom:u2\|data_rom_10k:u1\|lpm_rom:lpm_rom_component\|altrom:srom\|q\[4\]~mem_cell_ra0 2 MEM EC7_A 1 " "Info: 2: + IC(0.000 ns) + CELL(10.700 ns) = 10.700 ns; Loc. = EC7_A; Fanout = 1; MEM Node = 'divf_rom_sinx:u2\|sinx_rom:u2\|data_rom_10k:u1\|lpm_rom:lpm_rom_component\|altrom:srom\|q\[4\]~mem_cell_ra0'" {  } { { "E:/EDA/DDS/10k844/sinx_rom/rom_sinx/db/sf_df_rom_sinx_cmp.qrpt" "" { Report "E:/EDA/DDS/10k844/sinx_rom/rom_sinx/db/sf_df_rom_sinx_cmp.qrpt" Compiler "sf_df_rom_sinx" "UNKNOWN" "V1" "E:/EDA/DDS/10k844/sinx_rom/rom_sinx/db/sf_df_rom_sinx.quartus_db" { Floorplan "E:/EDA/DDS/10k844/sinx_rom/rom_sinx/" "" "10.700 ns" { divf_rom_sinx:u2|sinx_rom:u2|data_rom_10k:u1|lpm_rom:lpm_rom_component|altrom:srom|q[4]~reg_ra0 divf_rom_sinx:u2|sinx_rom:u2|data_rom_10k:u1|lpm_rom:lpm_rom_component|altrom:srom|q[4]~mem_cell_ra0 } "NODE_NAME" } "" } } { "altrom.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/altrom.tdf" 80 2 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.500 ns) 13.200 ns divf_rom_sinx:u2\|sinx_rom:u2\|data_rom_10k:u1\|lpm_rom:lpm_rom_component\|altrom:srom\|q\[4\] 3 MEM EC7_A 1 " "Info: 3: + IC(0.000 ns) + CELL(2.500 ns) = 13.200 ns; Loc. = EC7_A; Fanout = 1; MEM Node = 'divf_rom_sinx:u2\|sinx_rom:u2\|data_rom_10k:u1\|lpm_rom:lpm_rom_component\|altrom:srom\|q\[4\]'" {  } { { "E:/EDA/DDS/10k844/sinx_rom/rom_sinx/db/sf_df_rom_sinx_cmp.qrpt" "" { Report "E:/EDA/DDS/10k844/sinx_rom/rom_sinx/db/sf_df_rom_sinx_cmp.qrpt" Compiler "sf_df_rom_sinx" "UNKNOWN" "V1" "E:/EDA/DDS/10k844/sinx_rom/rom_sinx/db/sf_df_rom_sinx.quartus_db" { Floorplan "E:/EDA/DDS/10k844/sinx_rom/rom_sinx/" "" "2.500 ns" { divf_rom_sinx:u2|sinx_rom:u2|data_rom_10k:u1|lpm_rom:lpm_rom_component|altrom:srom|q[4]~mem_cell_ra0 divf_rom_sinx:u2|sinx_rom:u2|data_rom_10k:u1|lpm_rom:lpm_rom_component|altrom:srom|q[4] } "NODE_NAME" } "" } } { "altrom.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/altrom.tdf" 80 2 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(6.000 ns) + CELL(5.100 ns) 24.300 ns Da_data\[4\] 4 PIN PIN_71 0 " "Info: 4: + IC(6.000 ns) + CELL(5.100 ns) = 24.300 ns; Loc. = PIN_71; Fanout = 0; PIN Node = 'Da_data\[4\]'" {  } { { "E:/EDA/DDS/10k844/sinx_rom/rom_sinx/db/sf_df_rom_sinx_cmp.qrpt" "" { Report "E:/EDA/DDS/10k844/sinx_rom/rom_sinx/db/sf_df_rom_sinx_cmp.qrpt" Compiler "sf_df_rom_sinx" "UNKNOWN" "V1" "E:/EDA/DDS/10k844/sinx_rom/rom_sinx/db/sf_df_rom_sinx.quartus_db" { Floorplan "E:/EDA/DDS/10k844/sinx_rom/rom_sinx/" "" "11.100 ns" { divf_rom_sinx:u2|sinx_rom:u2|data_rom_10k:u1|lpm_rom:lpm_rom_component|altrom:srom|q[4] Da_data[4] } "NODE_NAME" } "" } } { "sf_df_rom_sinx.vhd" "" { Text "E:/EDA/DDS/10k844/sinx_rom/rom_sinx/sf_df_rom_sinx.vhd" 8 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "18.300 ns 75.31 % " "Info: Total cell delay = 18.300 ns ( 75.31 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.000 ns 24.69 % " "Info: Total interconnect delay = 6.000 ns ( 24.69 % )" {  } {  } 0}  } { { "E:/EDA/DDS/10k844/sinx_rom/rom_sinx/db/sf_df_rom_sinx_cmp.qrpt" "" { Report "E:/EDA/DDS/10k844/sinx_rom/rom_sinx/db/sf_df_rom_sinx_cmp.qrpt" Compiler "sf_df_rom_sinx" "UNKNOWN" "V1" "E:/EDA/DDS/10k844/sinx_rom/rom_sinx/db/sf_df_rom_sinx.quartus_db" { Floorplan "E:/EDA/DDS/10k844/sinx_rom/rom_sinx/" "" "24.300 ns" { divf_rom_sinx:u2|sinx_rom:u2|data_rom_10k:u1|lpm_rom:lpm_rom_component|altrom:srom|q[4]~reg_ra0 divf_rom_sinx:u2|sinx_rom:u2|data_rom_10k:u1|lpm_rom:lpm_rom_component|altrom:srom|q[4]~mem_cell_ra0 divf_rom_sinx:u2|sinx_rom:u2|data_rom_10k:u1|lpm_rom:lpm_rom_component|altrom:srom|q[4] Da_data[4] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "24.300 ns" { divf_rom_sinx:u2|sinx_rom:u2|data_rom_10k:u1|lpm_rom:lpm_rom_component|altrom:srom|q[4]~reg_ra0 divf_rom_sinx:u2|sinx_rom:u2|data_rom_10k:u1|lpm_rom:lpm_rom_component|altrom:srom|q[4]~mem_cell_ra0 divf_rom_sinx:u2|sinx_rom:u2|data_rom_10k:u1|lpm_rom:lpm_rom_component|altrom:srom|q[4] Da_data[4] } { 0.000ns 0.000ns 0.000ns 6.000ns } { 0.000ns 10.700ns 2.500ns 5.100ns } } }  } 0}  } { { "E:/EDA/DDS/10k844/sinx_rom/rom_sinx/db/sf_df_rom_sinx_cmp.qrpt" "" { Report "E:/EDA/DDS/10k844/sinx_rom/rom_sinx/db/sf_df_rom_sinx_cmp.qrpt" Compiler "sf_df_rom_sinx" "UNKNOWN" "V1" "E:/EDA/DDS/10k844/sinx_rom/rom_sinx/db/sf_df_rom_sinx.quartus_db" { Floorplan "E:/EDA/DDS/10k844/sinx_rom/rom_sinx/" "" "10.900 ns" { clkk divf_rom_sinx:u2|divf:u1|COUT divf_rom_sinx:u2|sinx_rom:u2|data_rom_10k:u1|lpm_rom:lpm_rom_component|altrom:srom|q[4]~reg_ra0 } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "10.900 ns" { clkk clkk~out divf_rom_sinx:u2|divf:u1|COUT divf_rom_sinx:u2|sinx_rom:u2|data_rom_10k:u1|lpm_rom:lpm_rom_component|altrom:srom|q[4]~reg_ra0 } { 0.000ns 0.000ns 2.500ns 4.500ns } { 0.000ns 2.800ns 1.100ns 0.000ns } } } { "E:/EDA/DDS/10k844/sinx_rom/rom_sinx/db/sf_df_rom_sinx_cmp.qrpt" "" { Report "E:/EDA/DDS/10k844/sinx_rom/rom_sinx/db/sf_df_rom_sinx_cmp.qrpt" Compiler "sf_df_rom_sinx" "UNKNOWN" "V1" "E:/EDA/DDS/10k844/sinx_rom/rom_sinx/db/sf_df_rom_sinx.quartus_db" { Floorplan "E:/EDA/DDS/10k844/sinx_rom/rom_sinx/" "" "24.300 ns" { divf_rom_sinx:u2|sinx_rom:u2|data_rom_10k:u1|lpm_rom:lpm_rom_component|altrom:srom|q[4]~reg_ra0 divf_rom_sinx:u2|sinx_rom:u2|data_rom_10k:u1|lpm_rom:lpm_rom_component|altrom:srom|q[4]~mem_cell_ra0 divf_rom_sinx:u2|sinx_rom:u2|data_rom_10k:u1|lpm_rom:lpm_rom_component|altrom:srom|q[4] Da_data[4] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "24.300 ns" { divf_rom_sinx:u2|sinx_rom:u2|data_rom_10k:u1|lpm_rom:lpm_rom_component|altrom:srom|q[4]~reg_ra0 divf_rom_sinx:u2|sinx_rom:u2|data_rom_10k:u1|lpm_rom:lpm_rom_component|altrom:srom|q[4]~mem_cell_ra0 divf_rom_sinx:u2|sinx_rom:u2|data_rom_10k:u1|lpm_rom:lpm_rom_component|altrom:srom|q[4] Da_data[4] } { 0.000ns 0.000ns 0.000ns 6.000ns } { 0.000ns 10.700ns 2.500ns 5.100ns } } }  } 0}