sf_df_rom_sinx.fit.eqn

来自「在EDA开发软件QuartusII上利用VHDL语言实现DDS信号发生器」· EQN 代码 · 共 433 行 · 第 1/2 页

-- Copyright (C) 1991-2005 Altera Corporation
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--G1_cout is divf_rom_sinx:u2|sinx_rom:u2|cout at LC4_C13
--operation mode is normal

G1_cout_lut_out = !G1L3 & E3_q[2] & E3_q[1] & E3_q[0];
G1_cout = DFFEA(G1_cout_lut_out, GLOBAL(F1_COUT), , , , , );

--G1L2Q is divf_rom_sinx:u2|sinx_rom:u2|cout~0 at LC4_C13
--operation mode is normal

G1L2Q = G1_cout;


--K1_q[0] is divf_rom_sinx:u2|sinx_rom:u2|data_rom_10k:u1|lpm_rom:lpm_rom_component|altrom:srom|q[0] at EC4_C
K1_q[0]_clock_0 = GLOBAL(F1_COUT);
K1_q[0]_write_address = WR_ADDR(E3_q[0], E3_q[1], E3_q[2], E3_q[3], E3_q[4], E3_q[5], E3_q[6]);
K1_q[0]_read_address = RD_ADDR(E3_q[0], E3_q[1], E3_q[2], E3_q[3], E3_q[4], E3_q[5], E3_q[6]);
K1_q[0] = MEMORY_SEGMENT(, , K1_q[0]_clock_0, , , , , , K1_q[0]_write_address, K1_q[0]_read_address);


--K1_q[1] is divf_rom_sinx:u2|sinx_rom:u2|data_rom_10k:u1|lpm_rom:lpm_rom_component|altrom:srom|q[1] at EC2_C
K1_q[1]_clock_0 = GLOBAL(F1_COUT);
K1_q[1]_write_address = WR_ADDR(E3_q[0], E3_q[1], E3_q[2], E3_q[3], E3_q[4], E3_q[5], E3_q[6]);
K1_q[1]_read_address = RD_ADDR(E3_q[0], E3_q[1], E3_q[2], E3_q[3], E3_q[4], E3_q[5], E3_q[6]);
K1_q[1] = MEMORY_SEGMENT(, , K1_q[1]_clock_0, , , , , , K1_q[1]_write_address, K1_q[1]_read_address);


--K1_q[2] is divf_rom_sinx:u2|sinx_rom:u2|data_rom_10k:u1|lpm_rom:lpm_rom_component|altrom:srom|q[2] at EC1_C
K1_q[2]_clock_0 = GLOBAL(F1_COUT);
K1_q[2]_write_address = WR_ADDR(E3_q[0], E3_q[1], E3_q[2], E3_q[3], E3_q[4], E3_q[5], E3_q[6]);
K1_q[2]_read_address = RD_ADDR(E3_q[0], E3_q[1], E3_q[2], E3_q[3], E3_q[4], E3_q[5], E3_q[6]);
K1_q[2] = MEMORY_SEGMENT(, , K1_q[2]_clock_0, , , , , , K1_q[2]_write_address, K1_q[2]_read_address);


--K1_q[3] is divf_rom_sinx:u2|sinx_rom:u2|data_rom_10k:u1|lpm_rom:lpm_rom_component|altrom:srom|q[3] at EC8_C
K1_q[3]_clock_0 = GLOBAL(F1_COUT);
K1_q[3]_write_address = WR_ADDR(E3_q[0], E3_q[1], E3_q[2], E3_q[3], E3_q[4], E3_q[5], E3_q[6]);
K1_q[3]_read_address = RD_ADDR(E3_q[0], E3_q[1], E3_q[2], E3_q[3], E3_q[4], E3_q[5], E3_q[6]);
K1_q[3] = MEMORY_SEGMENT(, , K1_q[3]_clock_0, , , , , , K1_q[3]_write_address, K1_q[3]_read_address);


--K1_q[4] is divf_rom_sinx:u2|sinx_rom:u2|data_rom_10k:u1|lpm_rom:lpm_rom_component|altrom:srom|q[4] at EC3_C
K1_q[4]_clock_0 = GLOBAL(F1_COUT);
K1_q[4]_write_address = WR_ADDR(E3_q[0], E3_q[1], E3_q[2], E3_q[3], E3_q[4], E3_q[5], E3_q[6]);
K1_q[4]_read_address = RD_ADDR(E3_q[0], E3_q[1], E3_q[2], E3_q[3], E3_q[4], E3_q[5], E3_q[6]);
K1_q[4] = MEMORY_SEGMENT(, , K1_q[4]_clock_0, , , , , , K1_q[4]_write_address, K1_q[4]_read_address);


--K1_q[5] is divf_rom_sinx:u2|sinx_rom:u2|data_rom_10k:u1|lpm_rom:lpm_rom_component|altrom:srom|q[5] at EC5_C
K1_q[5]_clock_0 = GLOBAL(F1_COUT);
K1_q[5]_write_address = WR_ADDR(E3_q[0], E3_q[1], E3_q[2], E3_q[3], E3_q[4], E3_q[5], E3_q[6]);
K1_q[5]_read_address = RD_ADDR(E3_q[0], E3_q[1], E3_q[2], E3_q[3], E3_q[4], E3_q[5], E3_q[6]);
K1_q[5] = MEMORY_SEGMENT(, , K1_q[5]_clock_0, , , , , , K1_q[5]_write_address, K1_q[5]_read_address);


--K1_q[6] is divf_rom_sinx:u2|sinx_rom:u2|data_rom_10k:u1|lpm_rom:lpm_rom_component|altrom:srom|q[6] at EC7_C
K1_q[6]_clock_0 = GLOBAL(F1_COUT);
K1_q[6]_write_address = WR_ADDR(E3_q[0], E3_q[1], E3_q[2], E3_q[3], E3_q[4], E3_q[5], E3_q[6]);
K1_q[6]_read_address = RD_ADDR(E3_q[0], E3_q[1], E3_q[2], E3_q[3], E3_q[4], E3_q[5], E3_q[6]);
K1_q[6] = MEMORY_SEGMENT(, , K1_q[6]_clock_0, , , , , , K1_q[6]_write_address, K1_q[6]_read_address);


--K1_q[7] is divf_rom_sinx:u2|sinx_rom:u2|data_rom_10k:u1|lpm_rom:lpm_rom_component|altrom:srom|q[7] at EC6_C
K1_q[7]_clock_0 = GLOBAL(F1_COUT);
K1_q[7]_write_address = WR_ADDR(E3_q[0], E3_q[1], E3_q[2], E3_q[3], E3_q[4], E3_q[5], E3_q[6]);
K1_q[7]_read_address = RD_ADDR(E3_q[0], E3_q[1], E3_q[2], E3_q[3], E3_q[4], E3_q[5], E3_q[6]);
K1_q[7] = MEMORY_SEGMENT(, , K1_q[7]_clock_0, , , , , , K1_q[7]_write_address, K1_q[7]_read_address);


--E3_q[6] is divf_rom_sinx:u2|sinx_rom:u2|lpm_counter:Q_rtl_0|alt_counter_f10ke:wysi_counter|q[6] at LC7_C14
--operation mode is clrb_cntr

E3_q[6]_lut_out = (E3_q[6] $ E3L31) & G1L4;
E3_q[6] = DFFEA(E3_q[6]_lut_out, GLOBAL(F1_COUT), , , , , );

--E3L92Q is divf_rom_sinx:u2|sinx_rom:u2|lpm_counter:Q_rtl_0|alt_counter_f10ke:wysi_counter|q[6]~0 at LC7_C14
--operation mode is clrb_cntr

E3L92Q = E3_q[6];


--E3_q[5] is divf_rom_sinx:u2|sinx_rom:u2|lpm_counter:Q_rtl_0|alt_counter_f10ke:wysi_counter|q[5] at LC6_C14
--operation mode is clrb_cntr

E3_q[5]_lut_out = (E3_q[5] $ E3L11) & G1L4;
E3_q[5] = DFFEA(E3_q[5]_lut_out, GLOBAL(F1_COUT), , , , , );

--E3L72Q is divf_rom_sinx:u2|sinx_rom:u2|lpm_counter:Q_rtl_0|alt_counter_f10ke:wysi_counter|q[5]~1 at LC6_C14
--operation mode is clrb_cntr

E3L72Q = E3_q[5];

--E3L31 is divf_rom_sinx:u2|sinx_rom:u2|lpm_counter:Q_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[5]~COUT at LC6_C14
--operation mode is clrb_cntr

E3L31 = CARRY(E3_q[5] & (E3L11));


--E3_q[4] is divf_rom_sinx:u2|sinx_rom:u2|lpm_counter:Q_rtl_0|alt_counter_f10ke:wysi_counter|q[4] at LC5_C14
--operation mode is clrb_cntr

E3_q[4]_lut_out = (E3_q[4] $ E3L9) & G1L4;
E3_q[4] = DFFEA(E3_q[4]_lut_out, GLOBAL(F1_COUT), , , , , );

--E3L52Q is divf_rom_sinx:u2|sinx_rom:u2|lpm_counter:Q_rtl_0|alt_counter_f10ke:wysi_counter|q[4]~2 at LC5_C14
--operation mode is clrb_cntr

E3L52Q = E3_q[4];

--E3L11 is divf_rom_sinx:u2|sinx_rom:u2|lpm_counter:Q_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[4]~COUT at LC5_C14
--operation mode is clrb_cntr

E3L11 = CARRY(E3_q[4] & (E3L9));


--E3_q[3] is divf_rom_sinx:u2|sinx_rom:u2|lpm_counter:Q_rtl_0|alt_counter_f10ke:wysi_counter|q[3] at LC4_C14
--operation mode is clrb_cntr

E3_q[3]_lut_out = (E3_q[3] $ E3L7) & G1L4;
E3_q[3] = DFFEA(E3_q[3]_lut_out, GLOBAL(F1_COUT), , , , , );

--E3L32Q is divf_rom_sinx:u2|sinx_rom:u2|lpm_counter:Q_rtl_0|alt_counter_f10ke:wysi_counter|q[3]~3 at LC4_C14
--operation mode is clrb_cntr

E3L32Q = E3_q[3];

--E3L9 is divf_rom_sinx:u2|sinx_rom:u2|lpm_counter:Q_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[3]~COUT at LC4_C14
--operation mode is clrb_cntr

E3L9 = CARRY(E3_q[3] & (E3L7));


--G1L3 is divf_rom_sinx:u2|sinx_rom:u2|LessThan~63 at LC1_C13
--operation mode is normal

G1L3 = !E3_q[3] # !E3_q[4] # !E3_q[5] # !E3_q[6];

--G1L5 is divf_rom_sinx:u2|sinx_rom:u2|LessThan~66 at LC1_C13
--operation mode is normal

G1L5 = !E3_q[3] # !E3_q[4] # !E3_q[5] # !E3_q[6];


--E3_q[2] is divf_rom_sinx:u2|sinx_rom:u2|lpm_counter:Q_rtl_0|alt_counter_f10ke:wysi_counter|q[2] at LC3_C14
--operation mode is clrb_cntr

E3_q[2]_lut_out = (E3_q[2] $ E3L5) & G1L4;
E3_q[2] = DFFEA(E3_q[2]_lut_out, GLOBAL(F1_COUT), , , , , );

--E3L12Q is divf_rom_sinx:u2|sinx_rom:u2|lpm_counter:Q_rtl_0|alt_counter_f10ke:wysi_counter|q[2]~4 at LC3_C14
--operation mode is clrb_cntr

E3L12Q = E3_q[2];

--E3L7 is divf_rom_sinx:u2|sinx_rom:u2|lpm_counter:Q_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[2]~COUT at LC3_C14
--operation mode is clrb_cntr

E3L7 = CARRY(E3_q[2] & (E3L5));


--E3_q[1] is divf_rom_sinx:u2|sinx_rom:u2|lpm_counter:Q_rtl_0|alt_counter_f10ke:wysi_counter|q[1] at LC2_C14
--operation mode is clrb_cntr

E3_q[1]_lut_out = (E3_q[1] $ E3L3) & G1L4;
E3_q[1] = DFFEA(E3_q[1]_lut_out, GLOBAL(F1_COUT), , , , , );

--E3L91Q is divf_rom_sinx:u2|sinx_rom:u2|lpm_counter:Q_rtl_0|alt_counter_f10ke:wysi_counter|q[1]~5 at LC2_C14
--operation mode is clrb_cntr

E3L91Q = E3_q[1];

--E3L5 is divf_rom_sinx:u2|sinx_rom:u2|lpm_counter:Q_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[1]~COUT at LC2_C14
--operation mode is clrb_cntr

E3L5 = CARRY(E3_q[1] & (E3L3));


--E3_q[0] is divf_rom_sinx:u2|sinx_rom:u2|lpm_counter:Q_rtl_0|alt_counter_f10ke:wysi_counter|q[0] at LC1_C14
--operation mode is clrb_cntr

E3_q[0]_lut_out = (!E3_q[0]) & G1L4;
E3_q[0] = DFFEA(E3_q[0]_lut_out, GLOBAL(F1_COUT), , , , , );

--E3L71Q is divf_rom_sinx:u2|sinx_rom:u2|lpm_counter:Q_rtl_0|alt_counter_f10ke:wysi_counter|q[0]~6 at LC1_C14
--operation mode is clrb_cntr

E3L71Q = E3_q[0];

--E3L3 is divf_rom_sinx:u2|sinx_rom:u2|lpm_counter:Q_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[0]~COUT at LC1_C14
--operation mode is clrb_cntr

E3L3 = CARRY(E3_q[0]);


--G1L4 is divf_rom_sinx:u2|sinx_rom:u2|LessThan~64 at LC8_C14
--operation mode is normal

G1L4 = G1L3 # !E3_q[0] # !E3_q[1] # !E3_q[2];

--G1L6 is divf_rom_sinx:u2|sinx_rom:u2|LessThan~67 at LC8_C14
--operation mode is normal

G1L6 = G1L3 # !E3_q[0] # !E3_q[1] # !E3_q[2];