divf_rom_sinx.vwf

来自「在EDA开发软件QuartusII上利用VHDL语言实现DDS信号发生器」· VWF 代码 · 共 1,267 行 · 第 1/2 页

VWF
1,267 行
字号
12
/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/

/*
Copyright (C) 1991-2005 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic       
functions, and any output files any of the foregoing           
(including device programming or simulation files), and any    
associated documentation or information are expressly subject  
to the terms and conditions of the Altera Program License      
Subscription Agreement, Altera MegaCore Function License       
Agreement, or other applicable license agreement, including,   
without limitation, that your use is for the sole purpose of   
programming logic devices manufactured by Altera and sold by   
Altera or its authorized distributors.  Please refer to the    
applicable agreement for further details.
*/

HEADER
{
	VERSION = 1;
	TIME_UNIT = ns;
	SIMULATION_TIME = 200000.0;
	GRID_PHASE = 0.0;
	GRID_PERIOD = 10.0;
	GRID_DUTY_CYCLE = 50;
}

SIGNAL("clkin")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = INPUT;
	PARENT = "";
}

SIGNAL("Dadata")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = BUS;
	WIDTH = 8;
	LSB_INDEX = 0;
	DIRECTION = OUTPUT;
	PARENT = "";
}

SIGNAL("Dadata[7]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = OUTPUT;
	PARENT = "Dadata";
}

SIGNAL("Dadata[6]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = OUTPUT;
	PARENT = "Dadata";
}

SIGNAL("Dadata[5]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = OUTPUT;
	PARENT = "Dadata";
}

SIGNAL("Dadata[4]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = OUTPUT;
	PARENT = "Dadata";
}

SIGNAL("Dadata[3]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = OUTPUT;
	PARENT = "Dadata";
}

SIGNAL("Dadata[2]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = OUTPUT;
	PARENT = "Dadata";
}

SIGNAL("Dadata[1]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = OUTPUT;
	PARENT = "Dadata";
}

SIGNAL("Dadata[0]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = OUTPUT;
	PARENT = "Dadata";
}

SIGNAL("datain")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = BUS;
	WIDTH = 4;
	LSB_INDEX = 0;
	DIRECTION = INPUT;
	PARENT = "";
}

SIGNAL("datain[3]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = INPUT;
	PARENT = "datain";
}

SIGNAL("datain[2]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = INPUT;
	PARENT = "datain";
}

SIGNAL("datain[1]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = INPUT;
	PARENT = "datain";
}

SIGNAL("datain[0]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = INPUT;
	PARENT = "datain";
}

SIGNAL("f")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = OUTPUT;
	PARENT = "";
}

TRANSITION_LIST("clkin")
{
	NODE
	{
		REPEAT = 1;
		NODE
		{
			REPEAT = 4000;
			LEVEL 0 FOR 25.0;
			LEVEL 1 FOR 25.0;
		}
	}
}

TRANSITION_LIST("Dadata[7]")
{
	NODE
	{
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		LEVEL 1 FOR 26407.3;
		LEVEL 0 FOR 51200.0;
		LEVEL 1 FOR 51200.0;
		LEVEL 0 FOR 51200.0;
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	}
}

TRANSITION_LIST("Dadata[6]")
{
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		LEVEL 0 FOR 33600.0;
		LEVEL 1 FOR 8800.0;
		LEVEL 0 FOR 8000.0;
		LEVEL 1 FOR 11991.8;
	}
}

TRANSITION_LIST("Dadata[5]")
{
	NODE
	{
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		LEVEL 1 FOR 4000.0;
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		LEVEL 0 FOR 5600.0;
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		LEVEL 1 FOR 4000.0;
		LEVEL 0 FOR 4000.0;
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		LEVEL 0 FOR 4800.0;
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		LEVEL 0 FOR 24000.0;
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		LEVEL 0 FOR 4800.0;
		LEVEL 1 FOR 4000.0;
		LEVEL 0 FOR 4000.0;
		LEVEL 1 FOR 4000.0;
		LEVEL 0 FOR 5600.0;
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	}
}

TRANSITION_LIST("Dadata[4]")
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	NODE
	{
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		NODE
		{
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			LEVEL 1 FOR 2400.0;
			LEVEL 0 FOR 1600.0;
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		NODE
		{
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			LEVEL 1 FOR 2400.0;
			LEVEL 0 FOR 2400.0;
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		LEVEL 1 FOR 4000.0;
		LEVEL 0 FOR 16000.0;
		LEVEL 1 FOR 4000.0;
		NODE
		{
			REPEAT = 2;
			LEVEL 0 FOR 2400.0;
			LEVEL 1 FOR 2400.0;
		}
		NODE
		{
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			LEVEL 0 FOR 1600.0;
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		}
		LEVEL 0 FOR 2400.0;
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		LEVEL 0 FOR 2400.0;
		LEVEL 1 FOR 1600.0;
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		NODE
		{
			REPEAT = 2;
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		NODE
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		NODE
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		LEVEL 0 FOR 2400.0;
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		LEVEL 0 FOR 2400.0;
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		LEVEL 0 FOR 3200.0;
		LEVEL 1 FOR 3192.7;
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}

TRANSITION_LIST("Dadata[3]")
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			LEVEL 1 FOR 800.0;
			LEVEL 0 FOR 1600.0;
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			LEVEL 1 FOR 1600.0;
			LEVEL 0 FOR 800.0;
		}
		LEVEL 1 FOR 800.0;
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		LEVEL 1 FOR 1600.0;
		LEVEL 0 FOR 800.0;
		NODE
		{
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			LEVEL 1 FOR 800.0;
			LEVEL 0 FOR 1600.0;
		}
		LEVEL 1 FOR 1600.0;
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		LEVEL 1 FOR 2400.0;
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		LEVEL 1 FOR 1600.0;
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}

TRANSITION_LIST("Dadata[2]")
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		NODE
		{
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		LEVEL 1 FOR 1600.0;
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		NODE
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		LEVEL 1 FOR 800.0;
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		NODE
		{
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		NODE
		{
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			LEVEL 1 FOR 1600.0;
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		LEVEL 1 FOR 800.0;
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		NODE
		{
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12

divf_rom_sinx.vwf - 源码说明

本页面展示了「在EDA开发软件QuartusII上利用VHDL语言实现DDS信号发生器」中的 divf_rom_sinx.vwf 源码文件，采用 VWF 编程语言编写，共 1,267 行代码。您可以在线阅读完整代码内容，也可以返回资源详情页下载完整源码包进行本地学习和开发。

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