sinx_rom.map.eqn

来自「在EDA开发软件QuartusII上利用VHDL语言实现DDS信号发生器」· EQN 代码 · 共 278 行

-- Copyright (C) 1991-2005 Altera Corporation
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--A1L4Q is cout~reg0
--operation mode is normal

A1L4Q_lut_out = !A1L41 & D1_q[2] & D1_q[1] & D1_q[0];
A1L4Q = DFFEA(A1L4Q_lut_out, CLK, , , , , );

--A1L3Q is cout~0
--operation mode is normal

A1L3Q = A1L4Q;


--F1_q[0] is data_rom_10k:u1|lpm_rom:lpm_rom_component|altrom:srom|q[0]
F1_q[0]_clock_0 = CLK;
F1_q[0]_write_address = WR_ADDR(D1_q[0], D1_q[1], D1_q[2], D1_q[3], D1_q[4], D1_q[5], D1_q[6]);
F1_q[0]_read_address = RD_ADDR(D1_q[0], D1_q[1], D1_q[2], D1_q[3], D1_q[4], D1_q[5], D1_q[6]);
F1_q[0] = MEMORY_SEGMENT(, , F1_q[0]_clock_0, , , , , , F1_q[0]_write_address, F1_q[0]_read_address);


--F1_q[1] is data_rom_10k:u1|lpm_rom:lpm_rom_component|altrom:srom|q[1]
F1_q[1]_clock_0 = CLK;
F1_q[1]_write_address = WR_ADDR(D1_q[0], D1_q[1], D1_q[2], D1_q[3], D1_q[4], D1_q[5], D1_q[6]);
F1_q[1]_read_address = RD_ADDR(D1_q[0], D1_q[1], D1_q[2], D1_q[3], D1_q[4], D1_q[5], D1_q[6]);
F1_q[1] = MEMORY_SEGMENT(, , F1_q[1]_clock_0, , , , , , F1_q[1]_write_address, F1_q[1]_read_address);


--F1_q[2] is data_rom_10k:u1|lpm_rom:lpm_rom_component|altrom:srom|q[2]
F1_q[2]_clock_0 = CLK;
F1_q[2]_write_address = WR_ADDR(D1_q[0], D1_q[1], D1_q[2], D1_q[3], D1_q[4], D1_q[5], D1_q[6]);
F1_q[2]_read_address = RD_ADDR(D1_q[0], D1_q[1], D1_q[2], D1_q[3], D1_q[4], D1_q[5], D1_q[6]);
F1_q[2] = MEMORY_SEGMENT(, , F1_q[2]_clock_0, , , , , , F1_q[2]_write_address, F1_q[2]_read_address);


--F1_q[3] is data_rom_10k:u1|lpm_rom:lpm_rom_component|altrom:srom|q[3]
F1_q[3]_clock_0 = CLK;
F1_q[3]_write_address = WR_ADDR(D1_q[0], D1_q[1], D1_q[2], D1_q[3], D1_q[4], D1_q[5], D1_q[6]);
F1_q[3]_read_address = RD_ADDR(D1_q[0], D1_q[1], D1_q[2], D1_q[3], D1_q[4], D1_q[5], D1_q[6]);
F1_q[3] = MEMORY_SEGMENT(, , F1_q[3]_clock_0, , , , , , F1_q[3]_write_address, F1_q[3]_read_address);


--F1_q[4] is data_rom_10k:u1|lpm_rom:lpm_rom_component|altrom:srom|q[4]
F1_q[4]_clock_0 = CLK;
F1_q[4]_write_address = WR_ADDR(D1_q[0], D1_q[1], D1_q[2], D1_q[3], D1_q[4], D1_q[5], D1_q[6]);
F1_q[4]_read_address = RD_ADDR(D1_q[0], D1_q[1], D1_q[2], D1_q[3], D1_q[4], D1_q[5], D1_q[6]);
F1_q[4] = MEMORY_SEGMENT(, , F1_q[4]_clock_0, , , , , , F1_q[4]_write_address, F1_q[4]_read_address);


--F1_q[5] is data_rom_10k:u1|lpm_rom:lpm_rom_component|altrom:srom|q[5]
F1_q[5]_clock_0 = CLK;
F1_q[5]_write_address = WR_ADDR(D1_q[0], D1_q[1], D1_q[2], D1_q[3], D1_q[4], D1_q[5], D1_q[6]);
F1_q[5]_read_address = RD_ADDR(D1_q[0], D1_q[1], D1_q[2], D1_q[3], D1_q[4], D1_q[5], D1_q[6]);
F1_q[5] = MEMORY_SEGMENT(, , F1_q[5]_clock_0, , , , , , F1_q[5]_write_address, F1_q[5]_read_address);


--F1_q[6] is data_rom_10k:u1|lpm_rom:lpm_rom_component|altrom:srom|q[6]
F1_q[6]_clock_0 = CLK;
F1_q[6]_write_address = WR_ADDR(D1_q[0], D1_q[1], D1_q[2], D1_q[3], D1_q[4], D1_q[5], D1_q[6]);
F1_q[6]_read_address = RD_ADDR(D1_q[0], D1_q[1], D1_q[2], D1_q[3], D1_q[4], D1_q[5], D1_q[6]);
F1_q[6] = MEMORY_SEGMENT(, , F1_q[6]_clock_0, , , , , , F1_q[6]_write_address, F1_q[6]_read_address);


--F1_q[7] is data_rom_10k:u1|lpm_rom:lpm_rom_component|altrom:srom|q[7]
F1_q[7]_clock_0 = CLK;
F1_q[7]_write_address = WR_ADDR(D1_q[0], D1_q[1], D1_q[2], D1_q[3], D1_q[4], D1_q[5], D1_q[6]);
F1_q[7]_read_address = RD_ADDR(D1_q[0], D1_q[1], D1_q[2], D1_q[3], D1_q[4], D1_q[5], D1_q[6]);
F1_q[7] = MEMORY_SEGMENT(, , F1_q[7]_clock_0, , , , , , F1_q[7]_write_address, F1_q[7]_read_address);


--D1_q[6] is lpm_counter:Q_rtl_0|alt_counter_f10ke:wysi_counter|q[6]
--operation mode is clrb_cntr

D1_q[6]_lut_out = (D1_q[6] $ D1L31) & A1L51;
D1_q[6] = DFFEA(D1_q[6]_lut_out, CLK, , , , , );

--D1L92Q is lpm_counter:Q_rtl_0|alt_counter_f10ke:wysi_counter|q[6]~0
--operation mode is clrb_cntr

D1L92Q = D1_q[6];


--D1_q[5] is lpm_counter:Q_rtl_0|alt_counter_f10ke:wysi_counter|q[5]
--operation mode is clrb_cntr

D1_q[5]_lut_out = (D1_q[5] $ D1L11) & A1L51;
D1_q[5] = DFFEA(D1_q[5]_lut_out, CLK, , , , , );

--D1L72Q is lpm_counter:Q_rtl_0|alt_counter_f10ke:wysi_counter|q[5]~1
--operation mode is clrb_cntr

D1L72Q = D1_q[5];

--D1L31 is lpm_counter:Q_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[5]~COUT
--operation mode is clrb_cntr

D1L31 = CARRY(D1_q[5] & (D1L11));


--D1_q[4] is lpm_counter:Q_rtl_0|alt_counter_f10ke:wysi_counter|q[4]
--operation mode is clrb_cntr

D1_q[4]_lut_out = (D1_q[4] $ D1L9) & A1L51;
D1_q[4] = DFFEA(D1_q[4]_lut_out, CLK, , , , , );

--D1L52Q is lpm_counter:Q_rtl_0|alt_counter_f10ke:wysi_counter|q[4]~2
--operation mode is clrb_cntr

D1L52Q = D1_q[4];

--D1L11 is lpm_counter:Q_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[4]~COUT
--operation mode is clrb_cntr

D1L11 = CARRY(D1_q[4] & (D1L9));


--D1_q[3] is lpm_counter:Q_rtl_0|alt_counter_f10ke:wysi_counter|q[3]
--operation mode is clrb_cntr

D1_q[3]_lut_out = (D1_q[3] $ D1L7) & A1L51;
D1_q[3] = DFFEA(D1_q[3]_lut_out, CLK, , , , , );

--D1L32Q is lpm_counter:Q_rtl_0|alt_counter_f10ke:wysi_counter|q[3]~3
--operation mode is clrb_cntr

D1L32Q = D1_q[3];

--D1L9 is lpm_counter:Q_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[3]~COUT
--operation mode is clrb_cntr

D1L9 = CARRY(D1_q[3] & (D1L7));


--A1L41 is LessThan~63
--operation mode is normal

A1L41 = !D1_q[3] # !D1_q[4] # !D1_q[5] # !D1_q[6];

--A1L61 is LessThan~66
--operation mode is normal

A1L61 = !D1_q[3] # !D1_q[4] # !D1_q[5] # !D1_q[6];


--D1_q[2] is lpm_counter:Q_rtl_0|alt_counter_f10ke:wysi_counter|q[2]
--operation mode is clrb_cntr

D1_q[2]_lut_out = (D1_q[2] $ D1L5) & A1L51;
D1_q[2] = DFFEA(D1_q[2]_lut_out, CLK, , , , , );

--D1L12Q is lpm_counter:Q_rtl_0|alt_counter_f10ke:wysi_counter|q[2]~4
--operation mode is clrb_cntr

D1L12Q = D1_q[2];

--D1L7 is lpm_counter:Q_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[2]~COUT
--operation mode is clrb_cntr

D1L7 = CARRY(D1_q[2] & (D1L5));


--D1_q[1] is lpm_counter:Q_rtl_0|alt_counter_f10ke:wysi_counter|q[1]
--operation mode is clrb_cntr

D1_q[1]_lut_out = (D1_q[1] $ D1L3) & A1L51;
D1_q[1] = DFFEA(D1_q[1]_lut_out, CLK, , , , , );

--D1L91Q is lpm_counter:Q_rtl_0|alt_counter_f10ke:wysi_counter|q[1]~5
--operation mode is clrb_cntr

D1L91Q = D1_q[1];

--D1L5 is lpm_counter:Q_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[1]~COUT
--operation mode is clrb_cntr

D1L5 = CARRY(D1_q[1] & (D1L3));


--D1_q[0] is lpm_counter:Q_rtl_0|alt_counter_f10ke:wysi_counter|q[0]
--operation mode is clrb_cntr

D1_q[0]_lut_out = (!D1_q[0]) & A1L51;
D1_q[0] = DFFEA(D1_q[0]_lut_out, CLK, , , , , );

--D1L71Q is lpm_counter:Q_rtl_0|alt_counter_f10ke:wysi_counter|q[0]~6
--operation mode is clrb_cntr

D1L71Q = D1_q[0];

--D1L3 is lpm_counter:Q_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[0]~COUT
--operation mode is clrb_cntr

D1L3 = CARRY(D1_q[0]);


--A1L51 is LessThan~64
--operation mode is normal

A1L51 = A1L41 # !D1_q[0] # !D1_q[1] # !D1_q[2];

--A1L71 is LessThan~67
--operation mode is normal

A1L71 = A1L41 # !D1_q[0] # !D1_q[1] # !D1_q[2];


--CLK is CLK
--operation mode is input

CLK = INPUT();


--cout is cout
--operation mode is output

cout = OUTPUT(A1L4Q);


--DOUT[0] is DOUT[0]
--operation mode is output

DOUT[0] = OUTPUT(F1_q[0]);


--DOUT[1] is DOUT[1]
--operation mode is output

DOUT[1] = OUTPUT(F1_q[1]);


--DOUT[2] is DOUT[2]
--operation mode is output

DOUT[2] = OUTPUT(F1_q[2]);


--DOUT[3] is DOUT[3]
--operation mode is output

DOUT[3] = OUTPUT(F1_q[3]);


--DOUT[4] is DOUT[4]
--operation mode is output

DOUT[4] = OUTPUT(F1_q[4]);


--DOUT[5] is DOUT[5]
--operation mode is output

DOUT[5] = OUTPUT(F1_q[5]);


--DOUT[6] is DOUT[6]
--operation mode is output

DOUT[6] = OUTPUT(F1_q[6]);


--DOUT[7] is DOUT[7]
--operation mode is output

DOUT[7] = OUTPUT(F1_q[7]);