sinx_rom.vhd

来自「在EDA开发软件QuartusII上利用VHDL语言实现DDS信号发生器」· VHDL 代码 · 共 29 行

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITY sinx_rom IS
    PORT ( CLK: IN STD_LOGIC;
           cout: out std_logic;
           DOUT: OUT STD_LOGIC_VECTOR(7 DOWNTO 0) );
END;

ARCHITECTURE behav OF sinx_rom IS

COMPONENT data_rom_10k
    PORT ( address: IN STD_LOGIC_VECTOR(6 DOWNTO 0);
           inclock: IN STD_LOGIC;
            q: out STD_LOGIC_VECTOR(7 DOWNTO 0) );
END COMPONENT;

    SIGNAL Q: STD_LOGIC_VECTOR(6 DOWNTO 0);
BEGIN
PROCESS(CLK)
BEGIN
    IF CLK'EVENT AND CLK='1' THEN if Q<127 then Q<=Q+1;cout<='0';
      else Q<="0000000";cout<='1';
      end if;
    END IF;
END PROCESS;
u1:data_rom_10k PORT MAP(address=>Q,q=>DOUT,inclock=>CLK);
END;