sf_df_rom_sinx.vhd

来自「在EDA开发软件QuartusII上利用VHDL语言实现DDS信号发生器」· VHDL 代码 · 共 29 行

library ieee;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITY sf_df_rom_sinx IS
    PORT ( clkk,en: IN STD_LOGIC;           
            ff: out std_logic;           -- 频率显示出口            
           Da_data: OUT STD_LOGIC_VECTOR(7 DOWNTO 0) );-- DA数据
END;

ARCHITECTURE behav OF sf_df_rom_sinx IS

component SCANCNT4B
    port(  CLK: IN  STD_LOGIC;
           EN: IN STD_LOGIC;
           FOUT: OUT STD_LOGIC_VECTOR(3 DOWNTO 0)  );
end component;

COMPONENT divf_rom_sinx
    PORT ( clkin: IN STD_LOGIC;
           datain:in std_logic_vector(3 downto 0); -- 初值
            f: out std_logic;           -- 频率显示出口
           Dadata: OUT STD_LOGIC_VECTOR(7 DOWNTO 0) );-- DA数据
END COMPONENT;
SIGNAL vari: STD_LOGIC_VECTOR(3 DOWNTO 0);
BEGIN
u1:SCANCNT4B PORT MAP( clk=>clkK,EN=>en,FOUT=>vari );
u2:divf_rom_sinx port map( clkin=>clkk,datain=>vari,f=>ff,dadata=>da_data );
END;