sf_df_rom_sinx.tan.rpt

来自「在EDA开发软件QuartusII上利用VHDL语言实现DDS信号发生器」· RPT 代码 · 共 265 行 · 第 1/5 页

; Timing Analyzer Settings                                                                             ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Option                                                ; Setting            ; From ; To ; Entity Name ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Device Name                                           ; EPF10K10LC84-4     ;      ;    ;             ;
; Timing Models                                         ; Final              ;      ;    ;             ;
; Number of source nodes to report per destination node ; 10                 ;      ;    ;             ;
; Number of destination nodes to report                 ; 10                 ;      ;    ;             ;
; Number of paths to report                             ; 200                ;      ;    ;             ;
; Report Minimum Timing Checks                          ; Off                ;      ;    ;             ;
; Use Fast Timing Models                                ; Off                ;      ;    ;             ;
; Report IO Paths Separately                            ; Off                ;      ;    ;             ;
; Default hold multicycle                               ; Same as Multicycle ;      ;    ;             ;
; Cut paths between unrelated clock domains             ; On                 ;      ;    ;             ;
; Cut off read during write signal paths                ; On                 ;      ;    ;             ;
; Cut off feedback from I/O pins                        ; On                 ;      ;    ;             ;
; Report Combined Fast/Slow Timing                      ; Off                ;      ;    ;             ;
; Ignore Clock Settings                                 ; Off                ;      ;    ;             ;
; Analyze latches as synchronous elements               ; Off                ;      ;    ;             ;
; Enable Recovery/Removal analysis                      ; Off                ;      ;    ;             ;
; Enable Clock Latency                                  ; Off                ;      ;    ;             ;
+-------------------------------------------------------+--------------------+------+----+-------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary                                                                                                                                                             ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; Clock Node Name ; Clock Setting Name ; Type     ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ; Phase offset ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; clkk            ;                    ; User Pin ; NONE             ; 0.000 ns      ; 0.000 ns     ; NONE     ; N/A                   ; N/A                 ; N/A    ;              ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'clkk'                                                                                                                                                                                                                                                                                                                                         ;
+-------+------------------------------------------------+--------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; Slack ; Actual fmax (period)                           ; From                                                                                 ; To                                                                                              ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-------+------------------------------------------------+--------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; N/A   ; 69.44 MHz ( period = 14.400 ns )               ; divf_rom_sinx:u2|sinx_rom:u2|lpm_counter:Q_rtl_0|alt_counter_f10ke:wysi_counter|q[3] ; divf_rom_sinx:u2|sinx_rom:u2|lpm_counter:Q_rtl_0|alt_counter_f10ke:wysi_counter|q[6]            ; clkk       ; clkk     ; None                        ; None                      ; 10.800 ns               ;
; N/A   ; 69.44 MHz ( period = 14.400 ns )               ; divf_rom_sinx:u2|sinx_rom:u2|lpm_counter:Q_rtl_0|alt_counter_f10ke:wysi_counter|q[4] ; divf_rom_sinx:u2|sinx_rom:u2|lpm_counter:Q_rtl_0|alt_counter_f10ke:wysi_counter|q[6]            ; clkk       ; clkk     ; None                        ; None                      ; 10.800 ns               ;
; N/A   ; 69.44 MHz ( period = 14.400 ns )               ; divf_rom_sinx:u2|sinx_rom:u2|lpm_counter:Q_rtl_0|alt_counter_f10ke:wysi_counter|q[5] ; divf_rom_sinx:u2|sinx_rom:u2|lpm_counter:Q_rtl_0|alt_counter_f10ke:wysi_counter|q[6]            ; clkk       ; clkk     ; None                        ; None                      ; 10.800 ns               ;
; N/A   ; 69.44 MHz ( period = 14.400 ns )               ; divf_rom_sinx:u2|sinx_rom:u2|lpm_counter:Q_rtl_0|alt_counter_f10ke:wysi_counter|q[3] ; divf_rom_sinx:u2|sinx_rom:u2|lpm_counter:Q_rtl_0|alt_counter_f10ke:wysi_counter|q[5]            ; clkk       ; clkk     ; None                        ; None                      ; 10.800 ns               ;
; N/A   ; 69.44 MHz ( period = 14.400 ns )               ; divf_rom_sinx:u2|sinx_rom:u2|lpm_counter:Q_rtl_0|alt_counter_f10ke:wysi_counter|q[4] ; divf_rom_sinx:u2|sinx_rom:u2|lpm_counter:Q_rtl_0|alt_counter_f10ke:wysi_counter|q[5]            ; clkk       ; clkk     ; None                        ; None                      ; 10.800 ns               ;
; N/A   ; 69.44 MHz ( period = 14.400 ns )               ; divf_rom_sinx:u2|sinx_rom:u2|lpm_counter:Q_rtl_0|alt_counter_f10ke:wysi_counter|q[5] ; divf_rom_sinx:u2|sinx_rom:u2|lpm_counter:Q_rtl_0|alt_counter_f10ke:wysi_counter|q[5]            ; clkk       ; clkk     ; None                        ; None                      ; 10.800 ns               ;
; N/A   ; 69.44 MHz ( period = 14.400 ns )               ; divf_rom_sinx:u2|sinx_rom:u2|lpm_counter:Q_rtl_0|alt_counter_f10ke:wysi_counter|q[3] ; divf_rom_sinx:u2|sinx_rom:u2|lpm_counter:Q_rtl_0|alt_counter_f10ke:wysi_counter|q[4]            ; clkk       ; clkk     ; None                        ; None                      ; 10.800 ns               ;
; N/A   ; 69.44 MHz ( period = 14.400 ns )               ; divf_rom_sinx:u2|sinx_rom:u2|lpm_counter:Q_rtl_0|alt_counter_f10ke:wysi_counter|q[4] ; divf_rom_sinx:u2|sinx_rom:u2|lpm_counter:Q_rtl_0|alt_counter_f10ke:wysi_counter|q[4]            ; clkk       ; clkk     ; None                        ; None                      ; 10.800 ns               ;
; N/A   ; 69.44 MHz ( period = 14.400 ns )               ; divf_rom_sinx:u2|sinx_rom:u2|lpm_counter:Q_rtl_0|alt_counter_f10ke:wysi_counter|q[5] ; divf_rom_sinx:u2|sinx_rom:u2|lpm_counter:Q_rtl_0|alt_counter_f10ke:wysi_counter|q[4]            ; clkk       ; clkk     ; None                        ; None                      ; 10.800 ns               ;
; N/A   ; 69.44 MHz ( period = 14.400 ns )               ; divf_rom_sinx:u2|sinx_rom:u2|lpm_counter:Q_rtl_0|alt_counter_f10ke:wysi_counter|q[3] ; divf_rom_sinx:u2|sinx_rom:u2|lpm_counter:Q_rtl_0|alt_counter_f10ke:wysi_counter|q[3]            ; clkk       ; clkk     ; None                        ; None                      ; 10.800 ns               ;
; N/A   ; 69.44 MHz ( period = 14.400 ns )               ; divf_rom_sinx:u2|sinx_rom:u2|lpm_counter:Q_rtl_0|alt_counter_f10ke:wysi_counter|q[4] ; divf_rom_sinx:u2|sinx_rom:u2|lpm_counter:Q_rtl_0|alt_counter_f10ke:wysi_counter|q[3]            ; clkk       ; clkk     ; None                        ; None                      ; 10.800 ns               ;
; N/A   ; 69.44 MHz ( period = 14.400 ns )               ; divf_rom_sinx:u2|sinx_rom:u2|lpm_counter:Q_rtl_0|alt_counter_f10ke:wysi_counter|q[5] ; divf_rom_sinx:u2|sinx_rom:u2|lpm_counter:Q_rtl_0|alt_counter_f10ke:wysi_counter|q[3]            ; clkk       ; clkk     ; None                        ; None                      ; 10.800 ns               ;
; N/A   ; 69.44 MHz ( period = 14.400 ns )               ; divf_rom_sinx:u2|sinx_rom:u2|lpm_counter:Q_rtl_0|alt_counter_f10ke:wysi_counter|q[3] ; divf_rom_sinx:u2|sinx_rom:u2|lpm_counter:Q_rtl_0|alt_counter_f10ke:wysi_counter|q[0]            ; clkk       ; clkk     ; None                        ; None                      ; 10.800 ns               ;
; N/A   ; 69.44 MHz ( period = 14.400 ns )               ; divf_rom_sinx:u2|sinx_rom:u2|lpm_counter:Q_rtl_0|alt_counter_f10ke:wysi_counter|q[4] ; divf_rom_sinx:u2|sinx_rom:u2|lpm_counter:Q_rtl_0|alt_counter_f10ke:wysi_counter|q[0]            ; clkk       ; clkk     ; None                        ; None                      ; 10.800 ns               ;
; N/A   ; 69.44 MHz ( period = 14.400 ns )               ; divf_rom_sinx:u2|sinx_rom:u2|lpm_counter:Q_rtl_0|alt_counter_f10ke:wysi_counter|q[5] ; divf_rom_sinx:u2|sinx_rom:u2|lpm_counter:Q_rtl_0|alt_counter_f10ke:wysi_counter|q[0]            ; clkk       ; clkk     ; None                        ; None                      ; 10.800 ns               ;