sinx_rom.tan.rpt

来自「在EDA开发软件QuartusII上利用VHDL语言实现DDS信号发生器」· RPT 代码 · 共 320 行 · 第 1/4 页

; N/A   ; None         ; 26.600 ns  ; data_rom_10k:u1|lpm_rom:lpm_rom_component|altrom:srom|q[4]~reg_ra5 ; DOUT[4] ; CLK        ;
; N/A   ; None         ; 26.600 ns  ; data_rom_10k:u1|lpm_rom:lpm_rom_component|altrom:srom|q[4]~reg_ra6 ; DOUT[4] ; CLK        ;
; N/A   ; None         ; 26.600 ns  ; data_rom_10k:u1|lpm_rom:lpm_rom_component|altrom:srom|q[3]~reg_ra0 ; DOUT[3] ; CLK        ;
; N/A   ; None         ; 26.600 ns  ; data_rom_10k:u1|lpm_rom:lpm_rom_component|altrom:srom|q[3]~reg_ra1 ; DOUT[3] ; CLK        ;
; N/A   ; None         ; 26.600 ns  ; data_rom_10k:u1|lpm_rom:lpm_rom_component|altrom:srom|q[3]~reg_ra2 ; DOUT[3] ; CLK        ;
; N/A   ; None         ; 26.600 ns  ; data_rom_10k:u1|lpm_rom:lpm_rom_component|altrom:srom|q[3]~reg_ra3 ; DOUT[3] ; CLK        ;
; N/A   ; None         ; 26.600 ns  ; data_rom_10k:u1|lpm_rom:lpm_rom_component|altrom:srom|q[3]~reg_ra4 ; DOUT[3] ; CLK        ;
; N/A   ; None         ; 26.600 ns  ; data_rom_10k:u1|lpm_rom:lpm_rom_component|altrom:srom|q[3]~reg_ra5 ; DOUT[3] ; CLK        ;
; N/A   ; None         ; 26.600 ns  ; data_rom_10k:u1|lpm_rom:lpm_rom_component|altrom:srom|q[3]~reg_ra6 ; DOUT[3] ; CLK        ;
; N/A   ; None         ; 26.600 ns  ; data_rom_10k:u1|lpm_rom:lpm_rom_component|altrom:srom|q[1]~reg_ra0 ; DOUT[1] ; CLK        ;
; N/A   ; None         ; 26.600 ns  ; data_rom_10k:u1|lpm_rom:lpm_rom_component|altrom:srom|q[1]~reg_ra1 ; DOUT[1] ; CLK        ;
; N/A   ; None         ; 26.600 ns  ; data_rom_10k:u1|lpm_rom:lpm_rom_component|altrom:srom|q[1]~reg_ra2 ; DOUT[1] ; CLK        ;
; N/A   ; None         ; 26.600 ns  ; data_rom_10k:u1|lpm_rom:lpm_rom_component|altrom:srom|q[1]~reg_ra3 ; DOUT[1] ; CLK        ;
; N/A   ; None         ; 26.600 ns  ; data_rom_10k:u1|lpm_rom:lpm_rom_component|altrom:srom|q[1]~reg_ra4 ; DOUT[1] ; CLK        ;
; N/A   ; None         ; 26.600 ns  ; data_rom_10k:u1|lpm_rom:lpm_rom_component|altrom:srom|q[1]~reg_ra5 ; DOUT[1] ; CLK        ;
; N/A   ; None         ; 26.600 ns  ; data_rom_10k:u1|lpm_rom:lpm_rom_component|altrom:srom|q[1]~reg_ra6 ; DOUT[1] ; CLK        ;
; N/A   ; None         ; 26.600 ns  ; data_rom_10k:u1|lpm_rom:lpm_rom_component|altrom:srom|q[0]~reg_ra0 ; DOUT[0] ; CLK        ;
; N/A   ; None         ; 26.600 ns  ; data_rom_10k:u1|lpm_rom:lpm_rom_component|altrom:srom|q[0]~reg_ra1 ; DOUT[0] ; CLK        ;
; N/A   ; None         ; 26.600 ns  ; data_rom_10k:u1|lpm_rom:lpm_rom_component|altrom:srom|q[0]~reg_ra2 ; DOUT[0] ; CLK        ;
; N/A   ; None         ; 26.600 ns  ; data_rom_10k:u1|lpm_rom:lpm_rom_component|altrom:srom|q[0]~reg_ra3 ; DOUT[0] ; CLK        ;
; N/A   ; None         ; 26.600 ns  ; data_rom_10k:u1|lpm_rom:lpm_rom_component|altrom:srom|q[0]~reg_ra4 ; DOUT[0] ; CLK        ;
; N/A   ; None         ; 26.600 ns  ; data_rom_10k:u1|lpm_rom:lpm_rom_component|altrom:srom|q[0]~reg_ra5 ; DOUT[0] ; CLK        ;
; N/A   ; None         ; 26.600 ns  ; data_rom_10k:u1|lpm_rom:lpm_rom_component|altrom:srom|q[0]~reg_ra6 ; DOUT[0] ; CLK        ;
; N/A   ; None         ; 14.100 ns  ; cout~reg0                                                          ; cout    ; CLK        ;
+-------+--------------+------------+--------------------------------------------------------------------+---------+------------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
    Info: Version 5.0 Build 148 04/26/2005 SJ Full Version
    Info: Processing started: Sat Apr 15 21:19:53 2006
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off sinx_rom -c sinx_rom
Info: Started post-fitting delay annotation
Info: Delay annotation completed successfully
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "CLK" is an undefined clock
Info: Clock "CLK" has Internal fmax of 69.44 MHz between source register "lpm_counter:Q_rtl_0|alt_counter_f10ke:wysi_counter|q[3]" and destination register "lpm_counter:Q_rtl_0|alt_counter_f10ke:wysi_counter|q[6]" (period= 14.4 ns)
    Info: + Longest register to register delay is 10.800 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC4_A14; Fanout = 12; REG Node = 'lpm_counter:Q_rtl_0|alt_counter_f10ke:wysi_counter|q[3]'
        Info: 2: + IC(2.200 ns) + CELL(2.300 ns) = 4.500 ns; Loc. = LC2_A13; Fanout = 2; COMB Node = 'LessThan~63'
        Info: 3: + IC(2.200 ns) + CELL(1.800 ns) = 8.500 ns; Loc. = LC8_A14; Fanout = 13; COMB Node = 'LessThan~64'
        Info: 4: + IC(0.600 ns) + CELL(1.700 ns) = 10.800 ns; Loc. = LC7_A14; Fanout = 10; REG Node = 'lpm_counter:Q_rtl_0|alt_counter_f10ke:wysi_counter|q[6]'
        Info: Total cell delay = 5.800 ns ( 53.70 % )
        Info: Total interconnect delay = 5.000 ns ( 46.30 % )
    Info: - Smallest clock skew is 0.000 ns
        Info: + Shortest clock path from clock "CLK" to destination register is 5.300 ns
            Info: 1: + IC(0.000 ns) + CELL(2.800 ns) = 2.800 ns; Loc. = PIN_43; Fanout = 70; CLK Node = 'CLK'
            Info: 2: + IC(2.500 ns) + CELL(0.000 ns) = 5.300 ns; Loc. = LC7_A14; Fanout = 10; REG Node = 'lpm_counter:Q_rtl_0|alt_counter_f10ke:wysi_counter|q[6]'
            Info: Total cell delay = 2.800 ns ( 52.83 % )
            Info: Total interconnect delay = 2.500 ns ( 47.17 % )
        Info: - Longest clock path from clock "CLK" to source register is 5.300 ns
            Info: 1: + IC(0.000 ns) + CELL(2.800 ns) = 2.800 ns; Loc. = PIN_43; Fanout = 70; CLK Node = 'CLK'
            Info: 2: + IC(2.500 ns) + CELL(0.000 ns) = 5.300 ns; Loc. = LC4_A14; Fanout = 12; REG Node = 'lpm_counter:Q_rtl_0|alt_counter_f10ke:wysi_counter|q[3]'
            Info: Total cell delay = 2.800 ns ( 52.83 % )
            Info: Total interconnect delay = 2.500 ns ( 47.17 % )
    Info: + Micro clock to output delay of source is 1.100 ns
    Info: + Micro setup delay of destination is 2.500 ns
Info: tco from clock "CLK" to destination pin "DOUT[7]" through memory "data_rom_10k:u1|lpm_rom:lpm_rom_component|altrom:srom|q[7]~reg_ra0" is 29.400 ns
    Info: + Longest clock path from clock "CLK" to source memory is 5.300 ns
        Info: 1: + IC(0.000 ns) + CELL(2.800 ns) = 2.800 ns; Loc. = PIN_43; Fanout = 70; CLK Node = 'CLK'
        Info: 2: + IC(2.500 ns) + CELL(0.000 ns) = 5.300 ns; Loc. = EC7_A; Fanout = 1; MEM Node = 'data_rom_10k:u1|lpm_rom:lpm_rom_component|altrom:srom|q[7]~reg_ra0'
        Info: Total cell delay = 2.800 ns ( 52.83 % )
        Info: Total interconnect delay = 2.500 ns ( 47.17 % )
    Info: + Micro clock to output delay of source is 0.600 ns
    Info: + Longest memory to pin delay is 23.500 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = EC7_A; Fanout = 1; MEM Node = 'data_rom_10k:u1|lpm_rom:lpm_rom_component|altrom:srom|q[7]~reg_ra0'
        Info: 2: + IC(0.000 ns) + CELL(10.700 ns) = 10.700 ns; Loc. = EC7_A; Fanout = 1; MEM Node = 'data_rom_10k:u1|lpm_rom:lpm_rom_component|altrom:srom|q[7]~mem_cell_ra0'
        Info: 3: + IC(0.000 ns) + CELL(2.500 ns) = 13.200 ns; Loc. = EC7_A; Fanout = 1; MEM Node = 'data_rom_10k:u1|lpm_rom:lpm_rom_component|altrom:srom|q[7]'
        Info: 4: + IC(5.200 ns) + CELL(5.100 ns) = 23.500 ns; Loc. = PIN_60; Fanout = 0; PIN Node = 'DOUT[7]'
        Info: Total cell delay = 18.300 ns ( 77.87 % )
        Info: Total interconnect delay = 5.200 ns ( 22.13 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning
    Info: Processing ended: Sat Apr 15 21:19:55 2006
    Info: Elapsed time: 00:00:02