divf.vhd

来自「在EDA开发软件QuartusII上利用VHDL语言实现DDS信号发生器」· VHDL 代码 · 共 27 行

LIBRARY  IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITY divf IS
    PORT(  CLK: IN  STD_LOGIC;
           DATA: IN STD_LOGIC_VECTOR(3 DOWNTO 0);
           FOUT: OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
           COUT: OUT STD_LOGIC
        );
END;

ARCHITECTURE behav OF divf IS

   BEGIN
    PROCESS(CLK,DATA)         -- 最大 16 分频
        VARIABLE CNT4: STD_LOGIC_VECTOR(3 DOWNTO 0);
      BEGIN
        IF CLK'EVENT AND CLK='1' THEN 
           IF CNT4<"1111" THEN CNT4:=CNT4+1;COUT<='0';
            ELSE CNT4 :=DATA; COUT<='1';
             END IF;
        END IF;
        FOUT<=CNT4;

    END PROCESS;
END;