divf_rom_sinx.tan.rpt

来自「在EDA开发软件QuartusII上利用VHDL语言实现DDS信号发生器」· RPT 代码 · 共 334 行 · 第 1/5 页

; N/A   ; None         ; 32.300 ns  ; sinx_rom:u2|data_rom_10k:u1|lpm_rom:lpm_rom_component|altrom:srom|q[7]~reg_ra4 ; Dadata[7] ; clkin      ;
; N/A   ; None         ; 32.300 ns  ; sinx_rom:u2|data_rom_10k:u1|lpm_rom:lpm_rom_component|altrom:srom|q[7]~reg_ra5 ; Dadata[7] ; clkin      ;
; N/A   ; None         ; 32.300 ns  ; sinx_rom:u2|data_rom_10k:u1|lpm_rom:lpm_rom_component|altrom:srom|q[7]~reg_ra6 ; Dadata[7] ; clkin      ;
; N/A   ; None         ; 32.300 ns  ; sinx_rom:u2|data_rom_10k:u1|lpm_rom:lpm_rom_component|altrom:srom|q[5]~reg_ra0 ; Dadata[5] ; clkin      ;
; N/A   ; None         ; 32.300 ns  ; sinx_rom:u2|data_rom_10k:u1|lpm_rom:lpm_rom_component|altrom:srom|q[5]~reg_ra1 ; Dadata[5] ; clkin      ;
; N/A   ; None         ; 32.300 ns  ; sinx_rom:u2|data_rom_10k:u1|lpm_rom:lpm_rom_component|altrom:srom|q[5]~reg_ra2 ; Dadata[5] ; clkin      ;
; N/A   ; None         ; 32.300 ns  ; sinx_rom:u2|data_rom_10k:u1|lpm_rom:lpm_rom_component|altrom:srom|q[5]~reg_ra3 ; Dadata[5] ; clkin      ;
; N/A   ; None         ; 32.300 ns  ; sinx_rom:u2|data_rom_10k:u1|lpm_rom:lpm_rom_component|altrom:srom|q[5]~reg_ra4 ; Dadata[5] ; clkin      ;
; N/A   ; None         ; 32.300 ns  ; sinx_rom:u2|data_rom_10k:u1|lpm_rom:lpm_rom_component|altrom:srom|q[5]~reg_ra5 ; Dadata[5] ; clkin      ;
; N/A   ; None         ; 32.300 ns  ; sinx_rom:u2|data_rom_10k:u1|lpm_rom:lpm_rom_component|altrom:srom|q[5]~reg_ra6 ; Dadata[5] ; clkin      ;
; N/A   ; None         ; 32.300 ns  ; sinx_rom:u2|data_rom_10k:u1|lpm_rom:lpm_rom_component|altrom:srom|q[4]~reg_ra0 ; Dadata[4] ; clkin      ;
; N/A   ; None         ; 32.300 ns  ; sinx_rom:u2|data_rom_10k:u1|lpm_rom:lpm_rom_component|altrom:srom|q[4]~reg_ra1 ; Dadata[4] ; clkin      ;
; N/A   ; None         ; 32.300 ns  ; sinx_rom:u2|data_rom_10k:u1|lpm_rom:lpm_rom_component|altrom:srom|q[4]~reg_ra2 ; Dadata[4] ; clkin      ;
; N/A   ; None         ; 32.300 ns  ; sinx_rom:u2|data_rom_10k:u1|lpm_rom:lpm_rom_component|altrom:srom|q[4]~reg_ra3 ; Dadata[4] ; clkin      ;
; N/A   ; None         ; 32.300 ns  ; sinx_rom:u2|data_rom_10k:u1|lpm_rom:lpm_rom_component|altrom:srom|q[4]~reg_ra4 ; Dadata[4] ; clkin      ;
; N/A   ; None         ; 32.300 ns  ; sinx_rom:u2|data_rom_10k:u1|lpm_rom:lpm_rom_component|altrom:srom|q[4]~reg_ra5 ; Dadata[4] ; clkin      ;
; N/A   ; None         ; 32.300 ns  ; sinx_rom:u2|data_rom_10k:u1|lpm_rom:lpm_rom_component|altrom:srom|q[4]~reg_ra6 ; Dadata[4] ; clkin      ;
; N/A   ; None         ; 32.300 ns  ; sinx_rom:u2|data_rom_10k:u1|lpm_rom:lpm_rom_component|altrom:srom|q[2]~reg_ra0 ; Dadata[2] ; clkin      ;
; N/A   ; None         ; 32.300 ns  ; sinx_rom:u2|data_rom_10k:u1|lpm_rom:lpm_rom_component|altrom:srom|q[2]~reg_ra1 ; Dadata[2] ; clkin      ;
; N/A   ; None         ; 32.300 ns  ; sinx_rom:u2|data_rom_10k:u1|lpm_rom:lpm_rom_component|altrom:srom|q[2]~reg_ra2 ; Dadata[2] ; clkin      ;
; N/A   ; None         ; 32.300 ns  ; sinx_rom:u2|data_rom_10k:u1|lpm_rom:lpm_rom_component|altrom:srom|q[2]~reg_ra3 ; Dadata[2] ; clkin      ;
; N/A   ; None         ; 32.300 ns  ; sinx_rom:u2|data_rom_10k:u1|lpm_rom:lpm_rom_component|altrom:srom|q[2]~reg_ra4 ; Dadata[2] ; clkin      ;
; N/A   ; None         ; 32.300 ns  ; sinx_rom:u2|data_rom_10k:u1|lpm_rom:lpm_rom_component|altrom:srom|q[2]~reg_ra5 ; Dadata[2] ; clkin      ;
; N/A   ; None         ; 32.300 ns  ; sinx_rom:u2|data_rom_10k:u1|lpm_rom:lpm_rom_component|altrom:srom|q[2]~reg_ra6 ; Dadata[2] ; clkin      ;
; N/A   ; None         ; 32.300 ns  ; sinx_rom:u2|data_rom_10k:u1|lpm_rom:lpm_rom_component|altrom:srom|q[1]~reg_ra0 ; Dadata[1] ; clkin      ;
; N/A   ; None         ; 32.300 ns  ; sinx_rom:u2|data_rom_10k:u1|lpm_rom:lpm_rom_component|altrom:srom|q[1]~reg_ra1 ; Dadata[1] ; clkin      ;
; N/A   ; None         ; 32.300 ns  ; sinx_rom:u2|data_rom_10k:u1|lpm_rom:lpm_rom_component|altrom:srom|q[1]~reg_ra2 ; Dadata[1] ; clkin      ;
; N/A   ; None         ; 32.300 ns  ; sinx_rom:u2|data_rom_10k:u1|lpm_rom:lpm_rom_component|altrom:srom|q[1]~reg_ra3 ; Dadata[1] ; clkin      ;
; N/A   ; None         ; 32.300 ns  ; sinx_rom:u2|data_rom_10k:u1|lpm_rom:lpm_rom_component|altrom:srom|q[1]~reg_ra4 ; Dadata[1] ; clkin      ;
; N/A   ; None         ; 32.300 ns  ; sinx_rom:u2|data_rom_10k:u1|lpm_rom:lpm_rom_component|altrom:srom|q[1]~reg_ra5 ; Dadata[1] ; clkin      ;
; N/A   ; None         ; 32.300 ns  ; sinx_rom:u2|data_rom_10k:u1|lpm_rom:lpm_rom_component|altrom:srom|q[1]~reg_ra6 ; Dadata[1] ; clkin      ;
; N/A   ; None         ; 18.900 ns  ; sinx_rom:u2|cout                                                               ; f         ; clkin      ;
+-------+--------------+------------+--------------------------------------------------------------------------------+-----------+------------+


+-------------------------------------------------------------------------------------------------------------------------------------+
; th                                                                                                                                  ;
+---------------+-------------+-----------+-----------+--------------------------------------------------------------------+----------+
; Minimum Slack ; Required th ; Actual th ; From      ; To                                                                 ; To Clock ;
+---------------+-------------+-----------+-----------+--------------------------------------------------------------------+----------+
; N/A           ; None        ; 0.800 ns  ; datain[2] ; divf:u1|lpm_counter:CNT4_rtl_1|alt_counter_f10ke:wysi_counter|q[2] ; clkin    ;
; N/A           ; None        ; 0.800 ns  ; datain[1] ; divf:u1|lpm_counter:CNT4_rtl_1|alt_counter_f10ke:wysi_counter|q[1] ; clkin    ;
; N/A           ; None        ; 0.800 ns  ; datain[0] ; divf:u1|lpm_counter:CNT4_rtl_1|alt_counter_f10ke:wysi_counter|q[0] ; clkin    ;
; N/A           ; None        ; 0.800 ns  ; datain[3] ; divf:u1|lpm_counter:CNT4_rtl_1|alt_counter_f10ke:wysi_counter|q[3] ; clkin    ;
+---------------+-------------+-----------+-----------+--------------------------------------------------------------------+----------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
    Info: Version 5.0 Build 148 04/26/2005 SJ Full Version
    Info: Processing started: Sat Apr 15 21:38:17 2006
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off divf_rom_sinx -c divf_rom_sinx
Info: Started post-fitting delay annotation
Info: Delay annotation completed successfully
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "clkin" is an undefined clock
Warning: Found 1 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew
    Info: Detected ripple clock "divf:u1|COUT" as buffer
Info: Clock "clkin" has Internal fmax of 69.44 MHz between source register "sinx_rom:u2|lpm_counter:Q_rtl_0|alt_counter_f10ke:wysi_counter|q[3]" and destination register "sinx_rom:u2|lpm_counter:Q_rtl_0|alt_counter_f10ke:wysi_counter|q[6]" (period= 14.4 ns)
    Info: + Longest register to register delay is 10.800 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC5_A14; Fanout = 12; REG Node = 'sinx_rom:u2|lpm_counter:Q_rtl_0|alt_counter_f10ke:wysi_counter|q[3]'
        Info: 2: + IC(2.200 ns) + CELL(2.300 ns) = 4.500 ns; Loc. = LC1_A13; Fanout = 2; COMB Node = 'sinx_rom:u2|LessThan~63'
        Info: 3: + IC(2.200 ns) + CELL(1.800 ns) = 8.500 ns; Loc. = LC1_A14; Fanout = 13; COM