divf_rom_sinx.tan.rpt
来自「在EDA开发软件QuartusII上利用VHDL语言实现DDS信号发生器」· RPT 代码 · 共 334 行 · 第 1/5 页
RPT
334 行
; Cut off read during write signal paths ; On ; ; ; ;
; Cut off feedback from I/O pins ; On ; ; ; ;
; Report Combined Fast/Slow Timing ; Off ; ; ; ;
; Ignore Clock Settings ; Off ; ; ; ;
; Analyze latches as synchronous elements ; Off ; ; ; ;
; Enable Recovery/Removal analysis ; Off ; ; ; ;
; Enable Clock Latency ; Off ; ; ; ;
+-------------------------------------------------------+--------------------+------+----+-------------+
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; Clock Node Name ; Clock Setting Name ; Type ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ; Phase offset ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; clkin ; ; User Pin ; NONE ; 0.000 ns ; 0.000 ns ; NONE ; N/A ; N/A ; N/A ; ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'clkin' ;
+-------+------------------------------------------------+---------------------------------------------------------------------+--------------------------------------------------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; Slack ; Actual fmax (period) ; From ; To ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-------+------------------------------------------------+---------------------------------------------------------------------+--------------------------------------------------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; N/A ; 69.44 MHz ( period = 14.400 ns ) ; sinx_rom:u2|lpm_counter:Q_rtl_0|alt_counter_f10ke:wysi_counter|q[3] ; sinx_rom:u2|lpm_counter:Q_rtl_0|alt_counter_f10ke:wysi_counter|q[6] ; clkin ; clkin ; None ; None ; 10.800 ns ;
; N/A ; 69.44 MHz ( period = 14.400 ns ) ; sinx_rom:u2|lpm_counter:Q_rtl_0|alt_counter_f10ke:wysi_counter|q[4] ; sinx_rom:u2|lpm_counter:Q_rtl_0|alt_counter_f10ke:wysi_counter|q[6] ; clkin ; clkin ; None ; None ; 10.800 ns ;
; N/A ; 69.44 MHz ( period = 14.400 ns ) ; sinx_rom:u2|lpm_counter:Q_rtl_0|alt_counter_f10ke:wysi_counter|q[5] ; sinx_rom:u2|lpm_counter:Q_rtl_0|alt_counter_f10ke:wysi_counter|q[6] ; clkin ; clkin ; None ; None ; 10.800 ns ;
; N/A ; 69.44 MHz ( period = 14.400 ns ) ; sinx_rom:u2|lpm_counter:Q_rtl_0|alt_counter_f10ke:wysi_counter|q[3] ; sinx_rom:u2|lpm_counter:Q_rtl_0|alt_counter_f10ke:wysi_counter|q[5] ; clkin ; clkin ; None ; None ; 10.800 ns ;
; N/A ; 69.44 MHz ( period = 14.400 ns ) ; sinx_rom:u2|lpm_counter:Q_rtl_0|alt_counter_f10ke:wysi_counter|q[4] ; sinx_rom:u2|lpm_counter:Q_rtl_0|alt_counter_f10ke:wysi_counter|q[5] ; clkin ; clkin ; None ; None ; 10.800 ns ;
; N/A ; 69.44 MHz ( period = 14.400 ns ) ; sinx_rom:u2|lpm_counter:Q_rtl_0|alt_counter_f10ke:wysi_counter|q[5] ; sinx_rom:u2|lpm_counter:Q_rtl_0|alt_counter_f10ke:wysi_counter|q[5] ; clkin ; clkin ; None ; None ; 10.800 ns ;
; N/A ; 69.44 MHz ( period = 14.400 ns ) ; sinx_rom:u2|lpm_counter:Q_rtl_0|alt_counter_f10ke:wysi_counter|q[3] ; sinx_rom:u2|lpm_counter:Q_rtl_0|alt_counter_f10ke:wysi_counter|q[4] ; clkin ; clkin ; None ; None ; 10.800 ns ;
; N/A ; 69.44 MHz ( period = 14.400 ns ) ; sinx_rom:u2|lpm_counter:Q_rtl_0|alt_counter_f10ke:wysi_counter|q[4] ; sinx_rom:u2|lpm_counter:Q_rtl_0|alt_counter_f10ke:wysi_counter|q[4] ; clkin ; clkin ; None ; None ; 10.800 ns ;
; N/A ; 69.44 MHz ( period = 14.400 ns ) ; sinx_rom:u2|lpm_counter:Q_rtl_0|alt_counter_f10ke:wysi_counter|q[5] ; sinx_rom:u2|lpm_counter:Q_rtl_0|alt_counter_f10ke:wysi_counter|q[4] ; clkin ; clkin ; None ; None ; 10.800 ns ;
; N/A ; 69.44 MHz ( period = 14.400 ns ) ; sinx_rom:u2|lpm_counter:Q_rtl_0|alt_counter_f10ke:wysi_counter|q[3] ; sinx_rom:u2|lpm_counter:Q_rtl_0|alt_counter_f10ke:wysi_counter|q[3] ; clkin ; clkin ; None ; None ; 10.800 ns ;
; N/A ; 69.44 MHz ( period = 14.400 ns ) ; sinx_rom:u2|lpm_counter:Q_rtl_0|alt_counter_f10ke:wysi_counter|q[4] ; sinx_rom:u2|lpm_counter:Q_rtl_0|alt_counter_f10ke:wysi_counter|q[3] ; clkin ; clkin ; None ; None ; 10.800 ns ;
; N/A ; 69.44 MHz ( period = 14.400 ns ) ; sinx_rom:u2|lpm_counter:Q_rtl_0|alt_counter_f10ke:wysi_counter|q[5] ; sinx_rom:u2|lpm_counter:Q_rtl_0|alt_counter_f10ke:wysi_counter|q[3] ; clkin ; clkin ; None ; None ; 10.800 ns ;
; N/A ; 69.44 MHz ( period = 14.400 ns ) ; sinx_rom:u2|lpm_counter:Q_rtl_0|alt_counter_f10ke:wysi_counter|q[3] ; sinx_rom:u2|lpm_counter:Q_rtl_0|alt_counter_f10ke:wysi_counter|q[0] ; clkin ; clkin ; None ; None ; 10.800 ns ;
; N/A ; 69.44 MHz ( period = 14.400 ns ) ; sinx_rom:u2|lpm_counter:Q_rtl_0|alt_counter_f10ke:wysi_counter|q[4] ; sinx_rom:u2|lpm_counter:Q_rtl_0|alt_counter_f10ke:wysi_counter|q[0] ; clkin ; clkin ; None ; None ; 10.800 ns ;
; N/A ; 69.44 MHz ( period = 14.400 ns ) ; sinx_rom:u2|lpm_counter:Q_rtl_0|alt_counter_f10ke:wysi_counter|q[5] ; sinx_rom:u2|lpm_counter:Q_rtl_0|alt_counter_f10ke:wysi_counter|q[0] ; clkin ; clkin ; None ; None ; 10.800 ns ;
; N/A ; 69.44 MHz ( period = 14.400 ns ) ; sinx_rom:u2|lpm_counter:Q_rtl_0|alt_counter_f10ke:wysi_counter|q[3] ; sinx_rom:u2|lpm_counter:Q_rtl_0|alt_counter_f10ke:wysi_counter|q[1] ; clkin ; clkin ; None ; None ; 10.800 ns ;
; N/A ; 69.44 MHz ( period = 14.400 ns ) ; sinx_rom:u2|lpm_counter:Q_rtl_0|alt_counter_f10ke:wysi_counter|q[4] ; sinx_rom:u2|lpm_counter:Q_rtl_0|alt_counter_f10ke:wysi_counter|q[1] ; clkin ; clkin ; None ; None ; 10.800 ns ;
; N/A ; 69.44 MHz ( period = 14.400 ns ) ; sinx_rom:u2|lpm_counter:Q_rtl_0|alt_counter_f10ke:wysi_counter|q[5] ; sinx_rom:u2|lpm_counter:Q_rtl_0|alt_counter_f10ke:wysi_counter|q[1] ; clkin ; clkin ; None ; None ; 10.800 ns ;
; N/A ; 69.44 MHz ( period = 14.400 ns ) ; sinx_rom:u2|lpm_counter:Q_rtl_0|alt_counter_f10ke:wysi_counter|q[3] ; sinx_rom:u2|lpm_counter:Q_rtl_0|alt_counter_f10ke:wysi_counter|q[2] ; clkin ; clkin ; None ; None ; 10.800 ns ;
; N/A ; 69.44 MHz ( period = 14.400 ns ) ; sinx_rom:u2|lpm_counter:Q_rtl_0|alt_counter_f10ke:wysi_counter|q[4] ; sinx_rom:u2|lpm_counter:Q_rtl_0|alt_counter_f10ke:wysi_counter|q[2] ; clkin ; clkin ; None ; None ; 10.800 ns ;
; N/A ; 69.44 MHz ( period = 14.400 ns ) ; sinx_rom:u2|lpm_counter:Q_rtl_0|alt_counter_f10ke:wysi_counter|q[5] ; sinx_rom:u2|lpm_counter:Q_rtl_0|alt_counter_f10ke:wysi_counter|q[2] ; clkin ; clkin ; None ; None ; 10.800 ns ;
; N/A ; 71.94 MHz ( period = 13.900 ns ) ; sinx_rom:u2|lpm_counter:Q_rtl_0|alt_counter_f10ke:wysi_counter|q[6] ; sinx_rom:u2|lpm_counter:Q_rtl_0|alt_counter_f10ke:wysi_counter|q[6] ; clkin ; clkin ; None ; None ; 10.300 ns ;
; N/A ; 71.94 MHz ( period = 13.900 ns ) ; sinx_rom:u2|lpm_counter:Q_rtl_0|alt_counter_f10ke:wysi_counter|q[6] ; sinx_rom:u2|lpm_counter:Q_rtl_0|alt_counter_f10ke:wysi_counter|q[5] ; clkin ; clkin ; None ; None ; 10.300 ns ;
; N/A ; 71.94 MHz ( period = 13.900 ns ) ; sinx_rom:u2|lpm_counter:Q_rtl_0|alt_counter_f10ke:wysi_counter|q[6] ; sinx_rom:u2|lpm_counter:Q_rtl_0|alt_counter_f10ke:wysi_counter|q[4] ; clkin ; clkin ; None ; None ; 10.300 ns ;
; N/A ; 71.94 MHz ( period = 13.900 ns ) ; sinx_rom:u2|lpm_counter:Q_rtl_0|alt_counter_f10ke:wysi_counter|q[6] ; sinx_rom:u2|lpm_counter:Q_rtl_0|alt_counter_f10ke:wysi_counter|q[3] ; clkin ; clkin ; None ; None ; 10.300 ns ;
; N/A ; 71.94 MHz ( period = 13.900 ns ) ; sinx_rom:u2|lpm_counter:Q_rtl_0|alt_counter_f10ke:wysi_counter|q[6] ; sinx_rom:u2|lpm_counter:Q_rtl_0|alt_counter_f10ke:wysi_counter|q[0] ; clkin ; clkin ; None ; None ; 10.300 ns ;
; N/A ; 71.94 MHz ( period = 13.900 ns ) ; sinx_rom:u2|lpm_counter:Q_rtl_0|alt_counter_f10ke:wysi_counter|q[6] ; sinx_rom:u2|lpm_counter:Q_rtl_0|alt_counter_f10ke:wysi_counter|q[1] ; clkin ; clkin ; None ; None ; 10.300 ns ;
; N/A ; 71.94 MHz ( period = 13.900 ns ) ; sinx_rom:u2|lpm_counter:Q_rtl_0|alt_counter_f10ke:wysi_counter|q[6] ; sinx_rom:u2|lpm_counter:Q_rtl_0|alt_counter_f10ke:wysi_counter|q[2] ; clkin ; clkin ; None ; None ; 10.300 ns ;
; N/A ; 101.01 MHz ( period = 9.900 ns ) ; sinx_rom:u2|lpm_counter:Q_rtl_0|alt_counter_f10ke:wysi_counter|q[3] ; sinx_rom:u2|cout ; clkin ; clkin ; None ; None ; 6.300 ns ;
; N/A ; 101.01 MHz ( period = 9.900 ns ) ; sinx_rom:u2|lpm_counter:Q_rtl_0|alt_counter_f10ke:wysi_counter|q[4] ; sinx_rom:u2|cout ; clkin ; clkin ; None ; None ; 6.300 ns ;
; N/A ; 101.01 MHz ( period = 9.900 ns ) ; sinx_rom:u2|lpm_counter:Q_rtl_0|alt_counter_f10ke:wysi_counter|q[5] ; sinx_rom:u2|cout ; clkin ; clkin ; None ; None ; 6.300 ns ;
; N/A ; 106.38 MHz ( period = 9.400 ns ) ; sinx_rom:u2|lpm_counter:Q_rtl_0|alt_counter_f10ke:wysi_counter|q[6] ; sinx_rom:u2|cout ; clkin ; clkin ; None ; None ; 5.800 ns ;
; N/A ; 113.64 MHz ( period = 8.800 ns ) ; sinx_rom:u2|lpm_counter:Q_rtl_0|alt_counter_f10ke:wysi_counter|q[2] ; sinx_rom:u2|lpm_counter:Q_rtl_0|alt_counter_f10ke:wysi_counter|q[6] ; clkin ; clkin ; None ; None ; 5.200 ns ;
; N/A ; 113.64 MHz ( period = 8.800 ns ) ; sinx_rom:u2|lpm_counter:Q_rtl_0|alt_counter_f10ke:wysi_counter|q[1] ; sinx_rom:u2|lpm_counter:Q_rtl_0|alt_counter_f10ke:wysi_counter|q[6] ; clkin ; clkin ; None ; None ; 5.200 ns ;
; N/A ; 113.64 MHz ( period = 8.800 ns ) ; sinx_rom:u2|lpm_counter:Q_rtl_0|alt_counter_f10ke:wysi_counter|q[0] ; sinx_rom:u2|lpm_counter:Q_rtl_0|alt_counter_f10ke:wysi_counter|q[6] ; clkin ; clkin ; None ; None ; 5.200 ns ;
; N/A ; 113.64 MHz ( period = 8.800 ns ) ; sinx_rom:u2|lpm_counter:Q_rtl_0|alt_counter_f10ke:wysi_counter|q[2] ; sinx_rom:u2|lpm_counter:Q_rtl_0|alt_counter_f10ke:wysi_counter|q[5] ; clkin ; clkin ; None ; None ; 5.200 ns ;
; N/A ; 113.64 MHz ( period = 8.800 ns ) ; sinx_rom:u2|lpm_counter:Q_rtl_0|alt_counter_f10ke:wysi_counter|q[1] ; sinx_rom:u2|lpm_counter:Q_rtl_0|alt_counter_f10ke:wysi_counter|q[5] ; clkin ; clkin ; None ; None ; 5.200 ns ;
; N/A ; 113.64 MHz ( period = 8.800 ns ) ; sinx_rom:u2|lpm_counter:Q_rtl_0|alt_counter_f10ke:wysi_counter|q[0] ; sinx_rom:u2|lpm_counter:Q_rtl_0|alt_counter_f10ke:wysi_counter|q[5] ; clkin ; clkin ; None ; None ; 5.200 ns ;
; N/A ; 113.64 MHz ( period = 8.800 ns ) ; sinx_rom:u2|lpm_counter:Q_rtl_0|alt_counter_f10ke:wysi_counter|q[2] ; sinx_rom:u2|lpm_counter:Q_rtl_0|alt_counter_f10ke:wysi_counter|q[4] ; clkin ; clkin ; None ; None ; 5.200 ns ;
; N/A ; 113.64 MHz ( period = 8.800 ns ) ; sinx_rom:u2|lpm_counter:Q_rtl_0|alt_counter_f10ke:wysi_counter|q[1] ; sinx_rom:u2|lpm_counter:Q_rtl_0|alt_counter_f10ke:wysi_counter|q[4] ; clkin ; clkin ; None ; None ; 5.200 ns ;
; N/A ; 113.64 MHz ( period = 8.800 ns ) ; sinx_rom:u2|lpm_counter:Q_rtl_0|alt_counter_f10ke:wysi_counter|q[0] ; sinx_rom:u2|lpm_counter:Q_rtl_0|alt_counter_f10ke:wysi_counter|q[4] ; clkin ; clkin ; None ; None ; 5.200 ns ;
; N/A ; 113.64 MHz ( period = 8.800 ns ) ; sinx_rom:u2|lpm_counter:Q_rtl_0|alt_counter_f10ke:wysi_counter|q[2] ; sinx_rom:u2|lpm_counter:Q_rtl_0|alt_counter_f10ke:wysi_counter|q[3] ; clkin ; clkin ; None ; None ; 5.200 ns ;
; N/A ; 113.64 MHz ( period = 8.800 ns ) ; sinx_rom:u2|lpm_counter:Q_rtl_0|alt_counter_f10ke:wysi_counter|q[1] ; sinx_rom:u2|lpm_counter:Q_rtl_0|alt_counter_f10ke:wysi_counter|q[3] ; clkin ; clkin ; None ; None ; 5.200 ns ;
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