sf_df_rom_sinx.flow.rpt

来自「在EDA开发软件QuartusII上利用VHDL语言实现DDS信号发生器」· RPT 代码 · 共 83 行

Flow report for sf_df_rom_sinx
Sat Apr 15 22:13:54 2006
Version 5.0 Build 148 04/26/2005 SJ Full Version


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Flow Summary
  3. Flow Settings
  4. Flow Elapsed Time
  5. Flow Log



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2005 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic       
functions, and any output files any of the foregoing           
(including device programming or simulation files), and any    
associated documentation or information are expressly subject  
to the terms and conditions of the Altera Program License      
Subscription Agreement, Altera MegaCore Function License       
Agreement, or other applicable license agreement, including,   
without limitation, that your use is for the sole purpose of   
programming logic devices manufactured by Altera and sold by   
Altera or its authorized distributors.  Please refer to the    
applicable agreement for further details.



+--------------------------------------------------------------------+
; Flow Summary                                                       ;
+-------------------------+------------------------------------------+
; Flow Status             ; Flow Failed - Sat Apr 15 22:13:54 2006   ;
; Quartus II Version      ; 5.0 Build 148 04/26/2005 SJ Full Version ;
; Revision Name           ; sf_df_rom_sinx                           ;
; Top-level Entity Name   ; sf_df_rom_sinx                           ;
; Family                  ; FLEX10K                                  ;
; Device                  ; EPF10K10LC84-4                           ;
; Timing Models           ; Final                                    ;
; Met timing requirements ; N/A                                      ;
; Total logic elements    ; 20 / 576 ( 3 % )                         ;
; Total pins              ; 11 / 59 ( 18 % )                         ;
; Total memory bits       ; 1,024 / 6,144 ( 16 % )                   ;
+-------------------------+------------------------------------------+


+-----------------------------------------+
; Flow Settings                           ;
+-------------------+---------------------+
; Option            ; Setting             ;
+-------------------+---------------------+
; Start date & time ; 04/15/2006 22:13:35 ;
; Main task         ; Compilation         ;
; Revision Name     ; sf_df_rom_sinx      ;
+-------------------+---------------------+


+-------------------------------------+
; Flow Elapsed Time                   ;
+----------------------+--------------+
; Module Name          ; Elapsed Time ;
+----------------------+--------------+
; Analysis & Synthesis ; 00:00:05     ;
; Fitter               ; 00:00:13     ;
; Total                ; 00:00:18     ;
+----------------------+--------------+


------------
; Flow Log ;
------------
quartus_map --read_settings_files=on --write_settings_files=off sf_df_rom_sinx -c sf_df_rom_sinx
quartus_fit --read_settings_files=off --write_settings_files=off sf_df_rom_sinx -c sf_df_rom_sinx