scan_divf_sinx2.tan.qmsg

来自「在EDA开发软件QuartusII上利用VHDL语言实现DDS信号发生器」· QMSG 代码 · 共 13 行 · 第 1/3 页

{ "Info" "ITDB_TH_RESULT" "SCANCNT4B:u1\|lpm_counter:CNT4_rtl_1\|alt_counter_f10ke:wysi_counter\|q\[3\] enable clock 1.300 ns register " "Info: th for register \"SCANCNT4B:u1\|lpm_counter:CNT4_rtl_1\|alt_counter_f10ke:wysi_counter\|q\[3\]\" (data pin = \"enable\", clock pin = \"clock\") is 1.300 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock destination 5.300 ns + Longest register " "Info: + Longest clock path from clock \"clock\" to destination register is 5.300 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.800 ns) 2.800 ns clock 1 CLK PIN_43 15 " "Info: 1: + IC(0.000 ns) + CELL(2.800 ns) = 2.800 ns; Loc. = PIN_43; Fanout = 15; CLK Node = 'clock'" {  } { { "E:/EDA/DDS/10k844/scan_divf_sinx2/db/scan_divf_sinx2_cmp.qrpt" "" { Report "E:/EDA/DDS/10k844/scan_divf_sinx2/db/scan_divf_sinx2_cmp.qrpt" Compiler "scan_divf_sinx2" "UNKNOWN" "V1" "E:/EDA/DDS/10k844/scan_divf_sinx2/db/scan_divf_sinx2.quartus_db" { Floorplan "E:/EDA/DDS/10k844/scan_divf_sinx2/" "" "" { clock } "NODE_NAME" } "" } } { "scan_divf_sinx2.vhd" "" { Text "E:/EDA/DDS/10k844/scan_divf_sinx2/scan_divf_sinx2.vhd" 6 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.500 ns) + CELL(0.000 ns) 5.300 ns SCANCNT4B:u1\|lpm_counter:CNT4_rtl_1\|alt_counter_f10ke:wysi_counter\|q\[3\] 2 REG LC8_C11 2 " "Info: 2: + IC(2.500 ns) + CELL(0.000 ns) = 5.300 ns; Loc. = LC8_C11; Fanout = 2; REG Node = 'SCANCNT4B:u1\|lpm_counter:CNT4_rtl_1\|alt_counter_f10ke:wysi_counter\|q\[3\]'" {  } { { "E:/EDA/DDS/10k844/scan_divf_sinx2/db/scan_divf_sinx2_cmp.qrpt" "" { Report "E:/EDA/DDS/10k844/scan_divf_sinx2/db/scan_divf_sinx2_cmp.qrpt" Compiler "scan_divf_sinx2" "UNKNOWN" "V1" "E:/EDA/DDS/10k844/scan_divf_sinx2/db/scan_divf_sinx2.quartus_db" { Floorplan "E:/EDA/DDS/10k844/scan_divf_sinx2/" "" "2.500 ns" { clock SCANCNT4B:u1|lpm_counter:CNT4_rtl_1|alt_counter_f10ke:wysi_counter|q[3] } "NODE_NAME" } "" } } { "alt_counter_f10ke.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/alt_counter_f10ke.tdf" 271 2 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.800 ns 52.83 % " "Info: Total cell delay = 2.800 ns ( 52.83 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.500 ns 47.17 % " "Info: Total interconnect delay = 2.500 ns ( 47.17 % )" {  } {  } 0}  } { { "E:/EDA/DDS/10k844/scan_divf_sinx2/db/scan_divf_sinx2_cmp.qrpt" "" { Report "E:/EDA/DDS/10k844/scan_divf_sinx2/db/scan_divf_sinx2_cmp.qrpt" Compiler "scan_divf_sinx2" "UNKNOWN" "V1" "E:/EDA/DDS/10k844/scan_divf_sinx2/db/scan_divf_sinx2.quartus_db" { Floorplan "E:/EDA/DDS/10k844/scan_divf_sinx2/" "" "5.300 ns" { clock SCANCNT4B:u1|lpm_counter:CNT4_rtl_1|alt_counter_f10ke:wysi_counter|q[3] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "5.300 ns" { clock clock~out SCANCNT4B:u1|lpm_counter:CNT4_rtl_1|alt_counter_f10ke:wysi_counter|q[3] } { 0.000ns 0.000ns 2.500ns } { 0.000ns 2.800ns 0.000ns } } }  } 0} { "Info" "ITDB_FULL_TH_DELAY" "1.600 ns + " "Info: + Micro hold delay of destination is 1.600 ns" {  } { { "alt_counter_f10ke.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/alt_counter_f10ke.tdf" 271 2 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.600 ns - Shortest pin register " "Info: - Shortest pin to register delay is 5.600 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.800 ns) 2.800 ns enable 1 PIN PIN_2 14 " "Info: 1: + IC(0.000 ns) + CELL(2.800 ns) = 2.800 ns; Loc. = PIN_2; Fanout = 14; PIN Node = 'enable'" {  } { { "E:/EDA/DDS/10k844/scan_divf_sinx2/db/scan_divf_sinx2_cmp.qrpt" "" { Report "E:/EDA/DDS/10k844/scan_divf_sinx2/db/scan_divf_sinx2_cmp.qrpt" Compiler "scan_divf_sinx2" "UNKNOWN" "V1" "E:/EDA/DDS/10k844/scan_divf_sinx2/db/scan_divf_sinx2.quartus_db" { Floorplan "E:/EDA/DDS/10k844/scan_divf_sinx2/" "" "" { enable } "NODE_NAME" } "" } } { "scan_divf_sinx2.vhd" "" { Text "E:/EDA/DDS/10k844/scan_divf_sinx2/scan_divf_sinx2.vhd" 6 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.600 ns) + CELL(1.200 ns) 5.600 ns SCANCNT4B:u1\|lpm_counter:CNT4_rtl_1\|alt_counter_f10ke:wysi_counter\|q\[3\] 2 REG LC8_C11 2 " "Info: 2: + IC(1.600 ns) + CELL(1.200 ns) = 5.600 ns; Loc. = LC8_C11; Fanout = 2; REG Node = 'SCANCNT4B:u1\|lpm_counter:CNT4_rtl_1\|alt_counter_f10ke:wysi_counter\|q\[3\]'" {  } { { "E:/EDA/DDS/10k844/scan_divf_sinx2/db/scan_divf_sinx2_cmp.qrpt" "" { Report "E:/EDA/DDS/10k844/scan_divf_sinx2/db/scan_divf_sinx2_cmp.qrpt" Compiler "scan_divf_sinx2" "UNKNOWN" "V1" "E:/EDA/DDS/10k844/scan_divf_sinx2/db/scan_divf_sinx2.quartus_db" { Floorplan "E:/EDA/DDS/10k844/scan_divf_sinx2/" "" "2.800 ns" { enable SCANCNT4B:u1|lpm_counter:CNT4_rtl_1|alt_counter_f10ke:wysi_counter|q[3] } "NODE_NAME" } "" } } { "alt_counter_f10ke.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/alt_counter_f10ke.tdf" 271 2 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.000 ns 71.43 % " "Info: Total cell delay = 4.000 ns ( 71.43 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.600 ns 28.57 % " "Info: Total interconnect delay = 1.600 ns ( 28.57 % )" {  } {  } 0}  } { { "E:/EDA/DDS/10k844/scan_divf_sinx2/db/scan_divf_sinx2_cmp.qrpt" "" { Report "E:/EDA/DDS/10k844/scan_divf_sinx2/db/scan_divf_sinx2_cmp.qrpt" Compiler "scan_divf_sinx2" "UNKNOWN" "V1" "E:/EDA/DDS/10k844/scan_divf_sinx2/db/scan_divf_sinx2.quartus_db" { Floorplan "E:/EDA/DDS/10k844/scan_divf_sinx2/" "" "5.600 ns" { enable SCANCNT4B:u1|lpm_counter:CNT4_rtl_1|alt_counter_f10ke:wysi_counter|q[3] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "5.600 ns" { enable enable~out SCANCNT4B:u1|lpm_counter:CNT4_rtl_1|alt_counter_f10ke:wysi_counter|q[3] } { 0.000ns 0.000ns 1.600ns } { 0.000ns 2.800ns 1.200ns } } }  } 0}  } { { "E:/EDA/DDS/10k844/scan_divf_sinx2/db/scan_divf_sinx2_cmp.qrpt" "" { Report "E:/EDA/DDS/10k844/scan_divf_sinx2/db/scan_divf_sinx2_cmp.qrpt" Compiler "scan_divf_sinx2" "UNKNOWN" "V1" "E:/EDA/DDS/10k844/scan_divf_sinx2/db/scan_divf_sinx2.quartus_db" { Floorplan "E:/EDA/DDS/10k844/scan_divf_sinx2/" "" "5.300 ns" { clock SCANCNT4B:u1|lpm_counter:CNT4_rtl_1|alt_counter_f10ke:wysi_counter|q[3] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "5.300 ns" { clock clock~out SCANCNT4B:u1|lpm_counter:CNT4_rtl_1|alt_counter_f10ke:wysi_counter|q[3] } { 0.000ns 0.000ns 2.500ns } { 0.000ns 2.800ns 0.000ns } } } { "E:/EDA/DDS/10k844/scan_divf_sinx2/db/scan_divf_sinx2_cmp.qrpt" "" { Report "E:/EDA/DDS/10k844/scan_divf_sinx2/db/scan_divf_sinx2_cmp.qrpt" Compiler "scan_divf_sinx2" "UNKNOWN" "V1" "E:/EDA/DDS/10k844/scan_divf_sinx2/db/scan_divf_sinx2.quartus_db" { Floorplan "E:/EDA/DDS/10k844/scan_divf_sinx2/" "" "5.600 ns" { enable SCANCNT4B:u1|lpm_counter:CNT4_rtl_1|alt_counter_f10ke:wysi_counter|q[3] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "5.600 ns" { enable enable~out SCANCNT4B:u1|lpm_counter:CNT4_rtl_1|alt_counter_f10ke:wysi_counter|q[3] } { 0.000ns 0.000ns 1.600ns } { 0.000ns 2.800ns 1.200ns } } }  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 2 s Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Fri Apr 14 22:18:10 2006 " "Info: Processing ended: Fri Apr 14 22:18:10 2006" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Info: Elapsed time: 00:00:03" {  } {  } 0}  } {  } 0}