scan_divf_sinx2.tan.qmsg

来自「在EDA开发软件QuartusII上利用VHDL语言实现DDS信号发生器」· QMSG 代码 · 共 13 行 · 第 1/3 页

{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clock " "Info: Assuming node \"clock\" is an undefined clock" {  } { { "scan_divf_sinx2.vhd" "" { Text "E:/EDA/DDS/10k844/scan_divf_sinx2/scan_divf_sinx2.vhd" 6 -1 0 } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "clock" } } } }  } 0}  } {  } 0}
{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "1 " "Warning: Found 1 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "divf:u2\|COUT " "Info: Detected ripple clock \"divf:u2\|COUT\" as buffer" {  } { { "divf.vhd" "" { Text "E:/EDA/DDS/10k844/scan_divf_sinx2/divf.vhd" 9 -1 0 } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "divf:u2\|COUT" } } } }  } 0}  } {  } 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clock register singt4:u3\|q\[2\] register singt4:u3\|q\[6\] 79.37 MHz 12.6 ns Internal " "Info: Clock \"clock\" has Internal fmax of 79.37 MHz between source register \"singt4:u3\|q\[2\]\" and destination register \"singt4:u3\|q\[6\]\" (period= 12.6 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "9.000 ns + Longest register register " "Info: + Longest register to register delay is 9.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns singt4:u3\|q\[2\] 1 REG LC2_C13 49 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC2_C13; Fanout = 49; REG Node = 'singt4:u3\|q\[2\]'" {  } { { "E:/EDA/DDS/10k844/scan_divf_sinx2/db/scan_divf_sinx2_cmp.qrpt" "" { Report "E:/EDA/DDS/10k844/scan_divf_sinx2/db/scan_divf_sinx2_cmp.qrpt" Compiler "scan_divf_sinx2" "UNKNOWN" "V1" "E:/EDA/DDS/10k844/scan_divf_sinx2/db/scan_divf_sinx2.quartus_db" { Floorplan "E:/EDA/DDS/10k844/scan_divf_sinx2/" "" "" { singt4:u3|q[2] } "NODE_NAME" } "" } } { "singt4.vhd" "" { Text "E:/EDA/DDS/10k844/scan_divf_sinx2/singt4.vhd" 13 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.200 ns) + CELL(1.200 ns) 3.400 ns singt4:u3\|lpm_add_sub:add_rtl_2\|addcore:adder\|a_csnbuffer:result_node\|cout\[2\] 2 COMB LC3_C14 2 " "Info: 2: + IC(2.200 ns) + CELL(1.200 ns) = 3.400 ns; Loc. = LC3_C14; Fanout = 2; COMB Node = 'singt4:u3\|lpm_add_sub:add_rtl_2\|addcore:adder\|a_csnbuffer:result_node\|cout\[2\]'" {  } { { "E:/EDA/DDS/10k844/scan_divf_sinx2/db/scan_divf_sinx2_cmp.qrpt" "" { Report "E:/EDA/DDS/10k844/scan_divf_sinx2/db/scan_divf_sinx2_cmp.qrpt" Compiler "scan_divf_sinx2" "UNKNOWN" "V1" "E:/EDA/DDS/10k844/scan_divf_sinx2/db/scan_divf_sinx2.quartus_db" { Floorplan "E:/EDA/DDS/10k844/scan_divf_sinx2/" "" "3.400 ns" { singt4:u3|q[2] singt4:u3|lpm_add_sub:add_rtl_2|addcore:adder|a_csnbuffer:result_node|cout[2] } "NODE_NAME" } "" } } { "a_csnbuffer.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/a_csnbuffer.tdf" 18 2 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.300 ns) 3.700 ns singt4:u3\|lpm_add_sub:add_rtl_2\|addcore:adder\|a_csnbuffer:result_node\|cout\[3\] 3 COMB LC4_C14 2 " "Info: 3: + IC(0.000 ns) + CELL(0.300 ns) = 3.700 ns; Loc. = LC4_C14; Fanout = 2; COMB Node = 'singt4:u3\|lpm_add_sub:add_rtl_2\|addcore:adder\|a_csnbuffer:result_node\|cout\[3\]'" {  } { { "E:/EDA/DDS/10k844/scan_divf_sinx2/db/scan_divf_sinx2_cmp.qrpt" "" { Report "E:/EDA/DDS/10k844/scan_divf_sinx2/db/scan_divf_sinx2_cmp.qrpt" Compiler "scan_divf_sinx2" "UNKNOWN" "V1" "E:/EDA/DDS/10k844/scan_divf_sinx2/db/scan_divf_sinx2.quartus_db" { Floorplan "E:/EDA/DDS/10k844/scan_divf_sinx2/" "" "0.300 ns" { singt4:u3|lpm_add_sub:add_rtl_2|addcore:adder|a_csnbuffer:result_node|cout[2] singt4:u3|lpm_add_sub:add_rtl_2|addcore:adder|a_csnbuffer:result_node|cout[3] } "NODE_NAME" } "" } } { "a_csnbuffer.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/a_csnbuffer.tdf" 18 2 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.300 ns) 4.000 ns singt4:u3\|lpm_add_sub:add_rtl_2\|addcore:adder\|a_csnbuffer:result_node\|cout\[4\] 4 COMB LC5_C14 2 " "Info: 4: + IC(0.000 ns) + CELL(0.300 ns) = 4.000 ns; Loc. = LC5_C14; Fanout = 2; COMB Node = 'singt4:u3\|lpm_add_sub:add_rtl_2\|addcore:adder\|a_csnbuffer:result_node\|cout\[4\]'" {  } { { "E:/EDA/DDS/10k844/scan_divf_sinx2/db/scan_divf_sinx2_cmp.qrpt" "" { Report "E:/EDA/DDS/10k844/scan_divf_sinx2/db/scan_divf_sinx2_cmp.qrpt" Compiler "scan_divf_sinx2" "UNKNOWN" "V1" "E:/EDA/DDS/10k844/scan_divf_sinx2/db/scan_divf_sinx2.quartus_db" { Floorplan "E:/EDA/DDS/10k844/scan_divf_sinx2/" "" "0.300 ns" { singt4:u3|lpm_add_sub:add_rtl_2|addcore:adder|a_csnbuffer:result_node|cout[3] singt4:u3|lpm_add_sub:add_rtl_2|addcore:adder|a_csnbuffer:result_node|cout[4] } "NODE_NAME" } "" } } { "a_csnbuffer.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/a_csnbuffer.tdf" 18 2 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.300 ns) 4.300 ns singt4:u3\|lpm_add_sub:add_rtl_2\|addcore:adder\|a_csnbuffer:result_node\|cout\[5\] 5 COMB LC6_C14 1 " "Info: 5: + IC(0.000 ns) + CELL(0.300 ns) = 4.300 ns; Loc. = LC6_C14; Fanout = 1; COMB Node = 'singt4:u3\|lpm_add_sub:add_rtl_2\|addcore:adder\|a_csnbuffer:result_node\|cout\[5\]'" {  } { { "E:/EDA/DDS/10k844/scan_divf_sinx2/db/scan_divf_sinx2_cmp.qrpt" "" { Report "E:/EDA/DDS/10k844/scan_divf_sinx2/db/scan_divf_sinx2_cmp.qrpt" Compiler "scan_divf_sinx2" "UNKNOWN" "V1" "E:/EDA/DDS/10k844/scan_divf_sinx2/db/scan_divf_sinx2.quartus_db" { Floorplan "E:/EDA/DDS/10k844/scan_divf_sinx2/" "" "0.300 ns" { singt4:u3|lpm_add_sub:add_rtl_2|addcore:adder|a_csnbuffer:result_node|cout[4] singt4:u3|lpm_add_sub:add_rtl_2|addcore:adder|a_csnbuffer:result_node|cout[5] } "NODE_NAME" } "" } } { "a_csnbuffer.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/a_csnbuffer.tdf" 18 2 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.300 ns) 5.600 ns singt4:u3\|lpm_add_sub:add_rtl_2\|addcore:adder\|unreg_res_node\[6\] 6 COMB LC7_C14 1 " "Info: 6: + IC(0.000 ns) + CELL(1.300 ns) = 5.600 ns; Loc. = LC7_C14; Fanout = 1; COMB Node = 'singt4:u3\|lpm_add_sub:add_rtl_2\|addcore:adder\|unreg_res_node\[6\]'" {  } { { "E:/EDA/DDS/10k844/scan_divf_sinx2/db/scan_divf_sinx2_cmp.qrpt" "" { Report "E:/EDA/DDS/10k844/scan_divf_sinx2/db/scan_divf_sinx2_cmp.qrpt" Compiler "scan_divf_sinx2" "UNKNOWN" "V1" "E:/EDA/DDS/10k844/scan_divf_sinx2/db/scan_divf_sinx2.quartus_db" { Floorplan "E:/EDA/DDS/10k844/scan_divf_sinx2/" "" "1.300 ns" { singt4:u3|lpm_add_sub:add_rtl_2|addcore:adder|a_csnbuffer:result_node|cout[5] singt4:u3|lpm_add_sub:add_rtl_2|addcore:adder|unreg_res_node[6] } "NODE_NAME" } "" } } { "addcore.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/addcore.tdf" 95 16 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.200 ns) + CELL(1.200 ns) 9.000 ns singt4:u3\|q\[6\] 7 REG LC8_C13 10 " "Info: 7: + IC(2.200 ns) + CELL(1.200 ns) = 9.000 ns; Loc. = LC8_C13; Fanout = 10; REG Node = 'singt4:u3\|q\[6\]'" {  } { { "E:/EDA/DDS/10k844/scan_divf_sinx2/db/scan_divf_sinx2_cmp.qrpt" "" { Report "E:/EDA/DDS/10k844/scan_divf_sinx2/db/scan_divf_sinx2_cmp.qrpt" Compiler "scan_divf_sinx2" "UNKNOWN" "V1" "E:/EDA/DDS/10k844/scan_divf_sinx2/db/scan_divf_sinx2.quartus_db" { Floorplan "E:/EDA/DDS/10k844/scan_divf_sinx2/" "" "3.400 ns" { singt4:u3|lpm_add_sub:add_rtl_2|addcore:adder|unreg_res_node[6] singt4:u3|q[6] } "NODE_NAME" } "" } } { "singt4.vhd" "" { Text "E:/EDA/DDS/10k844/scan_divf_sinx2/singt4.vhd" 13 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.600 ns 51.11 % " "Info: Total cell delay = 4.600 ns ( 51.11 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.400 ns 48.89 % " "Info: Total interconnect delay = 4.400 ns ( 48.89 % )" {  } {  } 0}  } { { "E:/EDA/DDS/10k844/scan_divf_sinx2/db/scan_divf_sinx2_cmp.qrpt" "" { Report "E:/EDA/DDS/10k844/scan_divf_sinx2/db/scan_divf_sinx2_cmp.qrpt" Compiler "scan_divf_sinx2" "UNKNOWN" "V1" "E:/EDA/DDS/10k844/scan_divf_sinx2/db/scan_divf_sinx2.quartus_db" { Floorplan "E:/EDA/DDS/10k844/scan_divf_sinx2/" "" "9.000 ns" { singt4:u3|q[2] singt4:u3|lpm_add_sub:add_rtl_2|addcore:adder|a_csnbuffer:result_node|cout[2] singt4:u3|lpm_add_sub:add_rtl_2|addcore:adder|a_csnbuffer:result_node|cout[3] singt4:u3|lpm_add_sub:add_rtl_2|addcore:adder|a_csnbuffer:result_node|cout[4] singt4:u3|lpm_add_sub:add_rtl_2|addcore:adder|a_csnbuffer:result_node|cout[5] singt4:u3|lpm_add_sub:add_rtl_2|addcore:adder|unreg_res_node[6] singt4:u3|q[6] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "9.000 ns" { singt4:u3|q[2] singt4:u3|lpm_add_sub:add_rtl_2|addcore:adder|a_csnbuffer:result_node|cout[2] singt4:u3|lpm_add_sub:add_rtl_2|addcore:adder|a_csnbuffer:result_node|cout[3] singt4:u3|lpm_add_sub:add_rtl_2|addcore:adder|a_csnbuffer:result_node|cout[4] singt4:u3|lpm_add_sub:add_rtl_2|addcore:adder|a_csnbuffer:result_node|cout[5] singt4:u3|lpm_add_sub:add_rtl_2|addcore:adder|unreg_res_node[6] singt4:u3|q[6] } { 0.000ns 2.200ns 0.000ns 0.000ns 0.000ns 0.000ns 2.200ns } { 0.000ns 1.200ns 0.300ns 0.300ns 0.300ns 1.300ns 1.200ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock destination 10.900 ns + Shortest register " "Info: + Shortest clock path from clock \"clock\" to destination register is 10.900 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.800 ns) 2.800 ns clock 1 CLK PIN_43 15 " "Info: 1: + IC(0.000 ns) + CELL(2.800 ns) = 2.800 ns; Loc. = PIN_43; Fanout = 15; CLK Node = 'clock'" {  } { { "E:/EDA/DDS/10k844/scan_divf_sinx2/db/scan_divf_sinx2_cmp.qrpt" "" { Report "E:/EDA/DDS/10k844/scan_divf_sinx2/db/scan_divf_sinx2_cmp.qrpt" Compiler "scan_divf_sinx2" "UNKNOWN" "V1" "E:/EDA/DDS/10k844/scan_divf_sinx2/db/scan_divf_sinx2.quartus_db" { Floorplan "E:/EDA/DDS/10k844/scan_divf_sinx2/" "" "" { clock } "NODE_NAME" } "" } } { "scan_divf_sinx2.vhd" "" { Text "E:/EDA/DDS/10k844/scan_divf_sinx2/scan_divf_sinx2.vhd" 6 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.500 ns) + CELL(1.100 ns) 6.400 ns divf:u2\|COUT 2 REG LC1_C6 8 " "Info: 2: + IC(2.500 ns) + CELL(1.100 ns) = 6.400 ns; Loc. = LC1_C6; Fanout = 8; REG Node = 'divf:u2\|COUT'" {  } { { "E:/EDA/DDS/10k844/scan_divf_sinx2/db/scan_divf_sinx2_cmp.qrpt" "" { Report "E:/EDA/DDS/10k844/scan_divf_sinx2/db/scan_divf_sinx2_cmp.qrpt" Compiler "scan_divf_sinx2" "UNKNOWN" "V1" "E:/EDA/DDS/10k844/scan_divf_sinx2/db/scan_divf_sinx2.quartus_db" { Floorplan "E:/EDA/DDS/10k844/scan_divf_sinx2/" "" "3.600 ns" { clock divf:u2|COUT } "NODE_NAME" } "" } } { "divf.vhd" "" { Text "E:/EDA/DDS/10k844/scan_divf_sinx2/divf.vhd" 9 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(4.500 ns) + CELL(0.000 ns) 10.900 ns singt4:u3\|q\[6\] 3 REG LC8_C13 10 " "Info: 3: + IC(4.500 ns) + CELL(0.000 ns) = 10.900 ns; Loc. = LC8_C13; Fanout = 10; REG Node = 'singt4:u3\|q\[6\]'" {  } { { "E:/EDA/DDS/10k844/scan_divf_sinx2/db/scan_divf_sinx2_cmp.qrpt" "" { Report "E:/EDA/DDS/10k844/scan_divf_sinx2/db/scan_divf_sinx2_cmp.qrpt" Compiler "scan_divf_sinx2" "UNKNOWN" "V1" "E:/EDA/DDS/10k844/scan_divf_sinx2/db/scan_divf_sinx2.quartus_db" { Floorplan "E:/EDA/DDS/10k844/scan_divf_sinx2/" "" "4.500 ns" { divf:u2|COUT singt4:u3|q[6] } "NODE_NAME" } "" } } { "singt4.vhd" "" { Text "E:/EDA/DDS/10k844/scan_divf_sinx2/singt4.vhd" 13 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.900 ns 35.78 % " "Info: Total cell delay = 3.900 ns ( 35.78 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "7.000 ns 64.22 % " "Info: Total interconnect delay = 7.000 ns ( 64.22 % )" {  } {  } 0}  } { { "E:/EDA/DDS/10k844/scan_divf_sinx2/db/scan_divf_sinx2_cmp.qrpt" "" { Report "E:/EDA/DDS/10k844/scan_divf_sinx2/db/scan_divf_sinx2_cmp.qrpt" Compiler "scan_divf_sinx2" "UNKNOWN" "V1" "E:/EDA/DDS/10k844/scan_divf_sinx2/db/scan_divf_sinx2.quartus_db" { Floorplan "E:/EDA/DDS/10k844/scan_divf_sinx2/" "" "10.900 ns" { clock divf:u2|COUT singt4:u3|q[6] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "10.900 ns" { clock clock~out divf:u2|COUT singt4:u3|q[6] } { 0.000ns 0.000ns 2.500ns 4.500ns } { 0.000ns 2.800ns 1.100ns 0.000ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock source 10.900 ns - Longest register " "Info: - Longest clock path from clock \"clock\" to source register is 10.900 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.800 ns) 2.800 ns clock 1 CLK PIN_43 15 " "Info: 1: + IC(0.000 ns) + CELL(2.800 ns) = 2.800 ns; Loc. = PIN_43; Fanout = 15; CLK Node = 'clock'" {  } { { "E:/EDA/DDS/10k844/scan_divf_sinx2/db/scan_divf_sinx2_cmp.qrpt" "" { Report "E:/EDA/DDS/10k844/scan_divf_sinx2/db/scan_divf_sinx2_cmp.qrpt" Compiler "scan_divf_sinx2" "UNKNOWN" "V1" "E:/EDA/DDS/10k844/scan_divf_sinx2/db/scan_divf_sinx2.quartus_db" { Floorplan "E:/EDA/DDS/10k844/scan_divf_sinx2/" "" "" { clock } "NODE_NAME" } "" } } { "scan_divf_sinx2.vhd" "" { Text "E:/EDA/DDS/10k844/scan_divf_sinx2/scan_divf_sinx2.vhd" 6 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.500 ns) + CELL(1.100 ns) 6.400 ns divf:u2\|COUT 2 REG LC1_C6 8 " "Info: 2: + IC(2.500 ns) + CELL(1.100 ns) = 6.400 ns; Loc. = LC1_C6; Fanout = 8; REG Node = 'divf:u2\|COUT'" {  } { { "E:/EDA/DDS/10k844/scan_divf_sinx2/db/scan_divf_sinx2_cmp.qrpt" "" { Report "E:/EDA/DDS/10k844/scan_divf_sinx2/db/scan_divf_sinx2_cmp.qrpt" Compiler "scan_divf_sinx2" "UNKNOWN" "V1" "E:/EDA/DDS/10k844/scan_divf_sinx2/db/scan_divf_sinx2.quartus_db" { Floorplan "E:/EDA/DDS/10k844/scan_divf_sinx2/" "" "3.600 ns" { clock divf:u2|COUT } "NODE_NAME" } "" } } { "divf.vhd" "" { Text "E:/EDA/DDS/10k844/scan_divf_sinx2/divf.vhd" 9 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(4.500 ns) + CELL(0.000 ns) 10.900 ns singt4:u3\|q\[2\] 3 REG LC2_C13 49 " "Info: 3: + IC(4.500 ns) + CELL(0.000 ns) = 10.900 ns; Loc. = LC2_C13; Fanout = 49; REG Node = 'singt4:u3\|q\[2\]'" {  } { { "E:/EDA/DDS/10k844/scan_divf_sinx2/db/scan_divf_sinx2_cmp.qrpt" "" { Report "E:/EDA/DDS/10k844/scan_divf_sinx2/db/scan_divf_sinx2_cmp.qrpt" Compiler "scan_divf_sinx2" "UNKNOWN" "V1" "E:/EDA/DDS/10k844/scan_divf_sinx2/db/scan_divf_sinx2.quartus_db" { Floorplan "E:/EDA/DDS/10k844/scan_divf_sinx2/" "" "4.500 ns" { divf:u2|COUT singt4:u3|q[2] } "NODE_NAME" } "" } } { "singt4.vhd" "" { Text "E:/EDA/DDS/10k844/scan_divf_sinx2/singt4.vhd" 13 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.900 ns 35.78 % " "Info: Total cell delay = 3.900 ns ( 35.78 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "7.000 ns 64.22 % " "Info: Total interconnect delay = 7.000 ns ( 64.22 % )" {  } {  } 0}  } { { "E:/EDA/DDS/10k844/scan_divf_sinx2/db/scan_divf_sinx2_cmp.qrpt" "" { Report "E:/EDA/DDS/10k844/scan_divf_sinx2/db/scan_divf_sinx2_cmp.qrpt" Compiler "scan_divf_sinx2" "UNKNOWN" "V1" "E:/EDA/DDS/10k844/scan_divf_sinx2/db/scan_divf_sinx2.quartus_db" { Floorplan "E:/EDA/DDS/10k844/scan_divf_sinx2/" "" "10.900 ns" { clock divf:u2|COUT singt4:u3|q[2] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "10.900 ns" { clock clock~out divf:u2|COUT singt4:u3|q[2] } { 0.000ns 0.000ns 2.500ns 4.500ns } { 0.000ns 2.800ns 1.100ns 0.000ns } } }  } 0}  } { { "E:/EDA/DDS/10k844/scan_divf_sinx2/db/scan_divf_sinx2_cmp.qrpt" "" { Report "E:/EDA/DDS/10k844/scan_divf_sinx2/db/scan_divf_sinx2_cmp.qrpt" Compiler "scan_divf_sinx2" "UNKNOWN" "V1" "E:/EDA/DDS/10k844/scan_divf_sinx2/db/scan_divf_sinx2.quartus_db" { Floorplan "E:/EDA/DDS/10k844/scan_divf_sinx2/" "" "10.900 ns" { clock divf:u2|COUT singt4:u3|q[6] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "10.900 ns" { clock clock~out divf:u2|COUT singt4:u3|q[6] } { 0.000ns 0.000ns 2.500ns 4.500ns } { 0.000ns 2.800ns 1.100ns 0.000ns } } } { "E:/EDA/DDS/10k844/scan_divf_sinx2/db/scan_divf_sinx2_cmp.qrpt" "" { Report "E:/EDA/DDS/10k844/scan_divf_sinx2/db/scan_divf_sinx2_cmp.qrpt" Compiler "scan_divf_sinx2" "UNKNOWN" "V1" "E:/EDA/DDS/10k844/scan_divf_sinx2/db/scan_divf_sinx2.quartus_db" { Floorplan "E:/EDA/DDS/10k844/scan_divf_sinx2/" "" "10.900 ns" { clock divf:u2|COUT singt4:u3|q[2] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "10.900 ns" { clock clock~out divf:u2|COUT singt4:u3|q[2] } { 0.000ns 0.000ns 2.500ns 4.500ns } { 0.000ns 2.800ns 1.100ns 0.000ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.100 ns + " "Info: + Micro clock to output delay of source is 1.100 ns" {  } { { "singt4.vhd" "" { Text "E:/EDA/DDS/10k844/scan_divf_sinx2/singt4.vhd" 13 -1 0 } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "2.500 ns + " "Info: + Micro setup delay of destination is 2.500 ns" {  } { { "singt4.vhd" "" { Text "E:/EDA/DDS/10k844/scan_divf_sinx2/singt4.vhd" 13 -1 0 } }  } 0}  } { { "E:/EDA/DDS/10k844/scan_divf_sinx2/db/scan_divf_sinx2_cmp.qrpt" "" { Report "E:/EDA/DDS/10k844/scan_divf_sinx2/db/scan_divf_sinx2_cmp.qrpt" Compiler "scan_divf_sinx2" "UNKNOWN" "V1" "E:/EDA/DDS/10k844/scan_divf_sinx2/db/scan_divf_sinx2.quartus_db" { Floorplan "E:/EDA/DDS/10k844/scan_divf_sinx2/" "" "9.000 ns" { singt4:u3|q[2] singt4:u3|lpm_add_sub:add_rtl_2|addcore:adder|a_csnbuffer:result_node|cout[2] singt4:u3|lpm_add_sub:add_rtl_2|addcore:adder|a_csnbuffer:result_node|cout[3] singt4:u3|lpm_add_sub:add_rtl_2|addcore:adder|a_csnbuffer:result_node|cout[4] singt4:u3|lpm_add_sub:add_rtl_2|addcore:adder|a_csnbuffer:result_node|cout[5] singt4:u3|lpm_add_sub:add_rtl_2|addcore:adder|unreg_res_node[6] singt4:u3|q[6] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "9.000 ns" { singt4:u3|q[2] singt4:u3|lpm_add_sub:add_rtl_2|addcore:adder|a_csnbuffer:result_node|cout[2] singt4:u3|lpm_add_sub:add_rtl_2|addcore:adder|a_csnbuffer:result_node|cout[3] singt4:u3|lpm_add_sub:add_rtl_2|addcore:adder|a_csnbuffer:result_node|cout[4] singt4:u3|lpm_add_sub:add_rtl_2|addcore:adder|a_csnbuffer:result_node|cout[5] singt4:u3|lpm_add_sub:add_rtl_2|addcore:adder|unreg_res_node[6] singt4:u3|q[6] } { 0.000ns 2.200ns 0.000ns 0.000ns 0.000ns 0.000ns 2.200ns } { 0.000ns 1.200ns 0.300ns 0.300ns 0.300ns 1.300ns 1.200ns } } } { "E:/EDA/DDS/10k844/scan_divf_sinx2/db/scan_divf_sinx2_cmp.qrpt" "" { Report "E:/EDA/DDS/10k844/scan_divf_sinx2/db/scan_divf_sinx2_cmp.qrpt" Compiler "scan_divf_sinx2" "UNKNOWN" "V1" "E:/EDA/DDS/10k844/scan_divf_sinx2/db/scan_divf_sinx2.quartus_db" { Floorplan "E:/EDA/DDS/10k844/scan_divf_sinx2/" "" "10.900 ns" { clock divf:u2|COUT singt4:u3|q[6] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "10.900 ns" { clock clock~out divf:u2|COUT singt4:u3|q[6] } { 0.000ns 0.000ns 2.500ns 4.500ns } { 0.000ns 2.800ns 1.100ns 0.000ns } } } { "E:/EDA/DDS/10k844/scan_divf_sinx2/db/scan_divf_sinx2_cmp.qrpt" "" { Report "E:/EDA/DDS/10k844/scan_divf_sinx2/db/scan_divf_sinx2_cmp.qrpt" Compiler "scan_divf_sinx2" "UNKNOWN" "V1" "E:/EDA/DDS/10k844/scan_divf_sinx2/db/scan_divf_sinx2.quartus_db" { Floorplan "E:/EDA/DDS/10k844/scan_divf_sinx2/" "" "10.900 ns" { clock divf:u2|COUT singt4:u3|q[2] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "10.900 ns" { clock clock~out divf:u2|COUT singt4:u3|q[2] } { 0.000ns 0.000ns 2.500ns 4.500ns } { 0.000ns 2.800ns 1.100ns 0.000ns } } }  } 0}
{ "Info" "ITDB_TSU_RESULT" "SCANCNT4B:u1\|lpm_counter:CNT4_rtl_1\|alt_counter_f10ke:wysi_counter\|q\[3\] enable clock 3.300 ns register " "Info: tsu for register \"SCANCNT4B:u1\|lpm_counter:CNT4_rtl_1\|alt_counter_f10ke:wysi_counter\|q\[3\]\" (data pin = \"enable\", clock pin = \"clock\") is 3.300 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.100 ns + Longest pin register " "Info: + Longest pin to register delay is 6.100 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.800 ns) 2.800 ns enable 1 PIN PIN_2 14 " "Info: 1: + IC(0.000 ns) + CELL(2.800 ns) = 2.800 ns; Loc. = PIN_2; Fanout = 14; PIN Node = 'enable'" {  } { { "E:/EDA/DDS/10k844/scan_divf_sinx2/db/scan_divf_sinx2_cmp.qrpt" "" { Report "E:/EDA/DDS/10k844/scan_divf_sinx2/db/scan_divf_sinx2_cmp.qrpt" Compiler "scan_divf_sinx2" "UNKNOWN" "V1" "E:/EDA/DDS/10k844/scan_divf_sinx2/db/scan_divf_sinx2.quartus_db" { Floorplan "E:/EDA/DDS/10k844/scan_divf_sinx2/" "" "" { enable } "NODE_NAME" } "" } } { "scan_divf_sinx2.vhd" "" { Text "E:/EDA/DDS/10k844/scan_divf_sinx2/scan_divf_sinx2.vhd" 6 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.600 ns) + CELL(1.700 ns) 6.100 ns SCANCNT4B:u1\|lpm_counter:CNT4_rtl_1\|alt_counter_f10ke:wysi_counter\|q\[3\] 2 REG LC8_C11 2 " "Info: 2: + IC(1.600 ns) + CELL(1.700 ns) = 6.100 ns; Loc. = LC8_C11; Fanout = 2; REG Node = 'SCANCNT4B:u1\|lpm_counter:CNT4_rtl_1\|alt_counter_f10ke:wysi_counter\|q\[3\]'" {  } { { "E:/EDA/DDS/10k844/scan_divf_sinx2/db/scan_divf_sinx2_cmp.qrpt" "" { Report "E:/EDA/DDS/10k844/scan_divf_sinx2/db/scan_divf_sinx2_cmp.qrpt" Compiler "scan_divf_sinx2" "UNKNOWN" "V1" "E:/EDA/DDS/10k844/scan_divf_sinx2/db/scan_divf_sinx2.quartus_db" { Floorplan "E:/EDA/DDS/10k844/scan_divf_sinx2/" "" "3.300 ns" { enable SCANCNT4B:u1|lpm_counter:CNT4_rtl_1|alt_counter_f10ke:wysi_counter|q[3] } "NODE_NAME" } "" } } { "alt_counter_f10ke.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/alt_counter_f10ke.tdf" 271 2 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.500 ns 73.77 % " "Info: Total cell delay = 4.500 ns ( 73.77 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.600 ns 26.23 % " "Info: Total interconnect delay = 1.600 ns ( 26.23 % )" {  } {  } 0}  } { { "E:/EDA/DDS/10k844/scan_divf_sinx2/db/scan_divf_sinx2_cmp.qrpt" "" { Report "E:/EDA/DDS/10k844/scan_divf_sinx2/db/scan_divf_sinx2_cmp.qrpt" Compiler "scan_divf_sinx2" "UNKNOWN" "V1" "E:/EDA/DDS/10k844/scan_divf_sinx2/db/scan_divf_sinx2.quartus_db" { Floorplan "E:/EDA/DDS/10k844/scan_divf_sinx2/" "" "6.100 ns" { enable SCANCNT4B:u1|lpm_counter:CNT4_rtl_1|alt_counter_f10ke:wysi_counter|q[3] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "6.100 ns" { enable enable~out SCANCNT4B:u1|lpm_counter:CNT4_rtl_1|alt_counter_f10ke:wysi_counter|q[3] } { 0.000ns 0.000ns 1.600ns } { 0.000ns 2.800ns 1.700ns } } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "2.500 ns + " "Info: + Micro setup delay of destination is 2.500 ns" {  } { { "alt_counter_f10ke.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/alt_counter_f10ke.tdf" 271 2 0 } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock destination 5.300 ns - Shortest register " "Info: - Shortest clock path from clock \"clock\" to destination register is 5.300 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.800 ns) 2.800 ns clock 1 CLK PIN_43 15 " "Info: 1: + IC(0.000 ns) + CELL(2.800 ns) = 2.800 ns; Loc. = PIN_43; Fanout = 15; CLK Node = 'clock'" {  } { { "E:/EDA/DDS/10k844/scan_divf_sinx2/db/scan_divf_sinx2_cmp.qrpt" "" { Report "E:/EDA/DDS/10k844/scan_divf_sinx2/db/scan_divf_sinx2_cmp.qrpt" Compiler "scan_divf_sinx2" "UNKNOWN" "V1" "E:/EDA/DDS/10k844/scan_divf_sinx2/db/scan_divf_sinx2.quartus_db" { Floorplan "E:/EDA/DDS/10k844/scan_divf_sinx2/" "" "" { clock } "NODE_NAME" } "" } } { "scan_divf_sinx2.vhd" "" { Text "E:/EDA/DDS/10k844/scan_divf_sinx2/scan_divf_sinx2.vhd" 6 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.500 ns) + CELL(0.000 ns) 5.300 ns SCANCNT4B:u1\|lpm_counter:CNT4_rtl_1\|alt_counter_f10ke:wysi_counter\|q\[3\] 2 REG LC8_C11 2 " "Info: 2: + IC(2.500 ns) + CELL(0.000 ns) = 5.300 ns; Loc. = LC8_C11; Fanout = 2; REG Node = 'SCANCNT4B:u1\|lpm_counter:CNT4_rtl_1\|alt_counter_f10ke:wysi_counter\|q\[3\]'" {  } { { "E:/EDA/DDS/10k844/scan_divf_sinx2/db/scan_divf_sinx2_cmp.qrpt" "" { Report "E:/EDA/DDS/10k844/scan_divf_sinx2/db/scan_divf_sinx2_cmp.qrpt" Compiler "scan_divf_sinx2" "UNKNOWN" "V1" "E:/EDA/DDS/10k844/scan_divf_sinx2/db/scan_divf_sinx2.quartus_db" { Floorplan "E:/EDA/DDS/10k844/scan_divf_sinx2/" "" "2.500 ns" { clock SCANCNT4B:u1|lpm_counter:CNT4_rtl_1|alt_counter_f10ke:wysi_counter|q[3] } "NODE_NAME" } "" } } { "alt_counter_f10ke.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/alt_counter_f10ke.tdf" 271 2 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.800 ns 52.83 % " "Info: Total cell delay = 2.800 ns ( 52.83 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.500 ns 47.17 % " "Info: Total interconnect delay = 2.500 ns ( 47.17 % )" {  } {  } 0}  } { { "E:/EDA/DDS/10k844/scan_divf_sinx2/db/scan_divf_sinx2_cmp.qrpt" "" { Report "E:/EDA/DDS/10k844/scan_divf_sinx2/db/scan_divf_sinx2_cmp.qrpt" Compiler "scan_divf_sinx2" "UNKNOWN" "V1" "E:/EDA/DDS/10k844/scan_divf_sinx2/db/scan_divf_sinx2.quartus_db" { Floorplan "E:/EDA/DDS/10k844/scan_divf_sinx2/" "" "5.300 ns" { clock SCANCNT4B:u1|lpm_counter:CNT4_rtl_1|alt_counter_f10ke:wysi_counter|q[3] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "5.300 ns" { clock clock~out SCANCNT4B:u1|lpm_counter:CNT4_rtl_1|alt_counter_f10ke:wysi_counter|q[3] } { 0.000ns 0.000ns 2.500ns } { 0.000ns 2.800ns 0.000ns } } }  } 0}  } { { "E:/EDA/DDS/10k844/scan_divf_sinx2/db/scan_divf_sinx2_cmp.qrpt" "" { Report "E:/EDA/DDS/10k844/scan_divf_sinx2/db/scan_divf_sinx2_cmp.qrpt" Compiler "scan_divf_sinx2" "UNKNOWN" "V1" "E:/EDA/DDS/10k844/scan_divf_sinx2/db/scan_divf_sinx2.quartus_db" { Floorplan "E:/EDA/DDS/10k844/scan_divf_sinx2/" "" "6.100 ns" { enable SCANCNT4B:u1|lpm_counter:CNT4_rtl_1|alt_counter_f10ke:wysi_counter|q[3] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "6.100 ns" { enable enable~out SCANCNT4B:u1|lpm_counter:CNT4_rtl_1|alt_counter_f10ke:wysi_counter|q[3] } { 0.000ns 0.000ns 1.600ns } { 0.000ns 2.800ns 1.700ns } } } { "E:/EDA/DDS/10k844/scan_divf_sinx2/db/scan_divf_sinx2_cmp.qrpt" "" { Report "E:/EDA/DDS/10k844/scan_divf_sinx2/db/scan_divf_sinx2_cmp.qrpt" Compiler "scan_divf_sinx2" "UNKNOWN" "V1" "E:/EDA/DDS/10k844/scan_divf_sinx2/db/scan_divf_sinx2.quartus_db" { Floorplan "E:/EDA/DDS/10k844/scan_divf_sinx2/" "" "5.300 ns" { clock SCANCNT4B:u1|lpm_counter:CNT4_rtl_1|alt_counter_f10ke:wysi_counter|q[3] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "5.300 ns" { clock clock~out SCANCNT4B:u1|lpm_counter:CNT4_rtl_1|alt_counter_f10ke:wysi_counter|q[3] } { 0.000ns 0.000ns 2.500ns } { 0.000ns 2.800ns 0.000ns } } }  } 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clock da_data\[0\] singt4:u3\|q\[1\] 38.000 ns register " "Info: tco from clock \"clock\" to destination pin \"da_data\[0\]\" through register \"singt4:u3\|q\[1\]\" is 38.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock source 10.900 ns + Longest register " "Info: + Longest clock path from clock \"clock\" to source register is 10.900 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.800 ns) 2.800 ns clock 1 CLK PIN_43 15 " "Info: 1: + IC(0.000 ns) + CELL(2.800 ns) = 2.800 ns; Loc. = PIN_43; Fanout = 15; CLK Node = 'clock'" {  } { { "E:/EDA/DDS/10k844/scan_divf_sinx2/db/scan_divf_sinx2_cmp.qrpt" "" { Report "E:/EDA/DDS/10k844/scan_divf_sinx2/db/scan_divf_sinx2_cmp.qrpt" Compiler "scan_divf_sinx2" "UNKNOWN" "V1" "E:/EDA/DDS/10k844/scan_divf_sinx2/db/scan_divf_sinx2.quartus_db" { Floorplan "E:/EDA/DDS/10k844/scan_divf_sinx2/" "" "" { clock } "NODE_NAME" } "" } } { "scan_divf_sinx2.vhd" "" { Text "E:/EDA/DDS/10k844/scan_divf_sinx2/scan_divf_sinx2.vhd" 6 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.500 ns) + CELL(1.100 ns) 6.400 ns divf:u2\|COUT 2 REG LC1_C6 8 " "Info: 2: + IC(2.500 ns) + CELL(1.100 ns) = 6.400 ns; Loc. = LC1_C6; Fanout = 8; REG Node = 'divf:u2\|COUT'" {  } { { "E:/EDA/DDS/10k844/scan_divf_sinx2/db/scan_divf_sinx2_cmp.qrpt" "" { Report "E:/EDA/DDS/10k844/scan_divf_sinx2/db/scan_divf_sinx2_cmp.qrpt" Compiler "scan_divf_sinx2" "UNKNOWN" "V1" "E:/EDA/DDS/10k844/scan_divf_sinx2/db/scan_divf_sinx2.quartus_db" { Floorplan "E:/EDA/DDS/10k844/scan_divf_sinx2/" "" "3.600 ns" { clock divf:u2|COUT } "NODE_NAME" } "" } } { "divf.vhd" "" { Text "E:/EDA/DDS/10k844/scan_divf_sinx2/divf.vhd" 9 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(4.500 ns) + CELL(0.000 ns) 10.900 ns singt4:u3\|q\[1\] 3 REG LC8_C14 46 " "Info: 3: + IC(4.500 ns) + CELL(0.000 ns) = 10.900 ns; Loc. = LC8_C14; Fanout = 46; REG Node = 'singt4:u3\|q\[1\]'" {  } { { "E:/EDA/DDS/10k844/scan_divf_sinx2/db/scan_divf_sinx2_cmp.qrpt" "" { Report "E:/EDA/DDS/10k844/scan_divf_sinx2/db/scan_divf_sinx2_cmp.qrpt" Compiler "scan_divf_sinx2" "UNKNOWN" "V1" "E:/EDA/DDS/10k844/scan_divf_sinx2/db/scan_divf_sinx2.quartus_db" { Floorplan "E:/EDA/DDS/10k844/scan_divf_sinx2/" "" "4.500 ns" { divf:u2|COUT singt4:u3|q[1] } "NODE_NAME" } "" } } { "singt4.vhd" "" { Text "E:/EDA/DDS/10k844/scan_divf_sinx2/singt4.vhd" 13 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.900 ns 35.78 % " "Info: Total cell delay = 3.900 ns ( 35.78 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "7.000 ns 64.22 % " "Info: Total interconnect delay = 7.000 ns ( 64.22 % )" {  } {  } 0}  } { { "E:/EDA/DDS/10k844/scan_divf_sinx2/db/scan_divf_sinx2_cmp.qrpt" "" { Report "E:/EDA/DDS/10k844/scan_divf_sinx2/db/scan_divf_sinx2_cmp.qrpt" Compiler "scan_divf_sinx2" "UNKNOWN" "V1" "E:/EDA/DDS/10k844/scan_divf_sinx2/db/scan_divf_sinx2.quartus_db" { Floorplan "E:/EDA/DDS/10k844/scan_divf_sinx2/" "" "10.900 ns" { clock divf:u2|COUT singt4:u3|q[1] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "10.900 ns" { clock clock~out divf:u2|COUT singt4:u3|q[1] } { 0.000ns 0.000ns 2.500ns 4.500ns } { 0.000ns 2.800ns 1.100ns 0.000ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.100 ns + " "Info: + Micro clock to output delay of source is 1.100 ns" {  } { { "singt4.vhd" "" { Text "E:/EDA/DDS/10k844/scan_divf_sinx2/singt4.vhd" 13 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "26.000 ns + Longest register pin " "Info: + Longest register to pin delay is 26.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns singt4:u3\|q\[1\] 1 REG LC8_C14 46 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC8_C14; Fanout = 46; REG Node = 'singt4:u3\|q\[1\]'" {  } { { "E:/EDA/DDS/10k844/scan_divf_sinx2/db/scan_divf_sinx2_cmp.qrpt" "" { Report "E:/EDA/DDS/10k844/scan_divf_sinx2/db/scan_divf_sinx2_cmp.qrpt" Compiler "scan_divf_sinx2" "UNKNOWN" "V1" "E:/EDA/DDS/10k844/scan_divf_sinx2/db/scan_divf_sinx2.quartus_db" { Floorplan "E:/EDA/DDS/10k844/scan_divf_sinx2/" "" "" { singt4:u3|q[1] } "NODE_NAME" } "" } } { "singt4.vhd" "" { Text "E:/EDA/DDS/10k844/scan_divf_sinx2/singt4.vhd" 13 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(4.600 ns) + CELL(2.300 ns) 6.900 ns singt4:u3\|dout\[0\]~652 2 COMB LC4_A9 1 " "Info: 2: + IC(4.600 ns) + CELL(2.300 ns) = 6.900 ns; Loc. = LC4_A9; Fanout = 1; COMB Node = 'singt4:u3\|dout\[0\]~652'" {  } { { "E:/EDA/DDS/10k844/scan_divf_sinx2/db/scan_divf_sinx2_cmp.qrpt" "" { Report "E:/EDA/DDS/10k844/scan_divf_sinx2/db/scan_divf_sinx2_cmp.qrpt" Compiler "scan_divf_sinx2" "UNKNOWN" "V1" "E:/EDA/DDS/10k844/scan_divf_sinx2/db/scan_divf_sinx2.quartus_db" { Floorplan "E:/EDA/DDS/10k844/scan_divf_sinx2/" "" "6.900 ns" { singt4:u3|q[1] singt4:u3|dout[0]~652 } "NODE_NAME" } "" } } { "singt4.vhd" "" { Text "E:/EDA/DDS/10k844/scan_divf_sinx2/singt4.vhd" 8 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.600 ns) + CELL(2.300 ns) 9.800 ns singt4:u3\|dout\[0\]~653 3 COMB LC2_A9 1 " "Info: 3: + IC(0.600 ns) + CELL(2.300 ns) = 9.800 ns; Loc. = LC2_A9; Fanout = 1; COMB Node = 'singt4:u3\|dout\[0\]~653'" {  } { { "E:/EDA/DDS/10k844/scan_divf_sinx2/db/scan_divf_sinx2_cmp.qrpt" "" { Report "E:/EDA/DDS/10k844/scan_divf_sinx2/db/scan_divf_sinx2_cmp.qrpt" Compiler "scan_divf_sinx2" "UNKNOWN" "V1" "E:/EDA/DDS/10k844/scan_divf_sinx2/db/scan_divf_sinx2.quartus_db" { Floorplan "E:/EDA/DDS/10k844/scan_divf_sinx2/" "" "2.900 ns" { singt4:u3|dout[0]~652 singt4:u3|dout[0]~653 } "NODE_NAME" } "" } } { "singt4.vhd" "" { Text "E:/EDA/DDS/10k844/scan_divf_sinx2/singt4.vhd" 8 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.700 ns) + CELL(2.300 ns) 14.800 ns singt4:u3\|dout\[0\]~655 4 COMB LC5_A17 1 " "Info: 4: + IC(2.700 ns) + CELL(2.300 ns) = 14.800 ns; Loc. = LC5_A17; Fanout = 1; COMB Node = 'singt4:u3\|dout\[0\]~655'" {  } { { "E:/EDA/DDS/10k844/scan_divf_sinx2/db/scan_divf_sinx2_cmp.qrpt" "" { Report "E:/EDA/DDS/10k844/scan_divf_sinx2/db/scan_divf_sinx2_cmp.qrpt" Compiler "scan_divf_sinx2" "UNKNOWN" "V1" "E:/EDA/DDS/10k844/scan_divf_sinx2/db/scan_divf_sinx2.quartus_db" { Floorplan "E:/EDA/DDS/10k844/scan_divf_sinx2/" "" "5.000 ns" { singt4:u3|dout[0]~653 singt4:u3|dout[0]~655 } "NODE_NAME" } "" } } { "singt4.vhd" "" { Text "E:/EDA/DDS/10k844/scan_divf_sinx2/singt4.vhd" 8 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.200 ns) + CELL(2.300 ns) 19.300 ns singt4:u3\|dout\[0\]~656 5 COMB LC5_A21 1 " "Info: 5: + IC(2.200 ns) + CELL(2.300 ns) = 19.300 ns; Loc. = LC5_A21; Fanout = 1; COMB Node = 'singt4:u3\|dout\[0\]~656'" {  } { { "E:/EDA/DDS/10k844/scan_divf_sinx2/db/scan_divf_sinx2_cmp.qrpt" "" { Report "E:/EDA/DDS/10k844/scan_divf_sinx2/db/scan_divf_sinx2_cmp.qrpt" Compiler "scan_divf_sinx2" "UNKNOWN" "V1" "E:/EDA/DDS/10k844/scan_divf_sinx2/db/scan_divf_sinx2.quartus_db" { Floorplan "E:/EDA/DDS/10k844/scan_divf_sinx2/" "" "4.500 ns" { singt4:u3|dout[0]~655 singt4:u3|dout[0]~656 } "NODE_NAME" } "" } } { "singt4.vhd" "" { Text "E:/EDA/DDS/10k844/scan_divf_sinx2/singt4.vhd" 8 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.600 ns) + CELL(5.100 ns) 26.000 ns da_data\[0\] 6 PIN PIN_70 0 " "Info: 6: + IC(1.600 ns) + CELL(5.100 ns) = 26.000 ns; Loc. = PIN_70; Fanout = 0; PIN Node = 'da_data\[0\]'" {  } { { "E:/EDA/DDS/10k844/scan_divf_sinx2/db/scan_divf_sinx2_cmp.qrpt" "" { Report "E:/EDA/DDS/10k844/scan_divf_sinx2/db/scan_divf_sinx2_cmp.qrpt" Compiler "scan_divf_sinx2" "UNKNOWN" "V1" "E:/EDA/DDS/10k844/scan_divf_sinx2/db/scan_divf_sinx2.quartus_db" { Floorplan "E:/EDA/DDS/10k844/scan_divf_sinx2/" "" "6.700 ns" { singt4:u3|dout[0]~656 da_data[0] } "NODE_NAME" } "" } } { "scan_divf_sinx2.vhd" "" { Text "E:/EDA/DDS/10k844/scan_divf_sinx2/scan_divf_sinx2.vhd" 8 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "14.300 ns 55.00 % " "Info: Total cell delay = 14.300 ns ( 55.00 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "11.700 ns 45.00 % " "Info: Total interconnect delay = 11.700 ns ( 45.00 % )" {  } {  } 0}  } { { "E:/EDA/DDS/10k844/scan_divf_sinx2/db/scan_divf_sinx2_cmp.qrpt" "" { Report "E:/EDA/DDS/10k844/scan_divf_sinx2/db/scan_divf_sinx2_cmp.qrpt" Compiler "scan_divf_sinx2" "UNKNOWN" "V1" "E:/EDA/DDS/10k844/scan_divf_sinx2/db/scan_divf_sinx2.quartus_db" { Floorplan "E:/EDA/DDS/10k844/scan_divf_sinx2/" "" "26.000 ns" { singt4:u3|q[1] singt4:u3|dout[0]~652 singt4:u3|dout[0]~653 singt4:u3|dout[0]~655 singt4:u3|dout[0]~656 da_data[0] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "26.000 ns" { singt4:u3|q[1] singt4:u3|dout[0]~652 singt4:u3|dout[0]~653 singt4:u3|dout[0]~655 singt4:u3|dout[0]~656 da_data[0] } { 0.000ns 4.600ns 0.600ns 2.700ns 2.200ns 1.600ns } { 0.000ns 2.300ns 2.300ns 2.300ns 2.300ns 5.100ns } } }  } 0}  } { { "E:/EDA/DDS/10k844/scan_divf_sinx2/db/scan_divf_sinx2_cmp.qrpt" "" { Report "E:/EDA/DDS/10k844/scan_divf_sinx2/db/scan_divf_sinx2_cmp.qrpt" Compiler "scan_divf_sinx2" "UNKNOWN" "V1" "E:/EDA/DDS/10k844/scan_divf_sinx2/db/scan_divf_sinx2.quartus_db" { Floorplan "E:/EDA/DDS/10k844/scan_divf_sinx2/" "" "10.900 ns" { clock divf:u2|COUT singt4:u3|q[1] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "10.900 ns" { clock clock~out divf:u2|COUT singt4:u3|q[1] } { 0.000ns 0.000ns 2.500ns 4.500ns } { 0.000ns 2.800ns 1.100ns 0.000ns } } } { "E:/EDA/DDS/10k844/scan_divf_sinx2/db/scan_divf_sinx2_cmp.qrpt" "" { Report "E:/EDA/DDS/10k844/scan_divf_sinx2/db/scan_divf_sinx2_cmp.qrpt" Compiler "scan_divf_sinx2" "UNKNOWN" "V1" "E:/EDA/DDS/10k844/scan_divf_sinx2/db/scan_divf_sinx2.quartus_db" { Floorplan "E:/EDA/DDS/10k844/scan_divf_sinx2/" "" "26.000 ns" { singt4:u3|q[1] singt4:u3|dout[0]~652 singt4:u3|dout[0]~653 singt4:u3|dout[0]~655 singt4:u3|dout[0]~656 da_data[0] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "26.000 ns" { singt4:u3|q[1] singt4:u3|dout[0]~652 singt4:u3|dout[0]~653 singt4:u3|dout[0]~655 singt4:u3|dout[0]~656 da_data[0] } { 0.000ns 4.600ns 0.600ns 2.700ns 2.200ns 1.600ns } { 0.000ns 2.300ns 2.300ns 2.300ns 2.300ns 5.100ns } } }  } 0}