singt4.tan.qmsg

来自「在EDA开发软件QuartusII上利用VHDL语言实现DDS信号发生器」· QMSG 代码 · 共 10 行 · 第 1/2 页

{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clk " "Info: Assuming node \"clk\" is an undefined clock" {  } { { "singt4.vhd" "" { Text "E:/EDA/DDS/10k844/singt4/singt4.vhd" 6 -1 0 } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "clk" } } } }  } 0}  } {  } 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register q\[2\] register q\[6\] 79.37 MHz 12.6 ns Internal " "Info: Clock \"clk\" has Internal fmax of 79.37 MHz between source register \"q\[2\]\" and destination register \"q\[6\]\" (period= 12.6 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "9.000 ns + Longest register register " "Info: + Longest register to register delay is 9.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns q\[2\] 1 REG LC4_A13 49 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC4_A13; Fanout = 49; REG Node = 'q\[2\]'" {  } { { "E:/EDA/DDS/10k844/singt4/db/singt4_cmp.qrpt" "" { Report "E:/EDA/DDS/10k844/singt4/db/singt4_cmp.qrpt" Compiler "singt4" "UNKNOWN" "V1" "E:/EDA/DDS/10k844/singt4/db/singt4.quartus_db" { Floorplan "E:/EDA/DDS/10k844/singt4/" "" "" { q[2] } "NODE_NAME" } "" } } { "singt4.vhd" "" { Text "E:/EDA/DDS/10k844/singt4/singt4.vhd" 13 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.200 ns) + CELL(1.200 ns) 3.400 ns lpm_add_sub:add_rtl_0\|addcore:adder\|a_csnbuffer:result_node\|cout\[2\] 2 COMB LC3_A14 2 " "Info: 2: + IC(2.200 ns) + CELL(1.200 ns) = 3.400 ns; Loc. = LC3_A14; Fanout = 2; COMB Node = 'lpm_add_sub:add_rtl_0\|addcore:adder\|a_csnbuffer:result_node\|cout\[2\]'" {  } { { "E:/EDA/DDS/10k844/singt4/db/singt4_cmp.qrpt" "" { Report "E:/EDA/DDS/10k844/singt4/db/singt4_cmp.qrpt" Compiler "singt4" "UNKNOWN" "V1" "E:/EDA/DDS/10k844/singt4/db/singt4.quartus_db" { Floorplan "E:/EDA/DDS/10k844/singt4/" "" "3.400 ns" { q[2] lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cout[2] } "NODE_NAME" } "" } } { "a_csnbuffer.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/a_csnbuffer.tdf" 18 2 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.300 ns) 3.700 ns lpm_add_sub:add_rtl_0\|addcore:adder\|a_csnbuffer:result_node\|cout\[3\] 3 COMB LC4_A14 2 " "Info: 3: + IC(0.000 ns) + CELL(0.300 ns) = 3.700 ns; Loc. = LC4_A14; Fanout = 2; COMB Node = 'lpm_add_sub:add_rtl_0\|addcore:adder\|a_csnbuffer:result_node\|cout\[3\]'" {  } { { "E:/EDA/DDS/10k844/singt4/db/singt4_cmp.qrpt" "" { Report "E:/EDA/DDS/10k844/singt4/db/singt4_cmp.qrpt" Compiler "singt4" "UNKNOWN" "V1" "E:/EDA/DDS/10k844/singt4/db/singt4.quartus_db" { Floorplan "E:/EDA/DDS/10k844/singt4/" "" "0.300 ns" { lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cout[2] lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cout[3] } "NODE_NAME" } "" } } { "a_csnbuffer.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/a_csnbuffer.tdf" 18 2 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.300 ns) 4.000 ns lpm_add_sub:add_rtl_0\|addcore:adder\|a_csnbuffer:result_node\|cout\[4\] 4 COMB LC5_A14 2 " "Info: 4: + IC(0.000 ns) + CELL(0.300 ns) = 4.000 ns; Loc. = LC5_A14; Fanout = 2; COMB Node = 'lpm_add_sub:add_rtl_0\|addcore:adder\|a_csnbuffer:result_node\|cout\[4\]'" {  } { { "E:/EDA/DDS/10k844/singt4/db/singt4_cmp.qrpt" "" { Report "E:/EDA/DDS/10k844/singt4/db/singt4_cmp.qrpt" Compiler "singt4" "UNKNOWN" "V1" "E:/EDA/DDS/10k844/singt4/db/singt4.quartus_db" { Floorplan "E:/EDA/DDS/10k844/singt4/" "" "0.300 ns" { lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cout[3] lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cout[4] } "NODE_NAME" } "" } } { "a_csnbuffer.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/a_csnbuffer.tdf" 18 2 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.300 ns) 4.300 ns lpm_add_sub:add_rtl_0\|addcore:adder\|a_csnbuffer:result_node\|cout\[5\] 5 COMB LC6_A14 1 " "Info: 5: + IC(0.000 ns) + CELL(0.300 ns) = 4.300 ns; Loc. = LC6_A14; Fanout = 1; COMB Node = 'lpm_add_sub:add_rtl_0\|addcore:adder\|a_csnbuffer:result_node\|cout\[5\]'" {  } { { "E:/EDA/DDS/10k844/singt4/db/singt4_cmp.qrpt" "" { Report "E:/EDA/DDS/10k844/singt4/db/singt4_cmp.qrpt" Compiler "singt4" "UNKNOWN" "V1" "E:/EDA/DDS/10k844/singt4/db/singt4.quartus_db" { Floorplan "E:/EDA/DDS/10k844/singt4/" "" "0.300 ns" { lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cout[4] lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cout[5] } "NODE_NAME" } "" } } { "a_csnbuffer.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/a_csnbuffer.tdf" 18 2 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.300 ns) 5.600 ns lpm_add_sub:add_rtl_0\|addcore:adder\|unreg_res_node\[6\] 6 COMB LC7_A14 1 " "Info: 6: + IC(0.000 ns) + CELL(1.300 ns) = 5.600 ns; Loc. = LC7_A14; Fanout = 1; COMB Node = 'lpm_add_sub:add_rtl_0\|addcore:adder\|unreg_res_node\[6\]'" {  } { { "E:/EDA/DDS/10k844/singt4/db/singt4_cmp.qrpt" "" { Report "E:/EDA/DDS/10k844/singt4/db/singt4_cmp.qrpt" Compiler "singt4" "UNKNOWN" "V1" "E:/EDA/DDS/10k844/singt4/db/singt4.quartus_db" { Floorplan "E:/EDA/DDS/10k844/singt4/" "" "1.300 ns" { lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cout[5] lpm_add_sub:add_rtl_0|addcore:adder|unreg_res_node[6] } "NODE_NAME" } "" } } { "addcore.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/addcore.tdf" 95 16 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.200 ns) + CELL(1.200 ns) 9.000 ns q\[6\] 7 REG LC6_A13 10 " "Info: 7: + IC(2.200 ns) + CELL(1.200 ns) = 9.000 ns; Loc. = LC6_A13; Fanout = 10; REG Node = 'q\[6\]'" {  } { { "E:/EDA/DDS/10k844/singt4/db/singt4_cmp.qrpt" "" { Report "E:/EDA/DDS/10k844/singt4/db/singt4_cmp.qrpt" Compiler "singt4" "UNKNOWN" "V1" "E:/EDA/DDS/10k844/singt4/db/singt4.quartus_db" { Floorplan "E:/EDA/DDS/10k844/singt4/" "" "3.400 ns" { lpm_add_sub:add_rtl_0|addcore:adder|unreg_res_node[6] q[6] } "NODE_NAME" } "" } } { "singt4.vhd" "" { Text "E:/EDA/DDS/10k844/singt4/singt4.vhd" 13 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.600 ns 51.11 % " "Info: Total cell delay = 4.600 ns ( 51.11 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.400 ns 48.89 % " "Info: Total interconnect delay = 4.400 ns ( 48.89 % )" {  } {  } 0}  } { { "E:/EDA/DDS/10k844/singt4/db/singt4_cmp.qrpt" "" { Report "E:/EDA/DDS/10k844/singt4/db/singt4_cmp.qrpt" Compiler "singt4" "UNKNOWN" "V1" "E:/EDA/DDS/10k844/singt4/db/singt4.quartus_db" { Floorplan "E:/EDA/DDS/10k844/singt4/" "" "9.000 ns" { q[2] lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cout[2] lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cout[3] lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cout[4] lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cout[5] lpm_add_sub:add_rtl_0|addcore:adder|unreg_res_node[6] q[6] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "9.000 ns" { q[2] lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cout[2] lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cout[3] lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cout[4] lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cout[5] lpm_add_sub:add_rtl_0|addcore:adder|unreg_res_node[6] q[6] } { 0.000ns 2.200ns 0.000ns 0.000ns 0.000ns 0.000ns 2.200ns } { 0.000ns 1.200ns 0.300ns 0.300ns 0.300ns 1.300ns 1.200ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 5.300 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 5.300 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.800 ns) 2.800 ns clk 1 CLK PIN_43 8 " "Info: 1: + IC(0.000 ns) + CELL(2.800 ns) = 2.800 ns; Loc. = PIN_43; Fanout = 8; CLK Node = 'clk'" {  } { { "E:/EDA/DDS/10k844/singt4/db/singt4_cmp.qrpt" "" { Report "E:/EDA/DDS/10k844/singt4/db/singt4_cmp.qrpt" Compiler "singt4" "UNKNOWN" "V1" "E:/EDA/DDS/10k844/singt4/db/singt4.quartus_db" { Floorplan "E:/EDA/DDS/10k844/singt4/" "" "" { clk } "NODE_NAME" } "" } } { "singt4.vhd" "" { Text "E:/EDA/DDS/10k844/singt4/singt4.vhd" 6 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.500 ns) + CELL(0.000 ns) 5.300 ns q\[6\] 2 REG LC6_A13 10 " "Info: 2: + IC(2.500 ns) + CELL(0.000 ns) = 5.300 ns; Loc. = LC6_A13; Fanout = 10; REG Node = 'q\[6\]'" {  } { { "E:/EDA/DDS/10k844/singt4/db/singt4_cmp.qrpt" "" { Report "E:/EDA/DDS/10k844/singt4/db/singt4_cmp.qrpt" Compiler "singt4" "UNKNOWN" "V1" "E:/EDA/DDS/10k844/singt4/db/singt4.quartus_db" { Floorplan "E:/EDA/DDS/10k844/singt4/" "" "2.500 ns" { clk q[6] } "NODE_NAME" } "" } } { "singt4.vhd" "" { Text "E:/EDA/DDS/10k844/singt4/singt4.vhd" 13 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.800 ns 52.83 % " "Info: Total cell delay = 2.800 ns ( 52.83 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.500 ns 47.17 % " "Info: Total interconnect delay = 2.500 ns ( 47.17 % )" {  } {  } 0}  } { { "E:/EDA/DDS/10k844/singt4/db/singt4_cmp.qrpt" "" { Report "E:/EDA/DDS/10k844/singt4/db/singt4_cmp.qrpt" Compiler "singt4" "UNKNOWN" "V1" "E:/EDA/DDS/10k844/singt4/db/singt4.quartus_db" { Floorplan "E:/EDA/DDS/10k844/singt4/" "" "5.300 ns" { clk q[6] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "5.300 ns" { clk clk~out q[6] } { 0.000ns 0.000ns 2.500ns } { 0.000ns 2.800ns 0.000ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 5.300 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 5.300 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.800 ns) 2.800 ns clk 1 CLK PIN_43 8 " "Info: 1: + IC(0.000 ns) + CELL(2.800 ns) = 2.800 ns; Loc. = PIN_43; Fanout = 8; CLK Node = 'clk'" {  } { { "E:/EDA/DDS/10k844/singt4/db/singt4_cmp.qrpt" "" { Report "E:/EDA/DDS/10k844/singt4/db/singt4_cmp.qrpt" Compiler "singt4" "UNKNOWN" "V1" "E:/EDA/DDS/10k844/singt4/db/singt4.quartus_db" { Floorplan "E:/EDA/DDS/10k844/singt4/" "" "" { clk } "NODE_NAME" } "" } } { "singt4.vhd" "" { Text "E:/EDA/DDS/10k844/singt4/singt4.vhd" 6 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.500 ns) + CELL(0.000 ns) 5.300 ns q\[2\] 2 REG LC4_A13 49 " "Info: 2: + IC(2.500 ns) + CELL(0.000 ns) = 5.300 ns; Loc. = LC4_A13; Fanout = 49; REG Node = 'q\[2\]'" {  } { { "E:/EDA/DDS/10k844/singt4/db/singt4_cmp.qrpt" "" { Report "E:/EDA/DDS/10k844/singt4/db/singt4_cmp.qrpt" Compiler "singt4" "UNKNOWN" "V1" "E:/EDA/DDS/10k844/singt4/db/singt4.quartus_db" { Floorplan "E:/EDA/DDS/10k844/singt4/" "" "2.500 ns" { clk q[2] } "NODE_NAME" } "" } } { "singt4.vhd" "" { Text "E:/EDA/DDS/10k844/singt4/singt4.vhd" 13 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.800 ns 52.83 % " "Info: Total cell delay = 2.800 ns ( 52.83 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.500 ns 47.17 % " "Info: Total interconnect delay = 2.500 ns ( 47.17 % )" {  } {  } 0}  } { { "E:/EDA/DDS/10k844/singt4/db/singt4_cmp.qrpt" "" { Report "E:/EDA/DDS/10k844/singt4/db/singt4_cmp.qrpt" Compiler "singt4" "UNKNOWN" "V1" "E:/EDA/DDS/10k844/singt4/db/singt4.quartus_db" { Floorplan "E:/EDA/DDS/10k844/singt4/" "" "5.300 ns" { clk q[2] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "5.300 ns" { clk clk~out q[2] } { 0.000ns 0.000ns 2.500ns } { 0.000ns 2.800ns 0.000ns } } }  } 0}  } { { "E:/EDA/DDS/10k844/singt4/db/singt4_cmp.qrpt" "" { Report "E:/EDA/DDS/10k844/singt4/db/singt4_cmp.qrpt" Compiler "singt4" "UNKNOWN" "V1" "E:/EDA/DDS/10k844/singt4/db/singt4.quartus_db" { Floorplan "E:/EDA/DDS/10k844/singt4/" "" "5.300 ns" { clk q[6] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "5.300 ns" { clk clk~out q[6] } { 0.000ns 0.000ns 2.500ns } { 0.000ns 2.800ns 0.000ns } } } { "E:/EDA/DDS/10k844/singt4/db/singt4_cmp.qrpt" "" { Report "E:/EDA/DDS/10k844/singt4/db/singt4_cmp.qrpt" Compiler "singt4" "UNKNOWN" "V1" "E:/EDA/DDS/10k844/singt4/db/singt4.quartus_db" { Floorplan "E:/EDA/DDS/10k844/singt4/" "" "5.300 ns" { clk q[2] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "5.300 ns" { clk clk~out q[2] } { 0.000ns 0.000ns 2.500ns } { 0.000ns 2.800ns 0.000ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.100 ns + " "Info: + Micro clock to output delay of source is 1.100 ns" {  } { { "singt4.vhd" "" { Text "E:/EDA/DDS/10k844/singt4/singt4.vhd" 13 -1 0 } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "2.500 ns + " "Info: + Micro setup delay of destination is 2.500 ns" {  } { { "singt4.vhd" "" { Text "E:/EDA/DDS/10k844/singt4/singt4.vhd" 13 -1 0 } }  } 0}  } { { "E:/EDA/DDS/10k844/singt4/db/singt4_cmp.qrpt" "" { Report "E:/EDA/DDS/10k844/singt4/db/singt4_cmp.qrpt" Compiler "singt4" "UNKNOWN" "V1" "E:/EDA/DDS/10k844/singt4/db/singt4.quartus_db" { Floorplan "E:/EDA/DDS/10k844/singt4/" "" "9.000 ns" { q[2] lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cout[2] lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cout[3] lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cout[4] lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cout[5] lpm_add_sub:add_rtl_0|addcore:adder|unreg_res_node[6] q[6] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "9.000 ns" { q[2] lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cout[2] lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cout[3] lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cout[4] lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cout[5] lpm_add_sub:add_rtl_0|addcore:adder|unreg_res_node[6] q[6] } { 0.000ns 2.200ns 0.000ns 0.000ns 0.000ns 0.000ns 2.200ns } { 0.000ns 1.200ns 0.300ns 0.300ns 0.300ns 1.300ns 1.200ns } } } { "E:/EDA/DDS/10k844/singt4/db/singt4_cmp.qrpt" "" { Report "E:/EDA/DDS/10k844/singt4/db/singt4_cmp.qrpt" Compiler "singt4" "UNKNOWN" "V1" "E:/EDA/DDS/10k844/singt4/db/singt4.quartus_db" { Floorplan "E:/EDA/DDS/10k844/singt4/" "" "5.300 ns" { clk q[6] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "5.300 ns" { clk clk~out q[6] } { 0.000ns 0.000ns 2.500ns } { 0.000ns 2.800ns 0.000ns } } } { "E:/EDA/DDS/10k844/singt4/db/singt4_cmp.qrpt" "" { Report "E:/EDA/DDS/10k844/singt4/db/singt4_cmp.qrpt" Compiler "singt4" "UNKNOWN" "V1" "E:/EDA/DDS/10k844/singt4/db/singt4.quartus_db" { Floorplan "E:/EDA/DDS/10k844/singt4/" "" "5.300 ns" { clk q[2] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "5.300 ns" { clk clk~out q[2] } { 0.000ns 0.000ns 2.500ns } { 0.000ns 2.800ns 0.000ns } } }  } 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk dout\[3\] q\[2\] 32.900 ns register " "Info: tco from clock \"clk\" to destination pin \"dout\[3\]\" through register \"q\[2\]\" is 32.900 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 5.300 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 5.300 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.800 ns) 2.800 ns clk 1 CLK PIN_43 8 " "Info: 1: + IC(0.000 ns) + CELL(2.800 ns) = 2.800 ns; Loc. = PIN_43; Fanout = 8; CLK Node = 'clk'" {  } { { "E:/EDA/DDS/10k844/singt4/db/singt4_cmp.qrpt" "" { Report "E:/EDA/DDS/10k844/singt4/db/singt4_cmp.qrpt" Compiler "singt4" "UNKNOWN" "V1" "E:/EDA/DDS/10k844/singt4/db/singt4.quartus_db" { Floorplan "E:/EDA/DDS/10k844/singt4/" "" "" { clk } "NODE_NAME" } "" } } { "singt4.vhd" "" { Text "E:/EDA/DDS/10k844/singt4/singt4.vhd" 6 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.500 ns) + CELL(0.000 ns) 5.300 ns q\[2\] 2 REG LC4_A13 49 " "Info: 2: + IC(2.500 ns) + CELL(0.000 ns) = 5.300 ns; Loc. = LC4_A13; Fanout = 49; REG Node = 'q\[2\]'" {  } { { "E:/EDA/DDS/10k844/singt4/db/singt4_cmp.qrpt" "" { Report "E:/EDA/DDS/10k844/singt4/db/singt4_cmp.qrpt" Compiler "singt4" "UNKNOWN" "V1" "E:/EDA/DDS/10k844/singt4/db/singt4.quartus_db" { Floorplan "E:/EDA/DDS/10k844/singt4/" "" "2.500 ns" { clk q[2] } "NODE_NAME" } "" } } { "singt4.vhd" "" { Text "E:/EDA/DDS/10k844/singt4/singt4.vhd" 13 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.800 ns 52.83 % " "Info: Total cell delay = 2.800 ns ( 52.83 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.500 ns 47.17 % " "Info: Total interconnect delay = 2.500 ns ( 47.17 % )" {  } {  } 0}  } { { "E:/EDA/DDS/10k844/singt4/db/singt4_cmp.qrpt" "" { Report "E:/EDA/DDS/10k844/singt4/db/singt4_cmp.qrpt" Compiler "singt4" "UNKNOWN" "V1" "E:/EDA/DDS/10k844/singt4/db/singt4.quartus_db" { Floorplan "E:/EDA/DDS/10k844/singt4/" "" "5.300 ns" { clk q[2] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "5.300 ns" { clk clk~out q[2] } { 0.000ns 0.000ns 2.500ns } { 0.000ns 2.800ns 0.000ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.100 ns + " "Info: + Micro clock to output delay of source is 1.100 ns" {  } { { "singt4.vhd" "" { Text "E:/EDA/DDS/10k844/singt4/singt4.vhd" 13 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "26.500 ns + Longest register pin " "Info: + Longest register to pin delay is 26.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns q\[2\] 1 REG LC4_A13 49 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC4_A13; Fanout = 49; REG Node = 'q\[2\]'" {  } { { "E:/EDA/DDS/10k844/singt4/db/singt4_cmp.qrpt" "" { Report "E:/EDA/DDS/10k844/singt4/db/singt4_cmp.qrpt" Compiler "singt4" "UNKNOWN" "V1" "E:/EDA/DDS/10k844/singt4/db/singt4.quartus_db" { Floorplan "E:/EDA/DDS/10k844/singt4/" "" "" { q[2] } "NODE_NAME" } "" } } { "singt4.vhd" "" { Text "E:/EDA/DDS/10k844/singt4/singt4.vhd" 13 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(4.900 ns) + CELL(2.300 ns) 7.200 ns Mux~693 2 COMB LC4_C7 1 " "Info: 2: + IC(4.900 ns) + CELL(2.300 ns) = 7.200 ns; Loc. = LC4_C7; Fanout = 1; COMB Node = 'Mux~693'" {  } { { "E:/EDA/DDS/10k844/singt4/db/singt4_cmp.qrpt" "" { Report "E:/EDA/DDS/10k844/singt4/db/singt4_cmp.qrpt" Compiler "singt4" "UNKNOWN" "V1" "E:/EDA/DDS/10k844/singt4/db/singt4.quartus_db" { Floorplan "E:/EDA/DDS/10k844/singt4/" "" "7.200 ns" { q[2] Mux~693 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.600 ns) + CELL(2.300 ns) 10.100 ns Mux~694 3 COMB LC1_C7 1 " "Info: 3: + IC(0.600 ns) + CELL(2.300 ns) = 10.100 ns; Loc. = LC1_C7; Fanout = 1; COMB Node = 'Mux~694'" {  } { { "E:/EDA/DDS/10k844/singt4/db/singt4_cmp.qrpt" "" { Report "E:/EDA/DDS/10k844/singt4/db/singt4_cmp.qrpt" Compiler "singt4" "UNKNOWN" "V1" "E:/EDA/DDS/10k844/singt4/db/singt4.quartus_db" { Floorplan "E:/EDA/DDS/10k844/singt4/" "" "2.900 ns" { Mux~693 Mux~694 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.500 ns) + CELL(2.300 ns) 14.900 ns Mux~696 4 COMB LC2_C8 1 " "Info: 4: + IC(2.500 ns) + CELL(2.300 ns) = 14.900 ns; Loc. = LC2_C8; Fanout = 1; COMB Node = 'Mux~696'" {  } { { "E:/EDA/DDS/10k844/singt4/db/singt4_cmp.qrpt" "" { Report "E:/EDA/DDS/10k844/singt4/db/singt4_cmp.qrpt" Compiler "singt4" "UNKNOWN" "V1" "E:/EDA/DDS/10k844/singt4/db/singt4.quartus_db" { Floorplan "E:/EDA/DDS/10k844/singt4/" "" "4.800 ns" { Mux~694 Mux~696 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.200 ns) + CELL(1.800 ns) 18.900 ns Mux~703 5 COMB LC3_C7 1 " "Info: 5: + IC(2.200 ns) + CELL(1.800 ns) = 18.900 ns; Loc. = LC3_C7; Fanout = 1; COMB Node = 'Mux~703'" {  } { { "E:/EDA/DDS/10k844/singt4/db/singt4_cmp.qrpt" "" { Report "E:/EDA/DDS/10k844/singt4/db/singt4_cmp.qrpt" Compiler "singt4" "UNKNOWN" "V1" "E:/EDA/DDS/10k844/singt4/db/singt4.quartus_db" { Floorplan "E:/EDA/DDS/10k844/singt4/" "" "4.000 ns" { Mux~696 Mux~703 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.500 ns) + CELL(5.100 ns) 26.500 ns dout\[3\] 6 PIN PIN_61 0 " "Info: 6: + IC(2.500 ns) + CELL(5.100 ns) = 26.500 ns; Loc. = PIN_61; Fanout = 0; PIN Node = 'dout\[3\]'" {  } { { "E:/EDA/DDS/10k844/singt4/db/singt4_cmp.qrpt" "" { Report "E:/EDA/DDS/10k844/singt4/db/singt4_cmp.qrpt" Compiler "singt4" "UNKNOWN" "V1" "E:/EDA/DDS/10k844/singt4/db/singt4.quartus_db" { Floorplan "E:/EDA/DDS/10k844/singt4/" "" "7.600 ns" { Mux~703 dout[3] } "NODE_NAME" } "" } } { "singt4.vhd" "" { Text "E:/EDA/DDS/10k844/singt4/singt4.vhd" 8 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "13.800 ns 52.08 % " "Info: Total cell delay = 13.800 ns ( 52.08 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "12.700 ns 47.92 % " "Info: Total interconnect delay = 12.700 ns ( 47.92 % )" {  } {  } 0}  } { { "E:/EDA/DDS/10k844/singt4/db/singt4_cmp.qrpt" "" { Report "E:/EDA/DDS/10k844/singt4/db/singt4_cmp.qrpt" Compiler "singt4" "UNKNOWN" "V1" "E:/EDA/DDS/10k844/singt4/db/singt4.quartus_db" { Floorplan "E:/EDA/DDS/10k844/singt4/" "" "26.500 ns" { q[2] Mux~693 Mux~694 Mux~696 Mux~703 dout[3] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "26.500 ns" { q[2] Mux~693 Mux~694 Mux~696 Mux~703 dout[3] } { 0.000ns 4.900ns 0.600ns 2.500ns 2.200ns 2.500ns } { 0.000ns 2.300ns 2.300ns 2.300ns 1.800ns 5.100ns } } }  } 0}  } { { "E:/EDA/DDS/10k844/singt4/db/singt4_cmp.qrpt" "" { Report "E:/EDA/DDS/10k844/singt4/db/singt4_cmp.qrpt" Compiler "singt4" "UNKNOWN" "V1" "E:/EDA/DDS/10k844/singt4/db/singt4.quartus_db" { Floorplan "E:/EDA/DDS/10k844/singt4/" "" "5.300 ns" { clk q[2] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "5.300 ns" { clk clk~out q[2] } { 0.000ns 0.000ns 2.500ns } { 0.000ns 2.800ns 0.000ns } } } { "E:/EDA/DDS/10k844/singt4/db/singt4_cmp.qrpt" "" { Report "E:/EDA/DDS/10k844/singt4/db/singt4_cmp.qrpt" Compiler "singt4" "UNKNOWN" "V1" "E:/EDA/DDS/10k844/singt4/db/singt4.quartus_db" { Floorplan "E:/EDA/DDS/10k844/singt4/" "" "26.500 ns" { q[2] Mux~693 Mux~694 Mux~696 Mux~703 dout[3] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "26.500 ns" { q[2] Mux~693 Mux~694 Mux~696 Mux~703 dout[3] } { 0.000ns 4.900ns 0.600ns 2.500ns 2.200ns 2.500ns } { 0.000ns 2.300ns 2.300ns 2.300ns 1.800ns 5.100ns } } }  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 1  Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Fri Apr 14 22:09:17 2006 " "Info: Processing ended: Fri Apr 14 22:09:17 2006" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Info: Elapsed time: 00:00:03" {  } {  } 0}  } {  } 0}