scancnt4b.tan.rpt

来自「在EDA开发软件QuartusII上利用VHDL语言实现DDS信号发生器」· RPT 代码 · 共 216 行 · 第 1/2 页

+-------+--------------+------------+------+------------------------------------------------------------+----------+
; N/A   ; None         ; 3.300 ns   ; EN   ; lpm_counter:CNT4_rtl_0|alt_counter_f10ke:wysi_counter|q[0] ; CLK      ;
; N/A   ; None         ; 3.300 ns   ; EN   ; lpm_counter:CNT4_rtl_0|alt_counter_f10ke:wysi_counter|q[1] ; CLK      ;
; N/A   ; None         ; 3.300 ns   ; EN   ; lpm_counter:CNT4_rtl_0|alt_counter_f10ke:wysi_counter|q[2] ; CLK      ;
; N/A   ; None         ; 3.300 ns   ; EN   ; lpm_counter:CNT4_rtl_0|alt_counter_f10ke:wysi_counter|q[3] ; CLK      ;
+-------+--------------+------------+------+------------------------------------------------------------+----------+


+-----------------------------------------------------------------------------------------------------------------------+
; tco                                                                                                                   ;
+-------+--------------+------------+------------------------------------------------------------+---------+------------+
; Slack ; Required tco ; Actual tco ; From                                                       ; To      ; From Clock ;
+-------+--------------+------------+------------------------------------------------------------+---------+------------+
; N/A   ; None         ; 13.100 ns  ; lpm_counter:CNT4_rtl_0|alt_counter_f10ke:wysi_counter|q[3] ; FOUT[3] ; CLK        ;
; N/A   ; None         ; 13.100 ns  ; lpm_counter:CNT4_rtl_0|alt_counter_f10ke:wysi_counter|q[2] ; FOUT[2] ; CLK        ;
; N/A   ; None         ; 13.100 ns  ; lpm_counter:CNT4_rtl_0|alt_counter_f10ke:wysi_counter|q[0] ; FOUT[0] ; CLK        ;
; N/A   ; None         ; 12.600 ns  ; lpm_counter:CNT4_rtl_0|alt_counter_f10ke:wysi_counter|q[1] ; FOUT[1] ; CLK        ;
+-------+--------------+------------+------------------------------------------------------------+---------+------------+


+------------------------------------------------------------------------------------------------------------------------+
; th                                                                                                                     ;
+---------------+-------------+-----------+------+------------------------------------------------------------+----------+
; Minimum Slack ; Required th ; Actual th ; From ; To                                                         ; To Clock ;
+---------------+-------------+-----------+------+------------------------------------------------------------+----------+
; N/A           ; None        ; 1.300 ns  ; EN   ; lpm_counter:CNT4_rtl_0|alt_counter_f10ke:wysi_counter|q[0] ; CLK      ;
; N/A           ; None        ; 1.300 ns  ; EN   ; lpm_counter:CNT4_rtl_0|alt_counter_f10ke:wysi_counter|q[1] ; CLK      ;
; N/A           ; None        ; 1.300 ns  ; EN   ; lpm_counter:CNT4_rtl_0|alt_counter_f10ke:wysi_counter|q[2] ; CLK      ;
; N/A           ; None        ; 1.300 ns  ; EN   ; lpm_counter:CNT4_rtl_0|alt_counter_f10ke:wysi_counter|q[3] ; CLK      ;
+---------------+-------------+-----------+------+------------------------------------------------------------+----------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
    Info: Version 5.0 Build 148 04/26/2005 SJ Full Version
    Info: Processing started: Fri Apr 14 20:56:21 2006
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off SCANCNT4B -c SCANCNT4B
Info: Started post-fitting delay annotation
Info: Delay annotation completed successfully
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "CLK" is an undefined clock
Info: Clock "CLK" Internal fmax is restricted to 125.0 MHz between source register "lpm_counter:CNT4_rtl_0|alt_counter_f10ke:wysi_counter|q[0]" and destination register "lpm_counter:CNT4_rtl_0|alt_counter_f10ke:wysi_counter|q[3]"
    Info: fmax restricted to Clock High delay (4.0 ns) plus Clock Low delay (4.0 ns) : restricted to 8.0 ns. Expand message to see actual delay path.
        Info: + Longest register to register delay is 2.500 ns
            Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC1_A15; Fanout = 4; REG Node = 'lpm_counter:CNT4_rtl_0|alt_counter_f10ke:wysi_counter|q[0]'
            Info: 2: + IC(0.000 ns) + CELL(1.200 ns) = 1.200 ns; Loc. = LC1_A15; Fanout = 3; COMB Node = 'lpm_counter:CNT4_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[0]~COUT'
            Info: 3: + IC(0.000 ns) + CELL(0.300 ns) = 1.500 ns; Loc. = LC2_A15; Fanout = 3; COMB Node = 'lpm_counter:CNT4_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[1]~COUT'
            Info: 4: + IC(0.000 ns) + CELL(0.300 ns) = 1.800 ns; Loc. = LC3_A15; Fanout = 1; COMB Node = 'lpm_counter:CNT4_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[2]~COUT'
            Info: 5: + IC(0.000 ns) + CELL(0.700 ns) = 2.500 ns; Loc. = LC4_A15; Fanout = 2; REG Node = 'lpm_counter:CNT4_rtl_0|alt_counter_f10ke:wysi_counter|q[3]'
            Info: Total cell delay = 2.500 ns ( 100.00 % )
        Info: - Smallest clock skew is 0.000 ns
            Info: + Shortest clock path from clock "CLK" to destination register is 5.300 ns
                Info: 1: + IC(0.000 ns) + CELL(2.800 ns) = 2.800 ns; Loc. = PIN_43; Fanout = 7; CLK Node = 'CLK'
                Info: 2: + IC(2.500 ns) + CELL(0.000 ns) = 5.300 ns; Loc. = LC4_A15; Fanout = 2; REG Node = 'lpm_counter:CNT4_rtl_0|alt_counter_f10ke:wysi_counter|q[3]'
                Info: Total cell delay = 2.800 ns ( 52.83 % )
                Info: Total interconnect delay = 2.500 ns ( 47.17 % )
            Info: - Longest clock path from clock "CLK" to source register is 5.300 ns
                Info: 1: + IC(0.000 ns) + CELL(2.800 ns) = 2.800 ns; Loc. = PIN_43; Fanout = 7; CLK Node = 'CLK'
                Info: 2: + IC(2.500 ns) + CELL(0.000 ns) = 5.300 ns; Loc. = LC1_A15; Fanout = 4; REG Node = 'lpm_counter:CNT4_rtl_0|alt_counter_f10ke:wysi_counter|q[0]'
                Info: Total cell delay = 2.800 ns ( 52.83 % )
                Info: Total interconnect delay = 2.500 ns ( 47.17 % )
        Info: + Micro clock to output delay of source is 1.100 ns
        Info: + Micro setup delay of destination is 2.500 ns
Info: tsu for register "lpm_counter:CNT4_rtl_0|alt_counter_f10ke:wysi_counter|q[0]" (data pin = "EN", clock pin = "CLK") is 3.300 ns
    Info: + Longest pin to register delay is 6.100 ns
        Info: 1: + IC(0.000 ns) + CELL(2.800 ns) = 2.800 ns; Loc. = PIN_84; Fanout = 14; PIN Node = 'EN'
        Info: 2: + IC(1.600 ns) + CELL(1.700 ns) = 6.100 ns; Loc. = LC1_A15; Fanout = 4; REG Node = 'lpm_counter:CNT4_rtl_0|alt_counter_f10ke:wysi_counter|q[0]'
        Info: Total cell delay = 4.500 ns ( 73.77 % )
        Info: Total interconnect delay = 1.600 ns ( 26.23 % )
    Info: + Micro setup delay of destination is 2.500 ns
    Info: - Shortest clock path from clock "CLK" to destination register is 5.300 ns
        Info: 1: + IC(0.000 ns) + CELL(2.800 ns) = 2.800 ns; Loc. = PIN_43; Fanout = 7; CLK Node = 'CLK'
        Info: 2: + IC(2.500 ns) + CELL(0.000 ns) = 5.300 ns; Loc. = LC1_A15; Fanout = 4; REG Node = 'lpm_counter:CNT4_rtl_0|alt_counter_f10ke:wysi_counter|q[0]'
        Info: Total cell delay = 2.800 ns ( 52.83 % )
        Info: Total interconnect delay = 2.500 ns ( 47.17 % )
Info: tco from clock "CLK" to destination pin "FOUT[3]" through register "lpm_counter:CNT4_rtl_0|alt_counter_f10ke:wysi_counter|q[3]" is 13.100 ns
    Info: + Longest clock path from clock "CLK" to source register is 5.300 ns
        Info: 1: + IC(0.000 ns) + CELL(2.800 ns) = 2.800 ns; Loc. = PIN_43; Fanout = 7; CLK Node = 'CLK'
        Info: 2: + IC(2.500 ns) + CELL(0.000 ns) = 5.300 ns; Loc. = LC4_A15; Fanout = 2; REG Node = 'lpm_counter:CNT4_rtl_0|alt_counter_f10ke:wysi_counter|q[3]'
        Info: Total cell delay = 2.800 ns ( 52.83 % )
        Info: Total interconnect delay = 2.500 ns ( 47.17 % )
    Info: + Micro clock to output delay of source is 1.100 ns
    Info: + Longest register to pin delay is 6.700 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC4_A15; Fanout = 2; REG Node = 'lpm_counter:CNT4_rtl_0|alt_counter_f10ke:wysi_counter|q[3]'
        Info: 2: + IC(1.600 ns) + CELL(5.100 ns) = 6.700 ns; Loc. = PIN_71; Fanout = 0; PIN Node = 'FOUT[3]'
        Info: Total cell delay = 5.100 ns ( 76.12 % )
        Info: Total interconnect delay = 1.600 ns ( 23.88 % )
Info: th for register "lpm_counter:CNT4_rtl_0|alt_counter_f10ke:wysi_counter|q[0]" (data pin = "EN", clock pin = "CLK") is 1.300 ns
    Info: + Longest clock path from clock "CLK" to destination register is 5.300 ns
        Info: 1: + IC(0.000 ns) + CELL(2.800 ns) = 2.800 ns; Loc. = PIN_43; Fanout = 7; CLK Node = 'CLK'
        Info: 2: + IC(2.500 ns) + CELL(0.000 ns) = 5.300 ns; Loc. = LC1_A15; Fanout = 4; REG Node = 'lpm_counter:CNT4_rtl_0|alt_counter_f10ke:wysi_counter|q[0]'
        Info: Total cell delay = 2.800 ns ( 52.83 % )
        Info: Total interconnect delay = 2.500 ns ( 47.17 % )
    Info: + Micro hold delay of destination is 1.600 ns
    Info: - Shortest pin to register delay is 5.600 ns
        Info: 1: + IC(0.000 ns) + CELL(2.800 ns) = 2.800 ns; Loc. = PIN_84; Fanout = 14; PIN Node = 'EN'
        Info: 2: + IC(1.600 ns) + CELL(1.200 ns) = 5.600 ns; Loc. = LC1_A15; Fanout = 4; REG Node = 'lpm_counter:CNT4_rtl_0|alt_counter_f10ke:wysi_counter|q[0]'
        Info: Total cell delay = 4.000 ns ( 71.43 % )
        Info: Total interconnect delay = 1.600 ns ( 28.57 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning
    Info: Processing ended: Fri Apr 14 20:56:23 2006
    Info: Elapsed time: 00:00:03