scancnt4b.fit.eqn
来自「在EDA开发软件QuartusII上利用VHDL语言实现DDS信号发生器」· EQN 代码 · 共 113 行
EQN
113 行
-- Copyright (C) 1991-2005 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and any output files any of the foregoing
-- (including device programming or simulation files), and any
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-- to the terms and conditions of the Altera Program License
-- Subscription Agreement, Altera MegaCore Function License
-- Agreement, or other applicable license agreement, including,
-- without limitation, that your use is for the sole purpose of
-- programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the
-- applicable agreement for further details.
--C1_q[0] is lpm_counter:CNT4_rtl_0|alt_counter_f10ke:wysi_counter|q[0] at LC1_A15
--operation mode is clrb_cntr
C1_q[0]_lut_out = (EN $ C1_q[0]) & VCC;
C1_q[0] = DFFEA(C1_q[0]_lut_out, GLOBAL(CLK), , , EN, , );
--C1L11Q is lpm_counter:CNT4_rtl_0|alt_counter_f10ke:wysi_counter|q[0]~0 at LC1_A15
--operation mode is clrb_cntr
C1L11Q = C1_q[0];
--C1L3 is lpm_counter:CNT4_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[0]~COUT at LC1_A15
--operation mode is clrb_cntr
C1L3 = CARRY(C1_q[0]);
--C1_q[1] is lpm_counter:CNT4_rtl_0|alt_counter_f10ke:wysi_counter|q[1] at LC2_A15
--operation mode is clrb_cntr
C1_q[1]_lut_out = (C1_q[1] $ (EN & C1L3)) & VCC;
C1_q[1] = DFFEA(C1_q[1]_lut_out, GLOBAL(CLK), , , EN, , );
--C1L31Q is lpm_counter:CNT4_rtl_0|alt_counter_f10ke:wysi_counter|q[1]~1 at LC2_A15
--operation mode is clrb_cntr
C1L31Q = C1_q[1];
--C1L5 is lpm_counter:CNT4_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[1]~COUT at LC2_A15
--operation mode is clrb_cntr
C1L5 = CARRY(C1_q[1] & (C1L3));
--C1_q[2] is lpm_counter:CNT4_rtl_0|alt_counter_f10ke:wysi_counter|q[2] at LC3_A15
--operation mode is clrb_cntr
C1_q[2]_lut_out = (C1_q[2] $ (EN & C1L5)) & VCC;
C1_q[2] = DFFEA(C1_q[2]_lut_out, GLOBAL(CLK), , , EN, , );
--C1L51Q is lpm_counter:CNT4_rtl_0|alt_counter_f10ke:wysi_counter|q[2]~2 at LC3_A15
--operation mode is clrb_cntr
C1L51Q = C1_q[2];
--C1L7 is lpm_counter:CNT4_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[2]~COUT at LC3_A15
--operation mode is clrb_cntr
C1L7 = CARRY(C1_q[2] & (C1L5));
--C1_q[3] is lpm_counter:CNT4_rtl_0|alt_counter_f10ke:wysi_counter|q[3] at LC4_A15
--operation mode is clrb_cntr
C1_q[3]_lut_out = (C1_q[3] $ (EN & C1L7)) & VCC;
C1_q[3] = DFFEA(C1_q[3]_lut_out, GLOBAL(CLK), , , EN, , );
--C1L71Q is lpm_counter:CNT4_rtl_0|alt_counter_f10ke:wysi_counter|q[3]~3 at LC4_A15
--operation mode is clrb_cntr
C1L71Q = C1_q[3];
--EN is EN at PIN_84
--operation mode is input
EN = INPUT();
--CLK is CLK at PIN_43
--operation mode is input
CLK = INPUT();
--FOUT[0] is FOUT[0] at PIN_73
--operation mode is output
FOUT[0] = OUTPUT(C1_q[0]);
--FOUT[1] is FOUT[1] at PIN_48
--operation mode is output
FOUT[1] = OUTPUT(C1_q[1]);
--FOUT[2] is FOUT[2] at PIN_72
--operation mode is output
FOUT[2] = OUTPUT(C1_q[2]);
--FOUT[3] is FOUT[3] at PIN_71
--operation mode is output
FOUT[3] = OUTPUT(C1_q[3]);
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