divf.tan.qmsg

来自「在EDA开发软件QuartusII上利用VHDL语言实现DDS信号发生器」· QMSG 代码 · 共 12 行 · 第 1/3 页

{ "Info" "ITDB_FULL_TCO_RESULT" "CLK COUT COUT~reg0 13.200 ns register " "Info: tco from clock \"CLK\" to destination pin \"COUT\" through register \"COUT~reg0\" is 13.200 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK source 5.300 ns + Longest register " "Info: + Longest clock path from clock \"CLK\" to source register is 5.300 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.800 ns) 2.800 ns CLK 1 CLK PIN_43 8 " "Info: 1: + IC(0.000 ns) + CELL(2.800 ns) = 2.800 ns; Loc. = PIN_43; Fanout = 8; CLK Node = 'CLK'" {  } { { "E:/EDA/DDS/10k844/divf8/db/divf_cmp.qrpt" "" { Report "E:/EDA/DDS/10k844/divf8/db/divf_cmp.qrpt" Compiler "divf" "UNKNOWN" "V1" "E:/EDA/DDS/10k844/divf8/db/divf.quartus_db" { Floorplan "E:/EDA/DDS/10k844/divf8/" "" "" { CLK } "NODE_NAME" } "" } } { "divf.vhd" "" { Text "E:/EDA/DDS/10k844/divf8/divf.vhd" 6 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.500 ns) + CELL(0.000 ns) 5.300 ns COUT~reg0 2 REG LC5_A13 1 " "Info: 2: + IC(2.500 ns) + CELL(0.000 ns) = 5.300 ns; Loc. = LC5_A13; Fanout = 1; REG Node = 'COUT~reg0'" {  } { { "E:/EDA/DDS/10k844/divf8/db/divf_cmp.qrpt" "" { Report "E:/EDA/DDS/10k844/divf8/db/divf_cmp.qrpt" Compiler "divf" "UNKNOWN" "V1" "E:/EDA/DDS/10k844/divf8/db/divf.quartus_db" { Floorplan "E:/EDA/DDS/10k844/divf8/" "" "2.500 ns" { CLK COUT~reg0 } "NODE_NAME" } "" } } { "divf.vhd" "" { Text "E:/EDA/DDS/10k844/divf8/divf.vhd" 19 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.800 ns 52.83 % " "Info: Total cell delay = 2.800 ns ( 52.83 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.500 ns 47.17 % " "Info: Total interconnect delay = 2.500 ns ( 47.17 % )" {  } {  } 0}  } { { "E:/EDA/DDS/10k844/divf8/db/divf_cmp.qrpt" "" { Report "E:/EDA/DDS/10k844/divf8/db/divf_cmp.qrpt" Compiler "divf" "UNKNOWN" "V1" "E:/EDA/DDS/10k844/divf8/db/divf.quartus_db" { Floorplan "E:/EDA/DDS/10k844/divf8/" "" "5.300 ns" { CLK COUT~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "5.300 ns" { CLK CLK~out COUT~reg0 } { 0.000ns 0.000ns 2.500ns } { 0.000ns 2.800ns 0.000ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.100 ns + " "Info: + Micro clock to output delay of source is 1.100 ns" {  } { { "divf.vhd" "" { Text "E:/EDA/DDS/10k844/divf8/divf.vhd" 19 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.800 ns + Longest register pin " "Info: + Longest register to pin delay is 6.800 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns COUT~reg0 1 REG LC5_A13 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC5_A13; Fanout = 1; REG Node = 'COUT~reg0'" {  } { { "E:/EDA/DDS/10k844/divf8/db/divf_cmp.qrpt" "" { Report "E:/EDA/DDS/10k844/divf8/db/divf_cmp.qrpt" Compiler "divf" "UNKNOWN" "V1" "E:/EDA/DDS/10k844/divf8/db/divf.quartus_db" { Floorplan "E:/EDA/DDS/10k844/divf8/" "" "" { COUT~reg0 } "NODE_NAME" } "" } } { "divf.vhd" "" { Text "E:/EDA/DDS/10k844/divf8/divf.vhd" 19 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.700 ns) + CELL(5.100 ns) 6.800 ns COUT 2 PIN PIN_70 0 " "Info: 2: + IC(1.700 ns) + CELL(5.100 ns) = 6.800 ns; Loc. = PIN_70; Fanout = 0; PIN Node = 'COUT'" {  } { { "E:/EDA/DDS/10k844/divf8/db/divf_cmp.qrpt" "" { Report "E:/EDA/DDS/10k844/divf8/db/divf_cmp.qrpt" Compiler "divf" "UNKNOWN" "V1" "E:/EDA/DDS/10k844/divf8/db/divf.quartus_db" { Floorplan "E:/EDA/DDS/10k844/divf8/" "" "6.800 ns" { COUT~reg0 COUT } "NODE_NAME" } "" } } { "divf.vhd" "" { Text "E:/EDA/DDS/10k844/divf8/divf.vhd" 9 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "5.100 ns 75.00 % " "Info: Total cell delay = 5.100 ns ( 75.00 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.700 ns 25.00 % " "Info: Total interconnect delay = 1.700 ns ( 25.00 % )" {  } {  } 0}  } { { "E:/EDA/DDS/10k844/divf8/db/divf_cmp.qrpt" "" { Report "E:/EDA/DDS/10k844/divf8/db/divf_cmp.qrpt" Compiler "divf" "UNKNOWN" "V1" "E:/EDA/DDS/10k844/divf8/db/divf.quartus_db" { Floorplan "E:/EDA/DDS/10k844/divf8/" "" "6.800 ns" { COUT~reg0 COUT } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "6.800 ns" { COUT~reg0 COUT } { 0.000ns 1.700ns } { 0.000ns 5.100ns } } }  } 0}  } { { "E:/EDA/DDS/10k844/divf8/db/divf_cmp.qrpt" "" { Report "E:/EDA/DDS/10k844/divf8/db/divf_cmp.qrpt" Compiler "divf" "UNKNOWN" "V1" "E:/EDA/DDS/10k844/divf8/db/divf.quartus_db" { Floorplan "E:/EDA/DDS/10k844/divf8/" "" "5.300 ns" { CLK COUT~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "5.300 ns" { CLK CLK~out COUT~reg0 } { 0.000ns 0.000ns 2.500ns } { 0.000ns 2.800ns 0.000ns } } } { "E:/EDA/DDS/10k844/divf8/db/divf_cmp.qrpt" "" { Report "E:/EDA/DDS/10k844/divf8/db/divf_cmp.qrpt" Compiler "divf" "UNKNOWN" "V1" "E:/EDA/DDS/10k844/divf8/db/divf.quartus_db" { Floorplan "E:/EDA/DDS/10k844/divf8/" "" "6.800 ns" { COUT~reg0 COUT } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "6.800 ns" { COUT~reg0 COUT } { 0.000ns 1.700ns } { 0.000ns 5.100ns } } }  } 0}
{ "Info" "ITDB_TH_RESULT" "lpm_counter:CNT4_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[3\] DATA\[3\] CLK 0.700 ns register " "Info: th for register \"lpm_counter:CNT4_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[3\]\" (data pin = \"DATA\[3\]\", clock pin = \"CLK\") is 0.700 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK destination 5.300 ns + Longest register " "Info: + Longest clock path from clock \"CLK\" to destination register is 5.300 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.800 ns) 2.800 ns CLK 1 CLK PIN_43 8 " "Info: 1: + IC(0.000 ns) + CELL(2.800 ns) = 2.800 ns; Loc. = PIN_43; Fanout = 8; CLK Node = 'CLK'" {  } { { "E:/EDA/DDS/10k844/divf8/db/divf_cmp.qrpt" "" { Report "E:/EDA/DDS/10k844/divf8/db/divf_cmp.qrpt" Compiler "divf" "UNKNOWN" "V1" "E:/EDA/DDS/10k844/divf8/db/divf.quartus_db" { Floorplan "E:/EDA/DDS/10k844/divf8/" "" "" { CLK } "NODE_NAME" } "" } } { "divf.vhd" "" { Text "E:/EDA/DDS/10k844/divf8/divf.vhd" 6 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.500 ns) + CELL(0.000 ns) 5.300 ns lpm_counter:CNT4_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[3\] 2 REG LC4_A13 4 " "Info: 2: + IC(2.500 ns) + CELL(0.000 ns) = 5.300 ns; Loc. = LC4_A13; Fanout = 4; REG Node = 'lpm_counter:CNT4_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[3\]'" {  } { { "E:/EDA/DDS/10k844/divf8/db/divf_cmp.qrpt" "" { Report "E:/EDA/DDS/10k844/divf8/db/divf_cmp.qrpt" Compiler "divf" "UNKNOWN" "V1" "E:/EDA/DDS/10k844/divf8/db/divf.quartus_db" { Floorplan "E:/EDA/DDS/10k844/divf8/" "" "2.500 ns" { CLK lpm_counter:CNT4_rtl_0|alt_counter_f10ke:wysi_counter|q[3] } "NODE_NAME" } "" } } { "alt_counter_f10ke.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/alt_counter_f10ke.tdf" 271 2 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.800 ns 52.83 % " "Info: Total cell delay = 2.800 ns ( 52.83 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.500 ns 47.17 % " "Info: Total interconnect delay = 2.500 ns ( 47.17 % )" {  } {  } 0}  } { { "E:/EDA/DDS/10k844/divf8/db/divf_cmp.qrpt" "" { Report "E:/EDA/DDS/10k844/divf8/db/divf_cmp.qrpt" Compiler "divf" "UNKNOWN" "V1" "E:/EDA/DDS/10k844/divf8/db/divf.quartus_db" { Floorplan "E:/EDA/DDS/10k844/divf8/" "" "5.300 ns" { CLK lpm_counter:CNT4_rtl_0|alt_counter_f10ke:wysi_counter|q[3] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "5.300 ns" { CLK CLK~out lpm_counter:CNT4_rtl_0|alt_counter_f10ke:wysi_counter|q[3] } { 0.000ns 0.000ns 2.500ns } { 0.000ns 2.800ns 0.000ns } } }  } 0} { "Info" "ITDB_FULL_TH_DELAY" "1.600 ns + " "Info: + Micro hold delay of destination is 1.600 ns" {  } { { "alt_counter_f10ke.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/alt_counter_f10ke.tdf" 271 2 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.200 ns - Shortest pin register " "Info: - Shortest pin to register delay is 6.200 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.800 ns) 2.800 ns DATA\[3\] 1 PIN PIN_42 1 " "Info: 1: + IC(0.000 ns) + CELL(2.800 ns) = 2.800 ns; Loc. = PIN_42; Fanout = 1; PIN Node = 'DATA\[3\]'" {  } { { "E:/EDA/DDS/10k844/divf8/db/divf_cmp.qrpt" "" { Report "E:/EDA/DDS/10k844/divf8/db/divf_cmp.qrpt" Compiler "divf" "UNKNOWN" "V1" "E:/EDA/DDS/10k844/divf8/db/divf.quartus_db" { Floorplan "E:/EDA/DDS/10k844/divf8/" "" "" { DATA[3] } "NODE_NAME" } "" } } { "divf.vhd" "" { Text "E:/EDA/DDS/10k844/divf8/divf.vhd" 7 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.700 ns) + CELL(1.700 ns) 6.200 ns lpm_counter:CNT4_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[3\] 2 REG LC4_A13 4 " "Info: 2: + IC(1.700 ns) + CELL(1.700 ns) = 6.200 ns; Loc. = LC4_A13; Fanout = 4; REG Node = 'lpm_counter:CNT4_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[3\]'" {  } { { "E:/EDA/DDS/10k844/divf8/db/divf_cmp.qrpt" "" { Report "E:/EDA/DDS/10k844/divf8/db/divf_cmp.qrpt" Compiler "divf" "UNKNOWN" "V1" "E:/EDA/DDS/10k844/divf8/db/divf.quartus_db" { Floorplan "E:/EDA/DDS/10k844/divf8/" "" "3.400 ns" { DATA[3] lpm_counter:CNT4_rtl_0|alt_counter_f10ke:wysi_counter|q[3] } "NODE_NAME" } "" } } { "alt_counter_f10ke.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/alt_counter_f10ke.tdf" 271 2 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.500 ns 72.58 % " "Info: Total cell delay = 4.500 ns ( 72.58 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.700 ns 27.42 % " "Info: Total interconnect delay = 1.700 ns ( 27.42 % )" {  } {  } 0}  } { { "E:/EDA/DDS/10k844/divf8/db/divf_cmp.qrpt" "" { Report "E:/EDA/DDS/10k844/divf8/db/divf_cmp.qrpt" Compiler "divf" "UNKNOWN" "V1" "E:/EDA/DDS/10k844/divf8/db/divf.quartus_db" { Floorplan "E:/EDA/DDS/10k844/divf8/" "" "6.200 ns" { DATA[3] lpm_counter:CNT4_rtl_0|alt_counter_f10ke:wysi_counter|q[3] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "6.200 ns" { DATA[3] DATA[3]~out lpm_counter:CNT4_rtl_0|alt_counter_f10ke:wysi_counter|q[3] } { 0.000ns 0.000ns 1.700ns } { 0.000ns 2.800ns 1.700ns } } }  } 0}  } { { "E:/EDA/DDS/10k844/divf8/db/divf_cmp.qrpt" "" { Report "E:/EDA/DDS/10k844/divf8/db/divf_cmp.qrpt" Compiler "divf" "UNKNOWN" "V1" "E:/EDA/DDS/10k844/divf8/db/divf.quartus_db" { Floorplan "E:/EDA/DDS/10k844/divf8/" "" "5.300 ns" { CLK lpm_counter:CNT4_rtl_0|alt_counter_f10ke:wysi_counter|q[3] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "5.300 ns" { CLK CLK~out lpm_counter:CNT4_rtl_0|alt_counter_f10ke:wysi_counter|q[3] } { 0.000ns 0.000ns 2.500ns } { 0.000ns 2.800ns 0.000ns } } } { "E:/EDA/DDS/10k844/divf8/db/divf_cmp.qrpt" "" { Report "E:/EDA/DDS/10k844/divf8/db/divf_cmp.qrpt" Compiler "divf" "UNKNOWN" "V1" "E:/EDA/DDS/10k844/divf8/db/divf.quartus_db" { Floorplan "E:/EDA/DDS/10k844/divf8/" "" "6.200 ns" { DATA[3] lpm_counter:CNT4_rtl_0|alt_counter_f10ke:wysi_counter|q[3] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "6.200 ns" { DATA[3] DATA[3]~out lpm_counter:CNT4_rtl_0|alt_counter_f10ke:wysi_counter|q[3] } { 0.000ns 0.000ns 1.700ns } { 0.000ns 2.800ns 1.700ns } } }  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 1  Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Fri Apr 14 19:46:23 2006 " "Info: Processing ended: Fri Apr 14 19:46:23 2006" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:06 " "Info: Elapsed time: 00:00:06" {  } {  } 0}  } {  } 0}