divf.tan.qmsg

来自「在EDA开发软件QuartusII上利用VHDL语言实现DDS信号发生器」· QMSG 代码 · 共 12 行 · 第 1/3 页

{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "CLK " "Info: Assuming node \"CLK\" is an undefined clock" {  } { { "divf.vhd" "" { Text "E:/EDA/DDS/10k844/divf8/divf.vhd" 6 -1 0 } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "CLK" } } } }  } 0}  } {  } 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "CLK register lpm_counter:CNT4_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[0\] register lpm_counter:CNT4_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[3\] 120.48 MHz 8.3 ns Internal " "Info: Clock \"CLK\" has Internal fmax of 120.48 MHz between source register \"lpm_counter:CNT4_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[0\]\" and destination register \"lpm_counter:CNT4_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[3\]\" (period= 8.3 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.700 ns + Longest register register " "Info: + Longest register to register delay is 4.700 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns lpm_counter:CNT4_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[0\] 1 REG LC1_A13 6 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC1_A13; Fanout = 6; REG Node = 'lpm_counter:CNT4_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[0\]'" {  } { { "E:/EDA/DDS/10k844/divf8/db/divf_cmp.qrpt" "" { Report "E:/EDA/DDS/10k844/divf8/db/divf_cmp.qrpt" Compiler "divf" "UNKNOWN" "V1" "E:/EDA/DDS/10k844/divf8/db/divf.quartus_db" { Floorplan "E:/EDA/DDS/10k844/divf8/" "" "" { lpm_counter:CNT4_rtl_0|alt_counter_f10ke:wysi_counter|q[0] } "NODE_NAME" } "" } } { "alt_counter_f10ke.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/alt_counter_f10ke.tdf" 271 2 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.600 ns) + CELL(2.300 ns) 2.900 ns LessThan~34 2 COMB LC6_A13 7 " "Info: 2: + IC(0.600 ns) + CELL(2.300 ns) = 2.900 ns; Loc. = LC6_A13; Fanout = 7; COMB Node = 'LessThan~34'" {  } { { "E:/EDA/DDS/10k844/divf8/db/divf_cmp.qrpt" "" { Report "E:/EDA/DDS/10k844/divf8/db/divf_cmp.qrpt" Compiler "divf" "UNKNOWN" "V1" "E:/EDA/DDS/10k844/divf8/db/divf.quartus_db" { Floorplan "E:/EDA/DDS/10k844/divf8/" "" "2.900 ns" { lpm_counter:CNT4_rtl_0|alt_counter_f10ke:wysi_counter|q[0] LessThan~34 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.600 ns) + CELL(1.200 ns) 4.700 ns lpm_counter:CNT4_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[3\] 3 REG LC4_A13 4 " "Info: 3: + IC(0.600 ns) + CELL(1.200 ns) = 4.700 ns; Loc. = LC4_A13; Fanout = 4; REG Node = 'lpm_counter:CNT4_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[3\]'" {  } { { "E:/EDA/DDS/10k844/divf8/db/divf_cmp.qrpt" "" { Report "E:/EDA/DDS/10k844/divf8/db/divf_cmp.qrpt" Compiler "divf" "UNKNOWN" "V1" "E:/EDA/DDS/10k844/divf8/db/divf.quartus_db" { Floorplan "E:/EDA/DDS/10k844/divf8/" "" "1.800 ns" { LessThan~34 lpm_counter:CNT4_rtl_0|alt_counter_f10ke:wysi_counter|q[3] } "NODE_NAME" } "" } } { "alt_counter_f10ke.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/alt_counter_f10ke.tdf" 271 2 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.500 ns 74.47 % " "Info: Total cell delay = 3.500 ns ( 74.47 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.200 ns 25.53 % " "Info: Total interconnect delay = 1.200 ns ( 25.53 % )" {  } {  } 0}  } { { "E:/EDA/DDS/10k844/divf8/db/divf_cmp.qrpt" "" { Report "E:/EDA/DDS/10k844/divf8/db/divf_cmp.qrpt" Compiler "divf" "UNKNOWN" "V1" "E:/EDA/DDS/10k844/divf8/db/divf.quartus_db" { Floorplan "E:/EDA/DDS/10k844/divf8/" "" "4.700 ns" { lpm_counter:CNT4_rtl_0|alt_counter_f10ke:wysi_counter|q[0] LessThan~34 lpm_counter:CNT4_rtl_0|alt_counter_f10ke:wysi_counter|q[3] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "4.700 ns" { lpm_counter:CNT4_rtl_0|alt_counter_f10ke:wysi_counter|q[0] LessThan~34 lpm_counter:CNT4_rtl_0|alt_counter_f10ke:wysi_counter|q[3] } { 0.000ns 0.600ns 0.600ns } { 0.000ns 2.300ns 1.200ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK destination 5.300 ns + Shortest register " "Info: + Shortest clock path from clock \"CLK\" to destination register is 5.300 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.800 ns) 2.800 ns CLK 1 CLK PIN_43 8 " "Info: 1: + IC(0.000 ns) + CELL(2.800 ns) = 2.800 ns; Loc. = PIN_43; Fanout = 8; CLK Node = 'CLK'" {  } { { "E:/EDA/DDS/10k844/divf8/db/divf_cmp.qrpt" "" { Report "E:/EDA/DDS/10k844/divf8/db/divf_cmp.qrpt" Compiler "divf" "UNKNOWN" "V1" "E:/EDA/DDS/10k844/divf8/db/divf.quartus_db" { Floorplan "E:/EDA/DDS/10k844/divf8/" "" "" { CLK } "NODE_NAME" } "" } } { "divf.vhd" "" { Text "E:/EDA/DDS/10k844/divf8/divf.vhd" 6 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.500 ns) + CELL(0.000 ns) 5.300 ns lpm_counter:CNT4_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[3\] 2 REG LC4_A13 4 " "Info: 2: + IC(2.500 ns) + CELL(0.000 ns) = 5.300 ns; Loc. = LC4_A13; Fanout = 4; REG Node = 'lpm_counter:CNT4_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[3\]'" {  } { { "E:/EDA/DDS/10k844/divf8/db/divf_cmp.qrpt" "" { Report "E:/EDA/DDS/10k844/divf8/db/divf_cmp.qrpt" Compiler "divf" "UNKNOWN" "V1" "E:/EDA/DDS/10k844/divf8/db/divf.quartus_db" { Floorplan "E:/EDA/DDS/10k844/divf8/" "" "2.500 ns" { CLK lpm_counter:CNT4_rtl_0|alt_counter_f10ke:wysi_counter|q[3] } "NODE_NAME" } "" } } { "alt_counter_f10ke.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/alt_counter_f10ke.tdf" 271 2 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.800 ns 52.83 % " "Info: Total cell delay = 2.800 ns ( 52.83 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.500 ns 47.17 % " "Info: Total interconnect delay = 2.500 ns ( 47.17 % )" {  } {  } 0}  } { { "E:/EDA/DDS/10k844/divf8/db/divf_cmp.qrpt" "" { Report "E:/EDA/DDS/10k844/divf8/db/divf_cmp.qrpt" Compiler "divf" "UNKNOWN" "V1" "E:/EDA/DDS/10k844/divf8/db/divf.quartus_db" { Floorplan "E:/EDA/DDS/10k844/divf8/" "" "5.300 ns" { CLK lpm_counter:CNT4_rtl_0|alt_counter_f10ke:wysi_counter|q[3] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "5.300 ns" { CLK CLK~out lpm_counter:CNT4_rtl_0|alt_counter_f10ke:wysi_counter|q[3] } { 0.000ns 0.000ns 2.500ns } { 0.000ns 2.800ns 0.000ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK source 5.300 ns - Longest register " "Info: - Longest clock path from clock \"CLK\" to source register is 5.300 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.800 ns) 2.800 ns CLK 1 CLK PIN_43 8 " "Info: 1: + IC(0.000 ns) + CELL(2.800 ns) = 2.800 ns; Loc. = PIN_43; Fanout = 8; CLK Node = 'CLK'" {  } { { "E:/EDA/DDS/10k844/divf8/db/divf_cmp.qrpt" "" { Report "E:/EDA/DDS/10k844/divf8/db/divf_cmp.qrpt" Compiler "divf" "UNKNOWN" "V1" "E:/EDA/DDS/10k844/divf8/db/divf.quartus_db" { Floorplan "E:/EDA/DDS/10k844/divf8/" "" "" { CLK } "NODE_NAME" } "" } } { "divf.vhd" "" { Text "E:/EDA/DDS/10k844/divf8/divf.vhd" 6 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.500 ns) + CELL(0.000 ns) 5.300 ns lpm_counter:CNT4_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[0\] 2 REG LC1_A13 6 " "Info: 2: + IC(2.500 ns) + CELL(0.000 ns) = 5.300 ns; Loc. = LC1_A13; Fanout = 6; REG Node = 'lpm_counter:CNT4_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[0\]'" {  } { { "E:/EDA/DDS/10k844/divf8/db/divf_cmp.qrpt" "" { Report "E:/EDA/DDS/10k844/divf8/db/divf_cmp.qrpt" Compiler "divf" "UNKNOWN" "V1" "E:/EDA/DDS/10k844/divf8/db/divf.quartus_db" { Floorplan "E:/EDA/DDS/10k844/divf8/" "" "2.500 ns" { CLK lpm_counter:CNT4_rtl_0|alt_counter_f10ke:wysi_counter|q[0] } "NODE_NAME" } "" } } { "alt_counter_f10ke.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/alt_counter_f10ke.tdf" 271 2 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.800 ns 52.83 % " "Info: Total cell delay = 2.800 ns ( 52.83 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.500 ns 47.17 % " "Info: Total interconnect delay = 2.500 ns ( 47.17 % )" {  } {  } 0}  } { { "E:/EDA/DDS/10k844/divf8/db/divf_cmp.qrpt" "" { Report "E:/EDA/DDS/10k844/divf8/db/divf_cmp.qrpt" Compiler "divf" "UNKNOWN" "V1" "E:/EDA/DDS/10k844/divf8/db/divf.quartus_db" { Floorplan "E:/EDA/DDS/10k844/divf8/" "" "5.300 ns" { CLK lpm_counter:CNT4_rtl_0|alt_counter_f10ke:wysi_counter|q[0] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "5.300 ns" { CLK CLK~out lpm_counter:CNT4_rtl_0|alt_counter_f10ke:wysi_counter|q[0] } { 0.000ns 0.000ns 2.500ns } { 0.000ns 2.800ns 0.000ns } } }  } 0}  } { { "E:/EDA/DDS/10k844/divf8/db/divf_cmp.qrpt" "" { Report "E:/EDA/DDS/10k844/divf8/db/divf_cmp.qrpt" Compiler "divf" "UNKNOWN" "V1" "E:/EDA/DDS/10k844/divf8/db/divf.quartus_db" { Floorplan "E:/EDA/DDS/10k844/divf8/" "" "5.300 ns" { CLK lpm_counter:CNT4_rtl_0|alt_counter_f10ke:wysi_counter|q[3] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "5.300 ns" { CLK CLK~out lpm_counter:CNT4_rtl_0|alt_counter_f10ke:wysi_counter|q[3] } { 0.000ns 0.000ns 2.500ns } { 0.000ns 2.800ns 0.000ns } } } { "E:/EDA/DDS/10k844/divf8/db/divf_cmp.qrpt" "" { Report "E:/EDA/DDS/10k844/divf8/db/divf_cmp.qrpt" Compiler "divf" "UNKNOWN" "V1" "E:/EDA/DDS/10k844/divf8/db/divf.quartus_db" { Floorplan "E:/EDA/DDS/10k844/divf8/" "" "5.300 ns" { CLK lpm_counter:CNT4_rtl_0|alt_counter_f10ke:wysi_counter|q[0] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "5.300 ns" { CLK CLK~out lpm_counter:CNT4_rtl_0|alt_counter_f10ke:wysi_counter|q[0] } { 0.000ns 0.000ns 2.500ns } { 0.000ns 2.800ns 0.000ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.100 ns + " "Info: + Micro clock to output delay of source is 1.100 ns" {  } { { "alt_counter_f10ke.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/alt_counter_f10ke.tdf" 271 2 0 } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "2.500 ns + " "Info: + Micro setup delay of destination is 2.500 ns" {  } { { "alt_counter_f10ke.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/alt_counter_f10ke.tdf" 271 2 0 } }  } 0}  } { { "E:/EDA/DDS/10k844/divf8/db/divf_cmp.qrpt" "" { Report "E:/EDA/DDS/10k844/divf8/db/divf_cmp.qrpt" Compiler "divf" "UNKNOWN" "V1" "E:/EDA/DDS/10k844/divf8/db/divf.quartus_db" { Floorplan "E:/EDA/DDS/10k844/divf8/" "" "4.700 ns" { lpm_counter:CNT4_rtl_0|alt_counter_f10ke:wysi_counter|q[0] LessThan~34 lpm_counter:CNT4_rtl_0|alt_counter_f10ke:wysi_counter|q[3] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "4.700 ns" { lpm_counter:CNT4_rtl_0|alt_counter_f10ke:wysi_counter|q[0] LessThan~34 lpm_counter:CNT4_rtl_0|alt_counter_f10ke:wysi_counter|q[3] } { 0.000ns 0.600ns 0.600ns } { 0.000ns 2.300ns 1.200ns } } } { "E:/EDA/DDS/10k844/divf8/db/divf_cmp.qrpt" "" { Report "E:/EDA/DDS/10k844/divf8/db/divf_cmp.qrpt" Compiler "divf" "UNKNOWN" "V1" "E:/EDA/DDS/10k844/divf8/db/divf.quartus_db" { Floorplan "E:/EDA/DDS/10k844/divf8/" "" "5.300 ns" { CLK lpm_counter:CNT4_rtl_0|alt_counter_f10ke:wysi_counter|q[3] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "5.300 ns" { CLK CLK~out lpm_counter:CNT4_rtl_0|alt_counter_f10ke:wysi_counter|q[3] } { 0.000ns 0.000ns 2.500ns } { 0.000ns 2.800ns 0.000ns } } } { "E:/EDA/DDS/10k844/divf8/db/divf_cmp.qrpt" "" { Report "E:/EDA/DDS/10k844/divf8/db/divf_cmp.qrpt" Compiler "divf" "UNKNOWN" "V1" "E:/EDA/DDS/10k844/divf8/db/divf.quartus_db" { Floorplan "E:/EDA/DDS/10k844/divf8/" "" "5.300 ns" { CLK lpm_counter:CNT4_rtl_0|alt_counter_f10ke:wysi_counter|q[0] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "5.300 ns" { CLK CLK~out lpm_counter:CNT4_rtl_0|alt_counter_f10ke:wysi_counter|q[0] } { 0.000ns 0.000ns 2.500ns } { 0.000ns 2.800ns 0.000ns } } }  } 0}
{ "Info" "ITDB_TSU_RESULT" "lpm_counter:CNT4_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[3\] DATA\[3\] CLK 3.400 ns register " "Info: tsu for register \"lpm_counter:CNT4_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[3\]\" (data pin = \"DATA\[3\]\", clock pin = \"CLK\") is 3.400 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.200 ns + Longest pin register " "Info: + Longest pin to register delay is 6.200 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.800 ns) 2.800 ns DATA\[3\] 1 PIN PIN_42 1 " "Info: 1: + IC(0.000 ns) + CELL(2.800 ns) = 2.800 ns; Loc. = PIN_42; Fanout = 1; PIN Node = 'DATA\[3\]'" {  } { { "E:/EDA/DDS/10k844/divf8/db/divf_cmp.qrpt" "" { Report "E:/EDA/DDS/10k844/divf8/db/divf_cmp.qrpt" Compiler "divf" "UNKNOWN" "V1" "E:/EDA/DDS/10k844/divf8/db/divf.quartus_db" { Floorplan "E:/EDA/DDS/10k844/divf8/" "" "" { DATA[3] } "NODE_NAME" } "" } } { "divf.vhd" "" { Text "E:/EDA/DDS/10k844/divf8/divf.vhd" 7 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.700 ns) + CELL(1.700 ns) 6.200 ns lpm_counter:CNT4_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[3\] 2 REG LC4_A13 4 " "Info: 2: + IC(1.700 ns) + CELL(1.700 ns) = 6.200 ns; Loc. = LC4_A13; Fanout = 4; REG Node = 'lpm_counter:CNT4_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[3\]'" {  } { { "E:/EDA/DDS/10k844/divf8/db/divf_cmp.qrpt" "" { Report "E:/EDA/DDS/10k844/divf8/db/divf_cmp.qrpt" Compiler "divf" "UNKNOWN" "V1" "E:/EDA/DDS/10k844/divf8/db/divf.quartus_db" { Floorplan "E:/EDA/DDS/10k844/divf8/" "" "3.400 ns" { DATA[3] lpm_counter:CNT4_rtl_0|alt_counter_f10ke:wysi_counter|q[3] } "NODE_NAME" } "" } } { "alt_counter_f10ke.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/alt_counter_f10ke.tdf" 271 2 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.500 ns 72.58 % " "Info: Total cell delay = 4.500 ns ( 72.58 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.700 ns 27.42 % " "Info: Total interconnect delay = 1.700 ns ( 27.42 % )" {  } {  } 0}  } { { "E:/EDA/DDS/10k844/divf8/db/divf_cmp.qrpt" "" { Report "E:/EDA/DDS/10k844/divf8/db/divf_cmp.qrpt" Compiler "divf" "UNKNOWN" "V1" "E:/EDA/DDS/10k844/divf8/db/divf.quartus_db" { Floorplan "E:/EDA/DDS/10k844/divf8/" "" "6.200 ns" { DATA[3] lpm_counter:CNT4_rtl_0|alt_counter_f10ke:wysi_counter|q[3] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "6.200 ns" { DATA[3] DATA[3]~out lpm_counter:CNT4_rtl_0|alt_counter_f10ke:wysi_counter|q[3] } { 0.000ns 0.000ns 1.700ns } { 0.000ns 2.800ns 1.700ns } } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "2.500 ns + " "Info: + Micro setup delay of destination is 2.500 ns" {  } { { "alt_counter_f10ke.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/alt_counter_f10ke.tdf" 271 2 0 } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK destination 5.300 ns - Shortest register " "Info: - Shortest clock path from clock \"CLK\" to destination register is 5.300 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.800 ns) 2.800 ns CLK 1 CLK PIN_43 8 " "Info: 1: + IC(0.000 ns) + CELL(2.800 ns) = 2.800 ns; Loc. = PIN_43; Fanout = 8; CLK Node = 'CLK'" {  } { { "E:/EDA/DDS/10k844/divf8/db/divf_cmp.qrpt" "" { Report "E:/EDA/DDS/10k844/divf8/db/divf_cmp.qrpt" Compiler "divf" "UNKNOWN" "V1" "E:/EDA/DDS/10k844/divf8/db/divf.quartus_db" { Floorplan "E:/EDA/DDS/10k844/divf8/" "" "" { CLK } "NODE_NAME" } "" } } { "divf.vhd" "" { Text "E:/EDA/DDS/10k844/divf8/divf.vhd" 6 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.500 ns) + CELL(0.000 ns) 5.300 ns lpm_counter:CNT4_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[3\] 2 REG LC4_A13 4 " "Info: 2: + IC(2.500 ns) + CELL(0.000 ns) = 5.300 ns; Loc. = LC4_A13; Fanout = 4; REG Node = 'lpm_counter:CNT4_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[3\]'" {  } { { "E:/EDA/DDS/10k844/divf8/db/divf_cmp.qrpt" "" { Report "E:/EDA/DDS/10k844/divf8/db/divf_cmp.qrpt" Compiler "divf" "UNKNOWN" "V1" "E:/EDA/DDS/10k844/divf8/db/divf.quartus_db" { Floorplan "E:/EDA/DDS/10k844/divf8/" "" "2.500 ns" { CLK lpm_counter:CNT4_rtl_0|alt_counter_f10ke:wysi_counter|q[3] } "NODE_NAME" } "" } } { "alt_counter_f10ke.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/alt_counter_f10ke.tdf" 271 2 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.800 ns 52.83 % " "Info: Total cell delay = 2.800 ns ( 52.83 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.500 ns 47.17 % " "Info: Total interconnect delay = 2.500 ns ( 47.17 % )" {  } {  } 0}  } { { "E:/EDA/DDS/10k844/divf8/db/divf_cmp.qrpt" "" { Report "E:/EDA/DDS/10k844/divf8/db/divf_cmp.qrpt" Compiler "divf" "UNKNOWN" "V1" "E:/EDA/DDS/10k844/divf8/db/divf.quartus_db" { Floorplan "E:/EDA/DDS/10k844/divf8/" "" "5.300 ns" { CLK lpm_counter:CNT4_rtl_0|alt_counter_f10ke:wysi_counter|q[3] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "5.300 ns" { CLK CLK~out lpm_counter:CNT4_rtl_0|alt_counter_f10ke:wysi_counter|q[3] } { 0.000ns 0.000ns 2.500ns } { 0.000ns 2.800ns 0.000ns } } }  } 0}  } { { "E:/EDA/DDS/10k844/divf8/db/divf_cmp.qrpt" "" { Report "E:/EDA/DDS/10k844/divf8/db/divf_cmp.qrpt" Compiler "divf" "UNKNOWN" "V1" "E:/EDA/DDS/10k844/divf8/db/divf.quartus_db" { Floorplan "E:/EDA/DDS/10k844/divf8/" "" "6.200 ns" { DATA[3] lpm_counter:CNT4_rtl_0|alt_counter_f10ke:wysi_counter|q[3] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "6.200 ns" { DATA[3] DATA[3]~out lpm_counter:CNT4_rtl_0|alt_counter_f10ke:wysi_counter|q[3] } { 0.000ns 0.000ns 1.700ns } { 0.000ns 2.800ns 1.700ns } } } { "E:/EDA/DDS/10k844/divf8/db/divf_cmp.qrpt" "" { Report "E:/EDA/DDS/10k844/divf8/db/divf_cmp.qrpt" Compiler "divf" "UNKNOWN" "V1" "E:/EDA/DDS/10k844/divf8/db/divf.quartus_db" { Floorplan "E:/EDA/DDS/10k844/divf8/" "" "5.300 ns" { CLK lpm_counter:CNT4_rtl_0|alt_counter_f10ke:wysi_counter|q[3] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "5.300 ns" { CLK CLK~out lpm_counter:CNT4_rtl_0|alt_counter_f10ke:wysi_counter|q[3] } { 0.000ns 0.000ns 2.500ns } { 0.000ns 2.800ns 0.000ns } } }  } 0}