divf.map.rpt

来自「在EDA开发软件QuartusII上利用VHDL语言实现DDS信号发生器」· RPT 代码 · 共 235 行 · 第 1/2 页

; alt_counter_stratix.inc          ; yes             ; Other           ; d:/altera/quartus50/libraries/megafunctions/alt_counter_stratix.inc ;
; aglobal50.inc                    ; yes             ; Other           ; d:/altera/quartus50/libraries/megafunctions/aglobal50.inc           ;
; alt_counter_f10ke.tdf            ; yes             ; Megafunction    ; d:/altera/quartus50/libraries/megafunctions/alt_counter_f10ke.tdf   ;
; flex10ke_lcell.inc               ; yes             ; Other           ; d:/altera/quartus50/libraries/megafunctions/flex10ke_lcell.inc      ;
+----------------------------------+-----------------+-----------------+---------------------------------------------------------------------+


+---------------------------------------------+
; Analysis & Synthesis Resource Usage Summary ;
+-----------------------------------+---------+
; Resource                          ; Usage   ;
+-----------------------------------+---------+
; Total logic elements              ; 6       ;
; Total combinational functions     ; 6       ;
;     -- Total 4-input functions    ; 2       ;
;     -- Total 3-input functions    ; 0       ;
;     -- Total 2-input functions    ; 0       ;
;     -- Total 1-input functions    ; 0       ;
;     -- Total 0-input functions    ; 4       ;
; Combinational cells for routing   ; 0       ;
; Total registers                   ; 5       ;
; Total logic cells in carry chains ; 4       ;
; I/O pins                          ; 10      ;
; Maximum fan-out node              ; CLK     ;
; Maximum fan-out                   ; 5       ;
; Total fan-out                     ; 29      ;
; Average fan-out                   ; 1.81    ;
+-----------------------------------+---------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                                                                                            ;
+----------------------------------------+-------------+--------------+-------------+------+--------------+-------------------+------------------+-----------------+-------------------------------------------------------------+
; Compilation Hierarchy Node             ; Logic Cells ; LC Registers ; Memory Bits ; Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Full Hierarchy Name                                         ;
+----------------------------------------+-------------+--------------+-------------+------+--------------+-------------------+------------------+-----------------+-------------------------------------------------------------+
; |divf                                  ; 6 (2)       ; 5            ; 0           ; 10   ; 1 (1)        ; 0 (0)             ; 5 (1)            ; 4 (0)           ; |divf                                                       ;
;    |lpm_counter:CNT4_rtl_0|            ; 4 (0)       ; 4            ; 0           ; 0    ; 0 (0)        ; 0 (0)             ; 4 (0)            ; 4 (0)           ; |divf|lpm_counter:CNT4_rtl_0                                ;
;       |alt_counter_f10ke:wysi_counter| ; 4 (4)       ; 4            ; 0           ; 0    ; 0 (0)        ; 0 (0)             ; 4 (4)            ; 4 (4)           ; |divf|lpm_counter:CNT4_rtl_0|alt_counter_f10ke:wysi_counter ;
+----------------------------------------+-------------+--------------+-------------+------+--------------+-------------------+------------------+-----------------+-------------------------------------------------------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 5     ;
; Number of registers using Synchronous Clear  ; 0     ;
; Number of registers using Synchronous Load   ; 4     ;
; Number of registers using Asynchronous Clear ; 0     ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 0     ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+-------------------------------------------------------------------------+
; Parameter Settings for Inferred Entity Instance: lpm_counter:CNT4_rtl_0 ;
+------------------------+---------+--------------------------------------+
; Parameter Name         ; Value   ; Type                                 ;
+------------------------+---------+--------------------------------------+
; AUTO_CARRY_CHAINS      ; ON      ; AUTO_CARRY                           ;
; IGNORE_CARRY_BUFFERS   ; OFF     ; IGNORE_CARRY                         ;
; AUTO_CASCADE_CHAINS    ; ON      ; AUTO_CASCADE                         ;
; IGNORE_CASCADE_BUFFERS ; OFF     ; IGNORE_CASCADE                       ;
; LPM_WIDTH              ; 4       ; Untyped                              ;
; LPM_DIRECTION          ; UP      ; Untyped                              ;
; LPM_MODULUS            ; 0       ; Untyped                              ;
; LPM_AVALUE             ; UNUSED  ; Untyped                              ;
; LPM_SVALUE             ; UNUSED  ; Untyped                              ;
; DEVICE_FAMILY          ; FLEX10K ; Untyped                              ;
; CARRY_CHAIN            ; MANUAL  ; Untyped                              ;
; CARRY_CHAIN_LENGTH     ; 48      ; CARRY_CHAIN_LENGTH                   ;
; NOT_GATE_PUSH_BACK     ; ON      ; NOT_GATE_PUSH_BACK                   ;
; CARRY_CNT_EN           ; SMART   ; Untyped                              ;
; LABWIDE_SCLR           ; ON      ; Untyped                              ;
; USE_NEW_VERSION        ; TRUE    ; Untyped                              ;
; CBXI_PARAMETER         ; NOTHING ; Untyped                              ;
+------------------------+---------+--------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+--------------------------------+
; Analysis & Synthesis Equations ;
+--------------------------------+
The equations can be found in E:/EDA/DDS/10k844/divf8/divf.map.eqn.


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 5.0 Build 148 04/26/2005 SJ Full Version
    Info: Processing started: Fri Apr 14 19:45:25 2006
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off divf -c divf
Info: Found 2 design units, including 1 entities, in source file divf.vhd
    Info: Found design unit 1: divf-behav
    Info: Found entity 1: divf
Info: Elaborating entity "divf" for the top level hierarchy
Info: Inferred 1 megafunctions from design logic
    Info: Inferred lpm_counter megafunction (LPM_WIDTH=4) from the following logic: "CNT4[0]~4"
Info: Found 1 design units, including 1 entities, in source file d:/altera/quartus50/libraries/megafunctions/lpm_counter.tdf
    Info: Found entity 1: lpm_counter
Info: Found 1 design units, including 1 entities, in source file d:/altera/quartus50/libraries/megafunctions/alt_counter_f10ke.tdf
    Info: Found entity 1: alt_counter_f10ke
Info: Implemented 16 device resources after synthesis - the final resource count might be different
    Info: Implemented 5 input pins
    Info: Implemented 5 output pins
    Info: Implemented 6 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 0 warnings
    Info: Processing ended: Fri Apr 14 19:45:37 2006
    Info: Elapsed time: 00:00:14