divf.tan.rpt

来自「在EDA开发软件QuartusII上利用VHDL语言实现DDS信号发生器」· RPT 代码 · 共 225 行 · 第 1/2 页

+---------------------------------------------------------------------------------------------------------------------+
; tsu                                                                                                                 ;
+-------+--------------+------------+---------+------------------------------------------------------------+----------+
; Slack ; Required tsu ; Actual tsu ; From    ; To                                                         ; To Clock ;
+-------+--------------+------------+---------+------------------------------------------------------------+----------+
; N/A   ; None         ; 3.400 ns   ; DATA[3] ; lpm_counter:CNT4_rtl_0|alt_counter_f10ke:wysi_counter|q[3] ; CLK      ;
; N/A   ; None         ; 3.400 ns   ; DATA[2] ; lpm_counter:CNT4_rtl_0|alt_counter_f10ke:wysi_counter|q[2] ; CLK      ;
; N/A   ; None         ; 3.400 ns   ; DATA[1] ; lpm_counter:CNT4_rtl_0|alt_counter_f10ke:wysi_counter|q[1] ; CLK      ;
; N/A   ; None         ; 3.400 ns   ; DATA[0] ; lpm_counter:CNT4_rtl_0|alt_counter_f10ke:wysi_counter|q[0] ; CLK      ;
+-------+--------------+------------+---------+------------------------------------------------------------+----------+


+-----------------------------------------------------------------------------------------------------------------------+
; tco                                                                                                                   ;
+-------+--------------+------------+------------------------------------------------------------+---------+------------+
; Slack ; Required tco ; Actual tco ; From                                                       ; To      ; From Clock ;
+-------+--------------+------------+------------------------------------------------------------+---------+------------+
; N/A   ; None         ; 13.200 ns  ; COUT~reg0                                                  ; COUT    ; CLK        ;
; N/A   ; None         ; 13.200 ns  ; lpm_counter:CNT4_rtl_0|alt_counter_f10ke:wysi_counter|q[3] ; FOUT[3] ; CLK        ;
; N/A   ; None         ; 13.200 ns  ; lpm_counter:CNT4_rtl_0|alt_counter_f10ke:wysi_counter|q[2] ; FOUT[2] ; CLK        ;
; N/A   ; None         ; 13.200 ns  ; lpm_counter:CNT4_rtl_0|alt_counter_f10ke:wysi_counter|q[0] ; FOUT[0] ; CLK        ;
; N/A   ; None         ; 12.400 ns  ; lpm_counter:CNT4_rtl_0|alt_counter_f10ke:wysi_counter|q[1] ; FOUT[1] ; CLK        ;
+-------+--------------+------------+------------------------------------------------------------+---------+------------+


+---------------------------------------------------------------------------------------------------------------------------+
; th                                                                                                                        ;
+---------------+-------------+-----------+---------+------------------------------------------------------------+----------+
; Minimum Slack ; Required th ; Actual th ; From    ; To                                                         ; To Clock ;
+---------------+-------------+-----------+---------+------------------------------------------------------------+----------+
; N/A           ; None        ; 0.700 ns  ; DATA[3] ; lpm_counter:CNT4_rtl_0|alt_counter_f10ke:wysi_counter|q[3] ; CLK      ;
; N/A           ; None        ; 0.700 ns  ; DATA[2] ; lpm_counter:CNT4_rtl_0|alt_counter_f10ke:wysi_counter|q[2] ; CLK      ;
; N/A           ; None        ; 0.700 ns  ; DATA[1] ; lpm_counter:CNT4_rtl_0|alt_counter_f10ke:wysi_counter|q[1] ; CLK      ;
; N/A           ; None        ; 0.700 ns  ; DATA[0] ; lpm_counter:CNT4_rtl_0|alt_counter_f10ke:wysi_counter|q[0] ; CLK      ;
+---------------+-------------+-----------+---------+------------------------------------------------------------+----------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
    Info: Version 5.0 Build 148 04/26/2005 SJ Full Version
    Info: Processing started: Fri Apr 14 19:46:19 2006
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off divf -c divf
Info: Started post-fitting delay annotation
Info: Delay annotation completed successfully
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "CLK" is an undefined clock
Info: Clock "CLK" has Internal fmax of 120.48 MHz between source register "lpm_counter:CNT4_rtl_0|alt_counter_f10ke:wysi_counter|q[0]" and destination register "lpm_counter:CNT4_rtl_0|alt_counter_f10ke:wysi_counter|q[3]" (period= 8.3 ns)
    Info: + Longest register to register delay is 4.700 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC1_A13; Fanout = 6; REG Node = 'lpm_counter:CNT4_rtl_0|alt_counter_f10ke:wysi_counter|q[0]'
        Info: 2: + IC(0.600 ns) + CELL(2.300 ns) = 2.900 ns; Loc. = LC6_A13; Fanout = 7; COMB Node = 'LessThan~34'
        Info: 3: + IC(0.600 ns) + CELL(1.200 ns) = 4.700 ns; Loc. = LC4_A13; Fanout = 4; REG Node = 'lpm_counter:CNT4_rtl_0|alt_counter_f10ke:wysi_counter|q[3]'
        Info: Total cell delay = 3.500 ns ( 74.47 % )
        Info: Total interconnect delay = 1.200 ns ( 25.53 % )
    Info: - Smallest clock skew is 0.000 ns
        Info: + Shortest clock path from clock "CLK" to destination register is 5.300 ns
            Info: 1: + IC(0.000 ns) + CELL(2.800 ns) = 2.800 ns; Loc. = PIN_43; Fanout = 8; CLK Node = 'CLK'
            Info: 2: + IC(2.500 ns) + CELL(0.000 ns) = 5.300 ns; Loc. = LC4_A13; Fanout = 4; REG Node = 'lpm_counter:CNT4_rtl_0|alt_counter_f10ke:wysi_counter|q[3]'
            Info: Total cell delay = 2.800 ns ( 52.83 % )
            Info: Total interconnect delay = 2.500 ns ( 47.17 % )
        Info: - Longest clock path from clock "CLK" to source register is 5.300 ns
            Info: 1: + IC(0.000 ns) + CELL(2.800 ns) = 2.800 ns; Loc. = PIN_43; Fanout = 8; CLK Node = 'CLK'
            Info: 2: + IC(2.500 ns) + CELL(0.000 ns) = 5.300 ns; Loc. = LC1_A13; Fanout = 6; REG Node = 'lpm_counter:CNT4_rtl_0|alt_counter_f10ke:wysi_counter|q[0]'
            Info: Total cell delay = 2.800 ns ( 52.83 % )
            Info: Total interconnect delay = 2.500 ns ( 47.17 % )
    Info: + Micro clock to output delay of source is 1.100 ns
    Info: + Micro setup delay of destination is 2.500 ns
Info: tsu for register "lpm_counter:CNT4_rtl_0|alt_counter_f10ke:wysi_counter|q[3]" (data pin = "DATA[3]", clock pin = "CLK") is 3.400 ns
    Info: + Longest pin to register delay is 6.200 ns
        Info: 1: + IC(0.000 ns) + CELL(2.800 ns) = 2.800 ns; Loc. = PIN_42; Fanout = 1; PIN Node = 'DATA[3]'
        Info: 2: + IC(1.700 ns) + CELL(1.700 ns) = 6.200 ns; Loc. = LC4_A13; Fanout = 4; REG Node = 'lpm_counter:CNT4_rtl_0|alt_counter_f10ke:wysi_counter|q[3]'
        Info: Total cell delay = 4.500 ns ( 72.58 % )
        Info: Total interconnect delay = 1.700 ns ( 27.42 % )
    Info: + Micro setup delay of destination is 2.500 ns
    Info: - Shortest clock path from clock "CLK" to destination register is 5.300 ns
        Info: 1: + IC(0.000 ns) + CELL(2.800 ns) = 2.800 ns; Loc. = PIN_43; Fanout = 8; CLK Node = 'CLK'
        Info: 2: + IC(2.500 ns) + CELL(0.000 ns) = 5.300 ns; Loc. = LC4_A13; Fanout = 4; REG Node = 'lpm_counter:CNT4_rtl_0|alt_counter_f10ke:wysi_counter|q[3]'
        Info: Total cell delay = 2.800 ns ( 52.83 % )
        Info: Total interconnect delay = 2.500 ns ( 47.17 % )
Info: tco from clock "CLK" to destination pin "COUT" through register "COUT~reg0" is 13.200 ns
    Info: + Longest clock path from clock "CLK" to source register is 5.300 ns
        Info: 1: + IC(0.000 ns) + CELL(2.800 ns) = 2.800 ns; Loc. = PIN_43; Fanout = 8; CLK Node = 'CLK'
        Info: 2: + IC(2.500 ns) + CELL(0.000 ns) = 5.300 ns; Loc. = LC5_A13; Fanout = 1; REG Node = 'COUT~reg0'
        Info: Total cell delay = 2.800 ns ( 52.83 % )
        Info: Total interconnect delay = 2.500 ns ( 47.17 % )
    Info: + Micro clock to output delay of source is 1.100 ns
    Info: + Longest register to pin delay is 6.800 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC5_A13; Fanout = 1; REG Node = 'COUT~reg0'
        Info: 2: + IC(1.700 ns) + CELL(5.100 ns) = 6.800 ns; Loc. = PIN_70; Fanout = 0; PIN Node = 'COUT'
        Info: Total cell delay = 5.100 ns ( 75.00 % )
        Info: Total interconnect delay = 1.700 ns ( 25.00 % )
Info: th for register "lpm_counter:CNT4_rtl_0|alt_counter_f10ke:wysi_counter|q[3]" (data pin = "DATA[3]", clock pin = "CLK") is 0.700 ns
    Info: + Longest clock path from clock "CLK" to destination register is 5.300 ns
        Info: 1: + IC(0.000 ns) + CELL(2.800 ns) = 2.800 ns; Loc. = PIN_43; Fanout = 8; CLK Node = 'CLK'
        Info: 2: + IC(2.500 ns) + CELL(0.000 ns) = 5.300 ns; Loc. = LC4_A13; Fanout = 4; REG Node = 'lpm_counter:CNT4_rtl_0|alt_counter_f10ke:wysi_counter|q[3]'
        Info: Total cell delay = 2.800 ns ( 52.83 % )
        Info: Total interconnect delay = 2.500 ns ( 47.17 % )
    Info: + Micro hold delay of destination is 1.600 ns
    Info: - Shortest pin to register delay is 6.200 ns
        Info: 1: + IC(0.000 ns) + CELL(2.800 ns) = 2.800 ns; Loc. = PIN_42; Fanout = 1; PIN Node = 'DATA[3]'
        Info: 2: + IC(1.700 ns) + CELL(1.700 ns) = 6.200 ns; Loc. = LC4_A13; Fanout = 4; REG Node = 'lpm_counter:CNT4_rtl_0|alt_counter_f10ke:wysi_counter|q[3]'
        Info: Total cell delay = 4.500 ns ( 72.58 % )
        Info: Total interconnect delay = 1.700 ns ( 27.42 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning
    Info: Processing ended: Fri Apr 14 19:46:23 2006
    Info: Elapsed time: 00:00:06