divf.tan.summary

来自「在EDA开发软件QuartusII上利用VHDL语言实现DDS信号发生器」· SUMMARY 代码 · 共 57 行

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Timing Analyzer Summary
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Type           : Worst-case tsu
Slack          : N/A
Required Time  : None
Actual Time    : 3.400 ns
From           : DATA[0]
To             : lpm_counter:CNT4_rtl_0|alt_counter_f10ke:wysi_counter|q[0]
From Clock     : 
To Clock       : CLK
Failed Paths   : 0

Type           : Worst-case tco
Slack          : N/A
Required Time  : None
Actual Time    : 13.200 ns
From           : lpm_counter:CNT4_rtl_0|alt_counter_f10ke:wysi_counter|q[0]
To             : FOUT[0]
From Clock     : CLK
To Clock       : 
Failed Paths   : 0

Type           : Worst-case th
Slack          : N/A
Required Time  : None
Actual Time    : 0.700 ns
From           : DATA[0]
To             : lpm_counter:CNT4_rtl_0|alt_counter_f10ke:wysi_counter|q[0]
From Clock     : 
To Clock       : CLK
Failed Paths   : 0

Type           : Clock Setup: 'CLK'
Slack          : N/A
Required Time  : None
Actual Time    : 120.48 MHz ( period = 8.300 ns )
From           : lpm_counter:CNT4_rtl_0|alt_counter_f10ke:wysi_counter|q[2]
To             : lpm_counter:CNT4_rtl_0|alt_counter_f10ke:wysi_counter|q[0]
From Clock     : CLK
To Clock       : CLK
Failed Paths   : 0

Type           : Total number of failed paths
Slack          : 
Required Time  : 
Actual Time    : 
From           : 
To             : 
From Clock     : 
To Clock       : 
Failed Paths   : 0

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