divf.map.eqn

来自「在EDA开发软件QuartusII上利用VHDL语言实现DDS信号发生器」· EQN 代码 · 共 160 行

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--C1_q[0] is lpm_counter:CNT4_rtl_0|alt_counter_f10ke:wysi_counter|q[0]
--operation mode is up_dn_cntr

C1_q[0]_lut_out = (!C1_q[0] & A1L51) # (DATA[0] & !A1L51);
C1_q[0] = DFFEA(C1_q[0]_lut_out, CLK, , , , , );

--C1L11Q is lpm_counter:CNT4_rtl_0|alt_counter_f10ke:wysi_counter|q[0]~0
--operation mode is up_dn_cntr

C1L11Q = C1_q[0];

--C1L3 is lpm_counter:CNT4_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[0]~COUT
--operation mode is up_dn_cntr

C1L3 = CARRY(C1_q[0]);


--C1_q[1] is lpm_counter:CNT4_rtl_0|alt_counter_f10ke:wysi_counter|q[1]
--operation mode is up_dn_cntr

C1_q[1]_lut_out = (C1_q[1] $ C1L3 & A1L51) # (DATA[1] & !A1L51);
C1_q[1] = DFFEA(C1_q[1]_lut_out, CLK, , , , , );

--C1L31Q is lpm_counter:CNT4_rtl_0|alt_counter_f10ke:wysi_counter|q[1]~1
--operation mode is up_dn_cntr

C1L31Q = C1_q[1];

--C1L5 is lpm_counter:CNT4_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[1]~COUT
--operation mode is up_dn_cntr

C1L5 = CARRY(C1_q[1] & (C1L3));


--C1_q[2] is lpm_counter:CNT4_rtl_0|alt_counter_f10ke:wysi_counter|q[2]
--operation mode is up_dn_cntr

C1_q[2]_lut_out = (C1_q[2] $ C1L5 & A1L51) # (DATA[2] & !A1L51);
C1_q[2] = DFFEA(C1_q[2]_lut_out, CLK, , , , , );

--C1L51Q is lpm_counter:CNT4_rtl_0|alt_counter_f10ke:wysi_counter|q[2]~2
--operation mode is up_dn_cntr

C1L51Q = C1_q[2];

--C1L7 is lpm_counter:CNT4_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[2]~COUT
--operation mode is up_dn_cntr

C1L7 = CARRY(C1_q[2] & (C1L5));


--C1_q[3] is lpm_counter:CNT4_rtl_0|alt_counter_f10ke:wysi_counter|q[3]
--operation mode is up_dn_cntr

C1_q[3]_lut_out = (C1_q[3] $ C1L7 & A1L51) # (DATA[3] & !A1L51);
C1_q[3] = DFFEA(C1_q[3]_lut_out, CLK, , , , , );

--C1L71Q is lpm_counter:CNT4_rtl_0|alt_counter_f10ke:wysi_counter|q[3]~3
--operation mode is up_dn_cntr

C1L71Q = C1_q[3];


--A1L4Q is COUT~reg0
--operation mode is normal

A1L4Q_lut_out = C1_q[0] & C1_q[1] & C1_q[2] & C1_q[3];
A1L4Q = DFFEA(A1L4Q_lut_out, CLK, , , , , );

--A1L3Q is COUT~0
--operation mode is normal

A1L3Q = A1L4Q;


--A1L51 is LessThan~34
--operation mode is normal

A1L51 = !C1_q[3] # !C1_q[2] # !C1_q[1] # !C1_q[0];

--A1L61 is LessThan~36
--operation mode is normal

A1L61 = !C1_q[3] # !C1_q[2] # !C1_q[1] # !C1_q[0];


--DATA[0] is DATA[0]
--operation mode is input

DATA[0] = INPUT();


--CLK is CLK
--operation mode is input

CLK = INPUT();


--DATA[1] is DATA[1]
--operation mode is input

DATA[1] = INPUT();


--DATA[2] is DATA[2]
--operation mode is input

DATA[2] = INPUT();


--DATA[3] is DATA[3]
--operation mode is input

DATA[3] = INPUT();


--FOUT[0] is FOUT[0]
--operation mode is output

FOUT[0] = OUTPUT(C1_q[0]);


--FOUT[1] is FOUT[1]
--operation mode is output

FOUT[1] = OUTPUT(C1_q[1]);


--FOUT[2] is FOUT[2]
--operation mode is output

FOUT[2] = OUTPUT(C1_q[2]);


--FOUT[3] is FOUT[3]
--operation mode is output

FOUT[3] = OUTPUT(C1_q[3]);


--COUT is COUT
--operation mode is output

COUT = OUTPUT(A1L4Q);