data_rom.tan.qmsg

在EDA开发软件QuartusII上利用VHDL语言实现DDS信号发生器

{ "Info" "ITAN_NO_REG2REG_EXIST" "inclock " "Info: No valid register-to-register data paths exist for clock \"inclock\"" {  } {  } 0}
{ "Info" "ITDB_TSU_RESULT" "lpm_rom:lpm_rom_component\|altrom:srom\|q\[0\]~reg_ra6 address\[6\] inclock 2.800 ns memory " "Info: tsu for memory \"lpm_rom:lpm_rom_component\|altrom:srom\|q\[0\]~reg_ra6\" (data pin = \"address\[6\]\", clock pin = \"inclock\") is 2.800 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.300 ns + Longest pin memory " "Info: + Longest pin to memory delay is 6.300 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.500 ns) 3.500 ns address\[6\] 1 PIN PIN_17 8 " "Info: 1: + IC(0.000 ns) + CELL(3.500 ns) = 3.500 ns; Loc. = PIN_17; Fanout = 8; PIN Node = 'address\[6\]'" {  } { { "E:/EDA/DDS/10k844/rom_10k/db/data_rom_cmp.qrpt" "" { Report "E:/EDA/DDS/10k844/rom_10k/db/data_rom_cmp.qrpt" Compiler "data_rom" "UNKNOWN" "V1" "E:/EDA/DDS/10k844/rom_10k/db/data_rom.quartus_db" { Floorplan "E:/EDA/DDS/10k844/rom_10k/" "" "" { address[6] } "NODE_NAME" } "" } } { "data_rom.vhd" "" { Text "E:/EDA/DDS/10k844/rom_10k/data_rom.vhd" 42 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.800 ns) + CELL(0.000 ns) 6.300 ns lpm_rom:lpm_rom_component\|altrom:srom\|q\[0\]~reg_ra6 2 MEM EC3_A 1 " "Info: 2: + IC(2.800 ns) + CELL(0.000 ns) = 6.300 ns; Loc. = EC3_A; Fanout = 1; MEM Node = 'lpm_rom:lpm_rom_component\|altrom:srom\|q\[0\]~reg_ra6'" {  } { { "E:/EDA/DDS/10k844/rom_10k/db/data_rom_cmp.qrpt" "" { Report "E:/EDA/DDS/10k844/rom_10k/db/data_rom_cmp.qrpt" Compiler "data_rom" "UNKNOWN" "V1" "E:/EDA/DDS/10k844/rom_10k/db/data_rom.quartus_db" { Floorplan "E:/EDA/DDS/10k844/rom_10k/" "" "2.800 ns" { address[6] lpm_rom:lpm_rom_component|altrom:srom|q[0]~reg_ra6 } "NODE_NAME" } "" } } { "altrom.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/altrom.tdf" 80 2 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.500 ns 55.56 % " "Info: Total cell delay = 3.500 ns ( 55.56 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.800 ns 44.44 % " "Info: Total interconnect delay = 2.800 ns ( 44.44 % )" {  } {  } 0}  } { { "E:/EDA/DDS/10k844/rom_10k/db/data_rom_cmp.qrpt" "" { Report "E:/EDA/DDS/10k844/rom_10k/db/data_rom_cmp.qrpt" Compiler "data_rom" "UNKNOWN" "V1" "E:/EDA/DDS/10k844/rom_10k/db/data_rom.quartus_db" { Floorplan "E:/EDA/DDS/10k844/rom_10k/" "" "6.300 ns" { address[6] lpm_rom:lpm_rom_component|altrom:srom|q[0]~reg_ra6 } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "6.300 ns" { address[6] address[6]~out lpm_rom:lpm_rom_component|altrom:srom|q[0]~reg_ra6 } { 0.000ns 0.000ns 2.800ns } { 0.000ns 3.500ns 0.000ns } } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "1.800 ns + " "Info: + Micro setup delay of destination is 1.800 ns" {  } { { "altrom.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/altrom.tdf" 80 2 0 } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "inclock destination 5.300 ns - Shortest memory " "Info: - Shortest clock path from clock \"inclock\" to destination memory is 5.300 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.800 ns) 2.800 ns inclock 1 CLK PIN_43 56 " "Info: 1: + IC(0.000 ns) + CELL(2.800 ns) = 2.800 ns; Loc. = PIN_43; Fanout = 56; CLK Node = 'inclock'" {  } { { "E:/EDA/DDS/10k844/rom_10k/db/data_rom_cmp.qrpt" "" { Report "E:/EDA/DDS/10k844/rom_10k/db/data_rom_cmp.qrpt" Compiler "data_rom" "UNKNOWN" "V1" "E:/EDA/DDS/10k844/rom_10k/db/data_rom.quartus_db" { Floorplan "E:/EDA/DDS/10k844/rom_10k/" "" "" { inclock } "NODE_NAME" } "" } } { "data_rom.vhd" "" { Text "E:/EDA/DDS/10k844/rom_10k/data_rom.vhd" 43 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.500 ns) + CELL(0.000 ns) 5.300 ns lpm_rom:lpm_rom_component\|altrom:srom\|q\[0\]~reg_ra6 2 MEM EC3_A 1 " "Info: 2: + IC(2.500 ns) + CELL(0.000 ns) = 5.300 ns; Loc. = EC3_A; Fanout = 1; MEM Node = 'lpm_rom:lpm_rom_component\|altrom:srom\|q\[0\]~reg_ra6'" {  } { { "E:/EDA/DDS/10k844/rom_10k/db/data_rom_cmp.qrpt" "" { Report "E:/EDA/DDS/10k844/rom_10k/db/data_rom_cmp.qrpt" Compiler "data_rom" "UNKNOWN" "V1" "E:/EDA/DDS/10k844/rom_10k/db/data_rom.quartus_db" { Floorplan "E:/EDA/DDS/10k844/rom_10k/" "" "2.500 ns" { inclock lpm_rom:lpm_rom_component|altrom:srom|q[0]~reg_ra6 } "NODE_NAME" } "" } } { "altrom.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/altrom.tdf" 80 2 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.800 ns 52.83 % " "Info: Total cell delay = 2.800 ns ( 52.83 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.500 ns 47.17 % " "Info: Total interconnect delay = 2.500 ns ( 47.17 % )" {  } {  } 0}  } { { "E:/EDA/DDS/10k844/rom_10k/db/data_rom_cmp.qrpt" "" { Report "E:/EDA/DDS/10k844/rom_10k/db/data_rom_cmp.qrpt" Compiler "data_rom" "UNKNOWN" "V1" "E:/EDA/DDS/10k844/rom_10k/db/data_rom.quartus_db" { Floorplan "E:/EDA/DDS/10k844/rom_10k/" "" "5.300 ns" { inclock lpm_rom:lpm_rom_component|altrom:srom|q[0]~reg_ra6 } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "5.300 ns" { inclock inclock~out lpm_rom:lpm_rom_component|altrom:srom|q[0]~reg_ra6 } { 0.000ns 0.000ns 2.500ns } { 0.000ns 2.800ns 0.000ns } } }  } 0}  } { { "E:/EDA/DDS/10k844/rom_10k/db/data_rom_cmp.qrpt" "" { Report "E:/EDA/DDS/10k844/rom_10k/db/data_rom_cmp.qrpt" Compiler "data_rom" "UNKNOWN" "V1" "E:/EDA/DDS/10k844/rom_10k/db/data_rom.quartus_db" { Floorplan "E:/EDA/DDS/10k844/rom_10k/" "" "6.300 ns" { address[6] lpm_rom:lpm_rom_component|altrom:srom|q[0]~reg_ra6 } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "6.300 ns" { address[6] address[6]~out lpm_rom:lpm_rom_component|altrom:srom|q[0]~reg_ra6 } { 0.000ns 0.000ns 2.800ns } { 0.000ns 3.500ns 0.000ns } } } { "E:/EDA/DDS/10k844/rom_10k/db/data_rom_cmp.qrpt" "" { Report "E:/EDA/DDS/10k844/rom_10k/db/data_rom_cmp.qrpt" Compiler "data_rom" "UNKNOWN" "V1" "E:/EDA/DDS/10k844/rom_10k/db/data_rom.quartus_db" { Floorplan "E:/EDA/DDS/10k844/rom_10k/" "" "5.300 ns" { inclock lpm_rom:lpm_rom_component|altrom:srom|q[0]~reg_ra6 } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "5.300 ns" { inclock inclock~out lpm_rom:lpm_rom_component|altrom:srom|q[0]~reg_ra6 } { 0.000ns 0.000ns 2.500ns } { 0.000ns 2.800ns 0.000ns } } }  } 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "inclock q\[7\] lpm_rom:lpm_rom_component\|altrom:srom\|q\[7\]~reg_ra0 29.400 ns memory " "Info: tco from clock \"inclock\" to destination pin \"q\[7\]\" through memory \"lpm_rom:lpm_rom_component\|altrom:srom\|q\[7\]~reg_ra0\" is 29.400 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "inclock source 5.300 ns + Longest memory " "Info: + Longest clock path from clock \"inclock\" to source memory is 5.300 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.800 ns) 2.800 ns inclock 1 CLK PIN_43 56 " "Info: 1: + IC(0.000 ns) + CELL(2.800 ns) = 2.800 ns; Loc. = PIN_43; Fanout = 56; CLK Node = 'inclock'" {  } { { "E:/EDA/DDS/10k844/rom_10k/db/data_rom_cmp.qrpt" "" { Report "E:/EDA/DDS/10k844/rom_10k/db/data_rom_cmp.qrpt" Compiler "data_rom" "UNKNOWN" "V1" "E:/EDA/DDS/10k844/rom_10k/db/data_rom.quartus_db" { Floorplan "E:/EDA/DDS/10k844/rom_10k/" "" "" { inclock } "NODE_NAME" } "" } } { "data_rom.vhd" "" { Text "E:/EDA/DDS/10k844/rom_10k/data_rom.vhd" 43 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.500 ns) + CELL(0.000 ns) 5.300 ns lpm_rom:lpm_rom_component\|altrom:srom\|q\[7\]~reg_ra0 2 MEM EC7_A 1 " "Info: 2: + IC(2.500 ns) + CELL(0.000 ns) = 5.300 ns; Loc. = EC7_A; Fanout = 1; MEM Node = 'lpm_rom:lpm_rom_component\|altrom:srom\|q\[7\]~reg_ra0'" {  } { { "E:/EDA/DDS/10k844/rom_10k/db/data_rom_cmp.qrpt" "" { Report "E:/EDA/DDS/10k844/rom_10k/db/data_rom_cmp.qrpt" Compiler "data_rom" "UNKNOWN" "V1" "E:/EDA/DDS/10k844/rom_10k/db/data_rom.quartus_db" { Floorplan "E:/EDA/DDS/10k844/rom_10k/" "" "2.500 ns" { inclock lpm_rom:lpm_rom_component|altrom:srom|q[7]~reg_ra0 } "NODE_NAME" } "" } } { "altrom.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/altrom.tdf" 80 2 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.800 ns 52.83 % " "Info: Total cell delay = 2.800 ns ( 52.83 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.500 ns 47.17 % " "Info: Total interconnect delay = 2.500 ns ( 47.17 % )" {  } {  } 0}  } { { "E:/EDA/DDS/10k844/rom_10k/db/data_rom_cmp.qrpt" "" { Report "E:/EDA/DDS/10k844/rom_10k/db/data_rom_cmp.qrpt" Compiler "data_rom" "UNKNOWN" "V1" "E:/EDA/DDS/10k844/rom_10k/db/data_rom.quartus_db" { Floorplan "E:/EDA/DDS/10k844/rom_10k/" "" "5.300 ns" { inclock lpm_rom:lpm_rom_component|altrom:srom|q[7]~reg_ra0 } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "5.300 ns" { inclock inclock~out lpm_rom:lpm_rom_component|altrom:srom|q[7]~reg_ra0 } { 0.000ns 0.000ns 2.500ns } { 0.000ns 2.800ns 0.000ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.600 ns + " "Info: + Micro clock to output delay of source is 0.600 ns" {  } { { "altrom.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/altrom.tdf" 80 2 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "23.500 ns + Longest memory pin " "Info: + Longest memory to pin delay is 23.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns lpm_rom:lpm_rom_component\|altrom:srom\|q\[7\]~reg_ra0 1 MEM EC7_A 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = EC7_A; Fanout = 1; MEM Node = 'lpm_rom:lpm_rom_component\|altrom:srom\|q\[7\]~reg_ra0'" {  } { { "E:/EDA/DDS/10k844/rom_10k/db/data_rom_cmp.qrpt" "" { Report "E:/EDA/DDS/10k844/rom_10k/db/data_rom_cmp.qrpt" Compiler "data_rom" "UNKNOWN" "V1" "E:/EDA/DDS/10k844/rom_10k/db/data_rom.quartus_db" { Floorplan "E:/EDA/DDS/10k844/rom_10k/" "" "" { lpm_rom:lpm_rom_component|altrom:srom|q[7]~reg_ra0 } "NODE_NAME" } "" } } { "altrom.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/altrom.tdf" 80 2 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(10.700 ns) 10.700 ns lpm_rom:lpm_rom_component\|altrom:srom\|q\[7\]~mem_cell_ra0 2 MEM EC7_A 1 " "Info: 2: + IC(0.000 ns) + CELL(10.700 ns) = 10.700 ns; Loc. = EC7_A; Fanout = 1; MEM Node = 'lpm_rom:lpm_rom_component\|altrom:srom\|q\[7\]~mem_cell_ra0'" {  } { { "E:/EDA/DDS/10k844/rom_10k/db/data_rom_cmp.qrpt" "" { Report "E:/EDA/DDS/10k844/rom_10k/db/data_rom_cmp.qrpt" Compiler "data_rom" "UNKNOWN" "V1" "E:/EDA/DDS/10k844/rom_10k/db/data_rom.quartus_db" { Floorplan "E:/EDA/DDS/10k844/rom_10k/" "" "10.700 ns" { lpm_rom:lpm_rom_component|altrom:srom|q[7]~reg_ra0 lpm_rom:lpm_rom_component|altrom:srom|q[7]~mem_cell_ra0 } "NODE_NAME" } "" } } { "altrom.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/altrom.tdf" 80 2 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.500 ns) 13.200 ns lpm_rom:lpm_rom_component\|altrom:srom\|q\[7\] 3 MEM EC7_A 1 " "Info: 3: + IC(0.000 ns) + CELL(2.500 ns) = 13.200 ns; Loc. = EC7_A; Fanout = 1; MEM Node = 'lpm_rom:lpm_rom_component\|altrom:srom\|q\[7\]'" {  } { { "E:/EDA/DDS/10k844/rom_10k/db/data_rom_cmp.qrpt" "" { Report "E:/EDA/DDS/10k844/rom_10k/db/data_rom_cmp.qrpt" Compiler "data_rom" "UNKNOWN" "V1" "E:/EDA/DDS/10k844/rom_10k/db/data_rom.quartus_db" { Floorplan "E:/EDA/DDS/10k844/rom_10k/" "" "2.500 ns" { lpm_rom:lpm_rom_component|altrom:srom|q[7]~mem_cell_ra0 lpm_rom:lpm_rom_component|altrom:srom|q[7] } "NODE_NAME" } "" } } { "altrom.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/altrom.tdf" 80 2 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(5.200 ns) + CELL(5.100 ns) 23.500 ns q\[7\] 4 PIN PIN_60 0 " "Info: 4: + IC(5.200 ns) + CELL(5.100 ns) = 23.500 ns; Loc. = PIN_60; Fanout = 0; PIN Node = 'q\[7\]'" {  } { { "E:/EDA/DDS/10k844/rom_10k/db/data_rom_cmp.qrpt" "" { Report "E:/EDA/DDS/10k844/rom_10k/db/data_rom_cmp.qrpt" Compiler "data_rom" "UNKNOWN" "V1" "E:/EDA/DDS/10k844/rom_10k/db/data_rom.quartus_db" { Floorplan "E:/EDA/DDS/10k844/rom_10k/" "" "10.300 ns" { lpm_rom:lpm_rom_component|altrom:srom|q[7] q[7] } "NODE_NAME" } "" } } { "data_rom.vhd" "" { Text "E:/EDA/DDS/10k844/rom_10k/data_rom.vhd" 44 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "18.300 ns 77.87 % " "Info: Total cell delay = 18.300 ns ( 77.87 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.200 ns 22.13 % " "Info: Total interconnect delay = 5.200 ns ( 22.13 % )" {  } {  } 0}  } { { "E:/EDA/DDS/10k844/rom_10k/db/data_rom_cmp.qrpt" "" { Report "E:/EDA/DDS/10k844/rom_10k/db/data_rom_cmp.qrpt" Compiler "data_rom" "UNKNOWN" "V1" "E:/EDA/DDS/10k844/rom_10k/db/data_rom.quartus_db" { Floorplan "E:/EDA/DDS/10k844/rom_10k/" "" "23.500 ns" { lpm_rom:lpm_rom_component|altrom:srom|q[7]~reg_ra0 lpm_rom:lpm_rom_component|altrom:srom|q[7]~mem_cell_ra0 lpm_rom:lpm_rom_component|altrom:srom|q[7] q[7] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "23.500 ns" { lpm_rom:lpm_rom_component|altrom:srom|q[7]~reg_ra0 lpm_rom:lpm_rom_component|altrom:srom|q[7]~mem_cell_ra0 lpm_rom:lpm_rom_component|altrom:srom|q[7] q[7] } { 0.000ns 0.000ns 0.000ns 5.200ns } { 0.000ns 10.700ns 2.500ns 5.100ns } } }  } 0}  } { { "E:/EDA/DDS/10k844/rom_10k/db/data_rom_cmp.qrpt" "" { Report "E:/EDA/DDS/10k844/rom_10k/db/data_rom_cmp.qrpt" Compiler "data_rom" "UNKNOWN" "V1" "E:/EDA/DDS/10k844/rom_10k/db/data_rom.quartus_db" { Floorplan "E:/EDA/DDS/10k844/rom_10k/" "" "5.300 ns" { inclock lpm_rom:lpm_rom_component|altrom:srom|q[7]~reg_ra0 } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "5.300 ns" { inclock inclock~out lpm_rom:lpm_rom_component|altrom:srom|q[7]~reg_ra0 } { 0.000ns 0.000ns 2.500ns } { 0.000ns 2.800ns 0.000ns } } } { "E:/EDA/DDS/10k844/rom_10k/db/data_rom_cmp.qrpt" "" { Report "E:/EDA/DDS/10k844/rom_10k/db/data_rom_cmp.qrpt" Compiler "data_rom" "UNKNOWN" "V1" "E:/EDA/DDS/10k844/rom_10k/db/data_rom.quartus_db" { Floorplan "E:/EDA/DDS/10k844/rom_10k/" "" "23.500 ns" { lpm_rom:lpm_rom_component|altrom:srom|q[7]~reg_ra0 lpm_rom:lpm_rom_component|altrom:srom|q[7]~mem_cell_ra0 lpm_rom:lpm_rom_component|altrom:srom|q[7] q[7] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "23.500 ns" { lpm_rom:lpm_rom_component|altrom:srom|q[7]~reg_ra0 lpm_rom:lpm_rom_component|altrom:srom|q[7]~mem_cell_ra0 lpm_rom:lpm_rom_component|altrom:srom|q[7] q[7] } { 0.000ns 0.000ns 0.000ns 5.200ns } { 0.000ns 10.700ns 2.500ns 5.100ns } } }  } 0}
{ "Info" "ITDB_TH_RESULT" "lpm_rom:lpm_rom_component\|altrom:srom\|q\[0\]~reg_ra4 address\[4\] inclock 3.300 ns memory " "Info: th for memory \"lpm_rom:lpm_rom_component\|altrom:srom\|q\[0\]~reg_ra4\" (data pin = \"address\[4\]\", clock pin = \"inclock\") is 3.300 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "inclock destination 5.300 ns + Longest memory " "Info: + Longest clock path from clock \"inclock\" to destination memory is 5.300 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.800 ns) 2.800 ns inclock 1 CLK PIN_43 56 " "Info: 1: + IC(0.000 ns) + CELL(2.800 ns) = 2.800 ns; Loc. = PIN_43; Fanout = 56; CLK Node = 'inclock'" {  } { { "E:/EDA/DDS/10k844/rom_10k/db/data_rom_cmp.qrpt" "" { Report "E:/EDA/DDS/10k844/rom_10k/db/data_rom_cmp.qrpt" Compiler "data_rom" "UNKNOWN" "V1" "E:/EDA/DDS/10k844/rom_10k/db/data_rom.quartus_db" { Floorplan "E:/EDA/DDS/10k844/rom_10k/" "" "" { inclock } "NODE_NAME" } "" } } { "data_rom.vhd" "" { Text "E:/EDA/DDS/10k844/rom_10k/data_rom.vhd" 43 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.500 ns) + CELL(0.000 ns) 5.300 ns lpm_rom:lpm_rom_component\|altrom:srom\|q\[0\]~reg_ra4 2 MEM EC3_A 1 " "Info: 2: + IC(2.500 ns) + CELL(0.000 ns) = 5.300 ns; Loc. = EC3_A; Fanout = 1; MEM Node = 'lpm_rom:lpm_rom_component\|altrom:srom\|q\[0\]~reg_ra4'" {  } { { "E:/EDA/DDS/10k844/rom_10k/db/data_rom_cmp.qrpt" "" { Report "E:/EDA/DDS/10k844/rom_10k/db/data_rom_cmp.qrpt" Compiler "data_rom" "UNKNOWN" "V1" "E:/EDA/DDS/10k844/rom_10k/db/data_rom.quartus_db" { Floorplan "E:/EDA/DDS/10k844/rom_10k/" "" "2.500 ns" { inclock lpm_rom:lpm_rom_component|altrom:srom|q[0]~reg_ra4 } "NODE_NAME" } "" } } { "altrom.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/altrom.tdf" 80 2 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.800 ns 52.83 % " "Info: Total cell delay = 2.800 ns ( 52.83 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.500 ns 47.17 % " "Info: Total interconnect delay = 2.500 ns ( 47.17 % )" {  } {  } 0}  } { { "E:/EDA/DDS/10k844/rom_10k/db/data_rom_cmp.qrpt" "" { Report "E:/EDA/DDS/10k844/rom_10k/db/data_rom_cmp.qrpt" Compiler "data_rom" "UNKNOWN" "V1" "E:/EDA/DDS/10k844/rom_10k/db/data_rom.quartus_db" { Floorplan "E:/EDA/DDS/10k844/rom_10k/" "" "5.300 ns" { inclock lpm_rom:lpm_rom_component|altrom:srom|q[0]~reg_ra4 } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "5.300 ns" { inclock inclock~out lpm_rom:lpm_rom_component|altrom:srom|q[0]~reg_ra4 } { 0.000ns 0.000ns 2.500ns } { 0.000ns 2.800ns 0.000ns } } }  } 0} { "Info" "ITDB_FULL_TH_DELAY" "2.500 ns + " "Info: + Micro hold delay of destination is 2.500 ns" {  } { { "altrom.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/altrom.tdf" 80 2 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.500 ns - Shortest pin memory " "Info: - Shortest pin to memory delay is 4.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.800 ns) 2.800 ns address\[4\] 1 PIN PIN_1 8 " "Info: 1: + IC(0.000 ns) + CELL(2.800 ns) = 2.800 ns; Loc. = PIN_1; Fanout = 8; PIN Node = 'address\[4\]'" {  } { { "E:/EDA/DDS/10k844/rom_10k/db/data_rom_cmp.qrpt" "" { Report "E:/EDA/DDS/10k844/rom_10k/db/data_rom_cmp.qrpt" Compiler "data_rom" "UNKNOWN" "V1" "E:/EDA/DDS/10k844/rom_10k/db/data_rom.quartus_db" { Floorplan "E:/EDA/DDS/10k844/rom_10k/" "" "" { address[4] } "NODE_NAME" } "" } } { "data_rom.vhd" "" { Text "E:/EDA/DDS/10k844/rom_10k/data_rom.vhd" 42 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.700 ns) + CELL(0.000 ns) 4.500 ns lpm_rom:lpm_rom_component\|altrom:srom\|q\[0\]~reg_ra4 2 MEM EC3_A 1 " "Info: 2: + IC(1.700 ns) + CELL(0.000 ns) = 4.500 ns; Loc. = EC3_A; Fanout = 1; MEM Node = 'lpm_rom:lpm_rom_component\|altrom:srom\|q\[0\]~reg_ra4'" {  } { { "E:/EDA/DDS/10k844/rom_10k/db/data_rom_cmp.qrpt" "" { Report "E:/EDA/DDS/10k844/rom_10k/db/data_rom_cmp.qrpt" Compiler "data_rom" "UNKNOWN" "V1" "E:/EDA/DDS/10k844/rom_10k/db/data_rom.quartus_db" { Floorplan "E:/EDA/DDS/10k844/rom_10k/" "" "1.700 ns" { address[4] lpm_rom:lpm_rom_component|altrom:srom|q[0]~reg_ra4 } "NODE_NAME" } "" } } { "altrom.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/altrom.tdf" 80 2 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.800 ns 62.22 % " "Info: Total cell delay = 2.800 ns ( 62.22 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.700 ns 37.78 % " "Info: Total interconnect delay = 1.700 ns ( 37.78 % )" {  } {  } 0}  } { { "E:/EDA/DDS/10k844/rom_10k/db/data_rom_cmp.qrpt" "" { Report "E:/EDA/DDS/10k844/rom_10k/db/data_rom_cmp.qrpt" Compiler "data_rom" "UNKNOWN" "V1" "E:/EDA/DDS/10k844/rom_10k/db/data_rom.quartus_db" { Floorplan "E:/EDA/DDS/10k844/rom_10k/" "" "4.500 ns" { address[4] lpm_rom:lpm_rom_component|altrom:srom|q[0]~reg_ra4 } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "4.500 ns" { address[4] address[4]~out lpm_rom:lpm_rom_component|altrom:srom|q[0]~reg_ra4 } { 0.000ns 0.000ns 1.700ns } { 0.000ns 2.800ns 0.000ns } } }  } 0}  } { { "E:/EDA/DDS/10k844/rom_10k/db/data_rom_cmp.qrpt" "" { Report "E:/EDA/DDS/10k844/rom_10k/db/data_rom_cmp.qrpt" Compiler "data_rom" "UNKNOWN" "V1" "E:/EDA/DDS/10k844/rom_10k/db/data_rom.quartus_db" { Floorplan "E:/EDA/DDS/10k844/rom_10k/" "" "5.300 ns" { inclock lpm_rom:lpm_rom_component|altrom:srom|q[0]~reg_ra4 } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "5.300 ns" { inclock inclock~out lpm_rom:lpm_rom_component|altrom:srom|q[0]~reg_ra4 } { 0.000ns 0.000ns 2.500ns } { 0.000ns 2.800ns 0.000ns } } } { "E:/EDA/DDS/10k844/rom_10k/db/data_rom_cmp.qrpt" "" { Report "E:/EDA/DDS/10k844/rom_10k/db/data_rom_cmp.qrpt" Compiler "data_rom" "UNKNOWN" "V1" "E:/EDA/DDS/10k844/rom_10k/db/data_rom.quartus_db" { Floorplan "E:/EDA/DDS/10k844/rom_10k/" "" "4.500 ns" { address[4] lpm_rom:lpm_rom_component|altrom:srom|q[0]~reg_ra4 } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "4.500 ns" { address[4] address[4]~out lpm_rom:lpm_rom_component|altrom:srom|q[0]~reg_ra4 } { 0.000ns 0.000ns 1.700ns } { 0.000ns 2.800ns 0.000ns } } }  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 1  Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Sat Apr 15 20:43:21 2006 " "Info: Processing ended: Sat Apr 15 20:43:21 2006" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Info: Elapsed time: 00:00:03" {  } {  } 0}  } {  } 0}