data_rom.tan.rpt

在EDA开发软件QuartusII上利用VHDL语言实现DDS信号发生器

; N/A           ; None        ; 3.300 ns  ; address[4] ; lpm_rom:lpm_rom_component|altrom:srom|q[5]~reg_ra4 ; inclock  ;
; N/A           ; None        ; 3.300 ns  ; address[4] ; lpm_rom:lpm_rom_component|altrom:srom|q[6]~reg_ra4 ; inclock  ;
; N/A           ; None        ; 3.300 ns  ; address[4] ; lpm_rom:lpm_rom_component|altrom:srom|q[7]~reg_ra4 ; inclock  ;
; N/A           ; None        ; 3.300 ns  ; address[3] ; lpm_rom:lpm_rom_component|altrom:srom|q[0]~reg_ra3 ; inclock  ;
; N/A           ; None        ; 3.300 ns  ; address[3] ; lpm_rom:lpm_rom_component|altrom:srom|q[1]~reg_ra3 ; inclock  ;
; N/A           ; None        ; 3.300 ns  ; address[3] ; lpm_rom:lpm_rom_component|altrom:srom|q[2]~reg_ra3 ; inclock  ;
; N/A           ; None        ; 3.300 ns  ; address[3] ; lpm_rom:lpm_rom_component|altrom:srom|q[3]~reg_ra3 ; inclock  ;
; N/A           ; None        ; 3.300 ns  ; address[3] ; lpm_rom:lpm_rom_component|altrom:srom|q[4]~reg_ra3 ; inclock  ;
; N/A           ; None        ; 3.300 ns  ; address[3] ; lpm_rom:lpm_rom_component|altrom:srom|q[5]~reg_ra3 ; inclock  ;
; N/A           ; None        ; 3.300 ns  ; address[3] ; lpm_rom:lpm_rom_component|altrom:srom|q[6]~reg_ra3 ; inclock  ;
; N/A           ; None        ; 3.300 ns  ; address[3] ; lpm_rom:lpm_rom_component|altrom:srom|q[7]~reg_ra3 ; inclock  ;
; N/A           ; None        ; 3.300 ns  ; address[2] ; lpm_rom:lpm_rom_component|altrom:srom|q[0]~reg_ra2 ; inclock  ;
; N/A           ; None        ; 3.300 ns  ; address[2] ; lpm_rom:lpm_rom_component|altrom:srom|q[1]~reg_ra2 ; inclock  ;
; N/A           ; None        ; 3.300 ns  ; address[2] ; lpm_rom:lpm_rom_component|altrom:srom|q[2]~reg_ra2 ; inclock  ;
; N/A           ; None        ; 3.300 ns  ; address[2] ; lpm_rom:lpm_rom_component|altrom:srom|q[3]~reg_ra2 ; inclock  ;
; N/A           ; None        ; 3.300 ns  ; address[2] ; lpm_rom:lpm_rom_component|altrom:srom|q[4]~reg_ra2 ; inclock  ;
; N/A           ; None        ; 3.300 ns  ; address[2] ; lpm_rom:lpm_rom_component|altrom:srom|q[5]~reg_ra2 ; inclock  ;
; N/A           ; None        ; 3.300 ns  ; address[2] ; lpm_rom:lpm_rom_component|altrom:srom|q[6]~reg_ra2 ; inclock  ;
; N/A           ; None        ; 3.300 ns  ; address[2] ; lpm_rom:lpm_rom_component|altrom:srom|q[7]~reg_ra2 ; inclock  ;
; N/A           ; None        ; 3.300 ns  ; address[1] ; lpm_rom:lpm_rom_component|altrom:srom|q[0]~reg_ra1 ; inclock  ;
; N/A           ; None        ; 3.300 ns  ; address[1] ; lpm_rom:lpm_rom_component|altrom:srom|q[1]~reg_ra1 ; inclock  ;
; N/A           ; None        ; 3.300 ns  ; address[1] ; lpm_rom:lpm_rom_component|altrom:srom|q[2]~reg_ra1 ; inclock  ;
; N/A           ; None        ; 3.300 ns  ; address[1] ; lpm_rom:lpm_rom_component|altrom:srom|q[3]~reg_ra1 ; inclock  ;
; N/A           ; None        ; 3.300 ns  ; address[1] ; lpm_rom:lpm_rom_component|altrom:srom|q[4]~reg_ra1 ; inclock  ;
; N/A           ; None        ; 3.300 ns  ; address[1] ; lpm_rom:lpm_rom_component|altrom:srom|q[5]~reg_ra1 ; inclock  ;
; N/A           ; None        ; 3.300 ns  ; address[1] ; lpm_rom:lpm_rom_component|altrom:srom|q[6]~reg_ra1 ; inclock  ;
; N/A           ; None        ; 3.300 ns  ; address[1] ; lpm_rom:lpm_rom_component|altrom:srom|q[7]~reg_ra1 ; inclock  ;
; N/A           ; None        ; 3.300 ns  ; address[0] ; lpm_rom:lpm_rom_component|altrom:srom|q[0]~reg_ra0 ; inclock  ;
; N/A           ; None        ; 3.300 ns  ; address[0] ; lpm_rom:lpm_rom_component|altrom:srom|q[1]~reg_ra0 ; inclock  ;
; N/A           ; None        ; 3.300 ns  ; address[0] ; lpm_rom:lpm_rom_component|altrom:srom|q[2]~reg_ra0 ; inclock  ;
; N/A           ; None        ; 3.300 ns  ; address[0] ; lpm_rom:lpm_rom_component|altrom:srom|q[3]~reg_ra0 ; inclock  ;
; N/A           ; None        ; 3.300 ns  ; address[0] ; lpm_rom:lpm_rom_component|altrom:srom|q[4]~reg_ra0 ; inclock  ;
; N/A           ; None        ; 3.300 ns  ; address[0] ; lpm_rom:lpm_rom_component|altrom:srom|q[5]~reg_ra0 ; inclock  ;
; N/A           ; None        ; 3.300 ns  ; address[0] ; lpm_rom:lpm_rom_component|altrom:srom|q[6]~reg_ra0 ; inclock  ;
; N/A           ; None        ; 3.300 ns  ; address[0] ; lpm_rom:lpm_rom_component|altrom:srom|q[7]~reg_ra0 ; inclock  ;
; N/A           ; None        ; 1.500 ns  ; address[6] ; lpm_rom:lpm_rom_component|altrom:srom|q[0]~reg_ra6 ; inclock  ;
; N/A           ; None        ; 1.500 ns  ; address[6] ; lpm_rom:lpm_rom_component|altrom:srom|q[1]~reg_ra6 ; inclock  ;
; N/A           ; None        ; 1.500 ns  ; address[6] ; lpm_rom:lpm_rom_component|altrom:srom|q[2]~reg_ra6 ; inclock  ;
; N/A           ; None        ; 1.500 ns  ; address[6] ; lpm_rom:lpm_rom_component|altrom:srom|q[3]~reg_ra6 ; inclock  ;
; N/A           ; None        ; 1.500 ns  ; address[6] ; lpm_rom:lpm_rom_component|altrom:srom|q[4]~reg_ra6 ; inclock  ;
; N/A           ; None        ; 1.500 ns  ; address[6] ; lpm_rom:lpm_rom_component|altrom:srom|q[5]~reg_ra6 ; inclock  ;
; N/A           ; None        ; 1.500 ns  ; address[6] ; lpm_rom:lpm_rom_component|altrom:srom|q[6]~reg_ra6 ; inclock  ;
; N/A           ; None        ; 1.500 ns  ; address[6] ; lpm_rom:lpm_rom_component|altrom:srom|q[7]~reg_ra6 ; inclock  ;
; N/A           ; None        ; 1.500 ns  ; address[5] ; lpm_rom:lpm_rom_component|altrom:srom|q[0]~reg_ra5 ; inclock  ;
; N/A           ; None        ; 1.500 ns  ; address[5] ; lpm_rom:lpm_rom_component|altrom:srom|q[1]~reg_ra5 ; inclock  ;
; N/A           ; None        ; 1.500 ns  ; address[5] ; lpm_rom:lpm_rom_component|altrom:srom|q[2]~reg_ra5 ; inclock  ;
; N/A           ; None        ; 1.500 ns  ; address[5] ; lpm_rom:lpm_rom_component|altrom:srom|q[3]~reg_ra5 ; inclock  ;
; N/A           ; None        ; 1.500 ns  ; address[5] ; lpm_rom:lpm_rom_component|altrom:srom|q[4]~reg_ra5 ; inclock  ;
; N/A           ; None        ; 1.500 ns  ; address[5] ; lpm_rom:lpm_rom_component|altrom:srom|q[5]~reg_ra5 ; inclock  ;
; N/A           ; None        ; 1.500 ns  ; address[5] ; lpm_rom:lpm_rom_component|altrom:srom|q[6]~reg_ra5 ; inclock  ;
; N/A           ; None        ; 1.500 ns  ; address[5] ; lpm_rom:lpm_rom_component|altrom:srom|q[7]~reg_ra5 ; inclock  ;
+---------------+-------------+-----------+------------+----------------------------------------------------+----------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
    Info: Version 5.0 Build 148 04/26/2005 SJ Full Version
    Info: Processing started: Sat Apr 15 20:43:19 2006
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off data_rom -c data_rom
Info: Started post-fitting delay annotation
Info: Delay annotation completed successfully
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "inclock" is an undefined clock
Info: No valid register-to-register data paths exist for clock "inclock"
Info: tsu for memory "lpm_rom:lpm_rom_component|altrom:srom|q[0]~reg_ra6" (data pin = "address[6]", clock pin = "inclock") is 2.800 ns
    Info: + Longest pin to memory delay is 6.300 ns
        Info: 1: + IC(0.000 ns) + CELL(3.500 ns) = 3.500 ns; Loc. = PIN_17; Fanout = 8; PIN Node = 'address[6]'
        Info: 2: + IC(2.800 ns) + CELL(0.000 ns) = 6.300 ns; Loc. = EC3_A; Fanout = 1; MEM Node = 'lpm_rom:lpm_rom_component|altrom:srom|q[0]~reg_ra6'
        Info: Total cell delay = 3.500 ns ( 55.56 % )
        Info: Total interconnect delay = 2.800 ns ( 44.44 % )
    Info: + Micro setup delay of destination is 1.800 ns
    Info: - Shortest clock path from clock "inclock" to destination memory is 5.300 ns
        Info: 1: + IC(0.000 ns) + CELL(2.800 ns) = 2.800 ns; Loc. = PIN_43; Fanout = 56; CLK Node = 'inclock'
        Info: 2: + IC(2.500 ns) + CELL(0.000 ns) = 5.300 ns; Loc. = EC3_A; Fanout = 1; MEM Node = 'lpm_rom:lpm_rom_component|altrom:srom|q[0]~reg_ra6'
        Info: Total cell delay = 2.800 ns ( 52.83 % )
        Info: Total interconnect delay = 2.500 ns ( 47.17 % )
Info: tco from clock "inclock" to destination pin "q[7]" through memory "lpm_rom:lpm_rom_component|altrom:srom|q[7]~reg_ra0" is 29.400 ns
    Info: + Longest clock path from clock "inclock" to source memory is 5.300 ns
        Info: 1: + IC(0.000 ns) + CELL(2.800 ns) = 2.800 ns; Loc. = PIN_43; Fanout = 56; CLK Node = 'inclock'
        Info: 2: + IC(2.500 ns) + CELL(0.000 ns) = 5.300 ns; Loc. = EC7_A; Fanout = 1; MEM Node = 'lpm_rom:lpm_rom_component|altrom:srom|q[7]~reg_ra0'
        Info: Total cell delay = 2.800 ns ( 52.83 % )
        Info: Total interconnect delay = 2.500 ns ( 47.17 % )
    Info: + Micro clock to output delay of source is 0.600 ns
    Info: + Longest memory to pin delay is 23.500 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = EC7_A; Fanout = 1; MEM Node = 'lpm_rom:lpm_rom_component|altrom:srom|q[7]~reg_ra0'
        Info: 2: + IC(0.000 ns) + CELL(10.700 ns) = 10.700 ns; Loc. = EC7_A; Fanout = 1; MEM Node = 'lpm_rom:lpm_rom_component|altrom:srom|q[7]~mem_cell_ra0'
        Info: 3: + IC(0.000 ns) + CELL(2.500 ns) = 13.200 ns; Loc. = EC7_A; Fanout = 1; MEM Node = 'lpm_rom:lpm_rom_component|altrom:srom|q[7]'
        Info: 4: + IC(5.200 ns) + CELL(5.100 ns) = 23.500 ns; Loc. = PIN_60; Fanout = 0; PIN Node = 'q[7]'
        Info: Total cell delay = 18.300 ns ( 77.87 % )
        Info: Total interconnect delay = 5.200 ns ( 22.13 % )
Info: th for memory "lpm_rom:lpm_rom_component|altrom:srom|q[0]~reg_ra4" (data pin = "address[4]", clock pin = "inclock") is 3.300 ns
    Info: + Longest clock path from clock "inclock" to destination memory is 5.300 ns
        Info: 1: + IC(0.000 ns) + CELL(2.800 ns) = 2.800 ns; Loc. = PIN_43; Fanout = 56; CLK Node = 'inclock'
        Info: 2: + IC(2.500 ns) + CELL(0.000 ns) = 5.300 ns; Loc. = EC3_A; Fanout = 1; MEM Node = 'lpm_rom:lpm_rom_component|altrom:srom|q[0]~reg_ra4'
        Info: Total cell delay = 2.800 ns ( 52.83 % )
        Info: Total interconnect delay = 2.500 ns ( 47.17 % )
    Info: + Micro hold delay of destination is 2.500 ns
    Info: - Shortest pin to memory delay is 4.500 ns
        Info: 1: + IC(0.000 ns) + CELL(2.800 ns) = 2.800 ns; Loc. = PIN_1; Fanout = 8; PIN Node = 'address[4]'
        Info: 2: + IC(1.700 ns) + CELL(0.000 ns) = 4.500 ns; Loc. = EC3_A; Fanout = 1; MEM Node = 'lpm_rom:lpm_rom_component|altrom:srom|q[0]~reg_ra4'
        Info: Total cell delay = 2.800 ns ( 62.22 % )
        Info: Total interconnect delay = 1.700 ns ( 37.78 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning
    Info: Processing ended: Sat Apr 15 20:43:21 2006
    Info: Elapsed time: 00:00:03