scan_divf_sinx.map.qmsg

在EDA开发软件QuartusII上利用VHDL语言实现DDS信号发生器

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.0 Build 148 04/26/2005 SJ Full Version " "Info: Version 5.0 Build 148 04/26/2005 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Fri Apr 14 21:33:57 2006 " "Info: Processing started: Fri Apr 14 21:33:57 2006" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off scan_divf_sinx -c scan_divf_sinx " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off scan_divf_sinx -c scan_divf_sinx" {  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "scan_divf_sinx.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file scan_divf_sinx.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 scan_divf_sinx-behav " "Info: Found design unit 1: scan_divf_sinx-behav" {  } { { "scan_divf_sinx.vhd" "" { Text "E:/EDA/DDS/10k844/scan_divf_sinx/scan_divf_sinx.vhd" 12 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 scan_divf_sinx " "Info: Found entity 1: scan_divf_sinx" {  } { { "scan_divf_sinx.vhd" "" { Text "E:/EDA/DDS/10k844/scan_divf_sinx/scan_divf_sinx.vhd" 5 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "scan_divf_sinx " "Info: Elaborating entity \"scan_divf_sinx\" for the top level hierarchy" {  } {  } 0}
{ "Info" "ISGN_SEARCH_FILE" "SCANCNT4B.vhd 2 1 " "Info: Using design file SCANCNT4B.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 SCANCNT4B-behav " "Info: Found design unit 1: SCANCNT4B-behav" {  } { { "SCANCNT4B.vhd" "" { Text "E:/EDA/DDS/10k844/scan_divf_sinx/SCANCNT4B.vhd" 12 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 SCANCNT4B " "Info: Found entity 1: SCANCNT4B" {  } { { "SCANCNT4B.vhd" "" { Text "E:/EDA/DDS/10k844/scan_divf_sinx/SCANCNT4B.vhd" 5 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "SCANCNT4B SCANCNT4B:u1 " "Info: Elaborating entity \"SCANCNT4B\" for hierarchy \"SCANCNT4B:u1\"" {  } { { "scan_divf_sinx.vhd" "u1" { Text "E:/EDA/DDS/10k844/scan_divf_sinx/scan_divf_sinx.vhd" 29 -1 0 } }  } 0}
{ "Info" "ISGN_SEARCH_FILE" "divf16_sinx.vhd 2 1 " "Info: Using design file divf16_sinx.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 divf16_sinx-behav " "Info: Found design unit 1: divf16_sinx-behav" {  } { { "divf16_sinx.vhd" "" { Text "E:/EDA/DDS/10k844/scan_divf_sinx/divf16_sinx.vhd" 12 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 divf16_sinx " "Info: Found entity 1: divf16_sinx" {  } { { "divf16_sinx.vhd" "" { Text "E:/EDA/DDS/10k844/scan_divf_sinx/divf16_sinx.vhd" 5 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "divf16_sinx divf16_sinx:u2 " "Info: Elaborating entity \"divf16_sinx\" for hierarchy \"divf16_sinx:u2\"" {  } { { "scan_divf_sinx.vhd" "u2" { Text "E:/EDA/DDS/10k844/scan_divf_sinx/scan_divf_sinx.vhd" 30 -1 0 } }  } 0}
{ "Info" "ISGN_SEARCH_FILE" "divf.vhd 2 1 " "Info: Using design file divf.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 divf-behav " "Info: Found design unit 1: divf-behav" {  } { { "divf.vhd" "" { Text "E:/EDA/DDS/10k844/scan_divf_sinx/divf.vhd" 13 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 divf " "Info: Found entity 1: divf" {  } { { "divf.vhd" "" { Text "E:/EDA/DDS/10k844/scan_divf_sinx/divf.vhd" 5 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "divf divf16_sinx:u2\|divf:u1 " "Info: Elaborating entity \"divf\" for hierarchy \"divf16_sinx:u2\|divf:u1\"" {  } { { "divf16_sinx.vhd" "u1" { Text "E:/EDA/DDS/10k844/scan_divf_sinx/divf16_sinx.vhd" 29 -1 0 } }  } 0}
{ "Info" "ISGN_SEARCH_FILE" "singt3.vhd 2 1 " "Info: Using design file singt3.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 singt3-behav " "Info: Found design unit 1: singt3-behav" {  } { { "singt3.vhd" "" { Text "E:/EDA/DDS/10k844/scan_divf_sinx/singt3.vhd" 10 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 singt3 " "Info: Found entity 1: singt3" {  } { { "singt3.vhd" "" { Text "E:/EDA/DDS/10k844/scan_divf_sinx/singt3.vhd" 5 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "singt3 divf16_sinx:u2\|singt3:u2 " "Info: Elaborating entity \"singt3\" for hierarchy \"divf16_sinx:u2\|singt3:u2\"" {  } { { "divf16_sinx.vhd" "u2" { Text "E:/EDA/DDS/10k844/scan_divf_sinx/divf16_sinx.vhd" 30 -1 0 } }  } 0}
{ "Info" "IVRFX_VHDL_CASE_STATEMENT_OTHERS_CLAUSE_NEVER_SELECTED" "singt3.vhd(73) " "Info: VHDL Case Statement information at singt3.vhd(73): OTHERS choice is never selected" {  } { { "singt3.vhd" "" { Text "E:/EDA/DDS/10k844/scan_divf_sinx/singt3.vhd" 73 0 0 } }  } 0}
{ "Info" "IOPT_INFERENCING_SUMMARY" "3 " "Info: Inferred 3 megafunctions from design logic" { { "Info" "IOPT_LPM_COUNTER_INFERRED" "divf16_sinx:u2\|singt3:u2\|q\[0\]~7 7 " "Info: Inferred lpm_counter megafunction (LPM_WIDTH=7) from the following logic: \"divf16_sinx:u2\|singt3:u2\|q\[0\]~7\"" {  } { { "singt3.vhd" "q\[0\]~7" { Text "E:/EDA/DDS/10k844/scan_divf_sinx/singt3.vhd" 12 -1 0 } }  } 0} { "Info" "IOPT_LPM_COUNTER_INFERRED" "divf16_sinx:u2\|divf:u1\|CNT4\[0\]~4 4 " "Info: Inferred lpm_counter megafunction (LPM_WIDTH=4) from the following logic: \"divf16_sinx:u2\|divf:u1\|CNT4\[0\]~4\"" {  } { { "divf.vhd" "CNT4\[0\]~4" { Text "E:/EDA/DDS/10k844/scan_divf_sinx/divf.vhd" 17 -1 0 } }  } 0} { "Info" "IOPT_LPM_COUNTER_INFERRED" "SCANCNT4B:u1\|CNT4\[0\]~4 4 " "Info: Inferred lpm_counter megafunction (LPM_WIDTH=4) from the following logic: \"SCANCNT4B:u1\|CNT4\[0\]~4\"" {  } { { "SCANCNT4B.vhd" "CNT4\[0\]~4" { Text "E:/EDA/DDS/10k844/scan_divf_sinx/SCANCNT4B.vhd" 16 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "d:/altera/quartus50/libraries/megafunctions/lpm_counter.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file d:/altera/quartus50/libraries/megafunctions/lpm_counter.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_counter " "Info: Found entity 1: lpm_counter" {  } { { "lpm_counter.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/lpm_counter.tdf" 227 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "d:/altera/quartus50/libraries/megafunctions/alt_counter_f10ke.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file d:/altera/quartus50/libraries/megafunctions/alt_counter_f10ke.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 alt_counter_f10ke " "Info: Found entity 1: alt_counter_f10ke" {  } { { "alt_counter_f10ke.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/alt_counter_f10ke.tdf" 250 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "113 " "Info: Implemented 113 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "2 " "Info: Implemented 2 input pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_OPINS" "8 " "Info: Implemented 8 output pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_LCELLS" "103 " "Info: Implemented 103 logic cells" {  } {  } 0}  } {  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 0 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Fri Apr 14 21:34:04 2006 " "Info: Processing ended: Fri Apr 14 21:34:04 2006" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:08 " "Info: Elapsed time: 00:00:08" {  } {  } 0}  } {  } 0}