scan_divf_sinx.tan.qmsg

在EDA开发软件QuartusII上利用VHDL语言实现DDS信号发生器

{ "Info" "ITDB_TSU_RESULT" "SCANCNT4B:u1\|lpm_counter:CNT4_rtl_2\|alt_counter_f10ke:wysi_counter\|q\[3\] enable clock 5.900 ns register " "Info: tsu for register \"SCANCNT4B:u1\|lpm_counter:CNT4_rtl_2\|alt_counter_f10ke:wysi_counter\|q\[3\]\" (data pin = \"enable\", clock pin = \"clock\") is 5.900 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "8.700 ns + Longest pin register " "Info: + Longest pin to register delay is 8.700 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.500 ns) 3.500 ns enable 1 PIN PIN_5 14 " "Info: 1: + IC(0.000 ns) + CELL(3.500 ns) = 3.500 ns; Loc. = PIN_5; Fanout = 14; PIN Node = 'enable'" {  } { { "E:/EDA/DDS/10k844/scan_divf_sinx/db/scan_divf_sinx_cmp.qrpt" "" { Report "E:/EDA/DDS/10k844/scan_divf_sinx/db/scan_divf_sinx_cmp.qrpt" Compiler "scan_divf_sinx" "UNKNOWN" "V1" "E:/EDA/DDS/10k844/scan_divf_sinx/db/scan_divf_sinx.quartus_db" { Floorplan "E:/EDA/DDS/10k844/scan_divf_sinx/" "" "" { enable } "NODE_NAME" } "" } } { "scan_divf_sinx.vhd" "" { Text "E:/EDA/DDS/10k844/scan_divf_sinx/scan_divf_sinx.vhd" 6 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.500 ns) + CELL(1.700 ns) 8.700 ns SCANCNT4B:u1\|lpm_counter:CNT4_rtl_2\|alt_counter_f10ke:wysi_counter\|q\[3\] 2 REG LC6_B12 2 " "Info: 2: + IC(3.500 ns) + CELL(1.700 ns) = 8.700 ns; Loc. = LC6_B12; Fanout = 2; REG Node = 'SCANCNT4B:u1\|lpm_counter:CNT4_rtl_2\|alt_counter_f10ke:wysi_counter\|q\[3\]'" {  } { { "E:/EDA/DDS/10k844/scan_divf_sinx/db/scan_divf_sinx_cmp.qrpt" "" { Report "E:/EDA/DDS/10k844/scan_divf_sinx/db/scan_divf_sinx_cmp.qrpt" Compiler "scan_divf_sinx" "UNKNOWN" "V1" "E:/EDA/DDS/10k844/scan_divf_sinx/db/scan_divf_sinx.quartus_db" { Floorplan "E:/EDA/DDS/10k844/scan_divf_sinx/" "" "5.200 ns" { enable SCANCNT4B:u1|lpm_counter:CNT4_rtl_2|alt_counter_f10ke:wysi_counter|q[3] } "NODE_NAME" } "" } } { "alt_counter_f10ke.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/alt_counter_f10ke.tdf" 271 2 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "5.200 ns 59.77 % " "Info: Total cell delay = 5.200 ns ( 59.77 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.500 ns 40.23 % " "Info: Total interconnect delay = 3.500 ns ( 40.23 % )" {  } {  } 0}  } { { "E:/EDA/DDS/10k844/scan_divf_sinx/db/scan_divf_sinx_cmp.qrpt" "" { Report "E:/EDA/DDS/10k844/scan_divf_sinx/db/scan_divf_sinx_cmp.qrpt" Compiler "scan_divf_sinx" "UNKNOWN" "V1" "E:/EDA/DDS/10k844/scan_divf_sinx/db/scan_divf_sinx.quartus_db" { Floorplan "E:/EDA/DDS/10k844/scan_divf_sinx/" "" "8.700 ns" { enable SCANCNT4B:u1|lpm_counter:CNT4_rtl_2|alt_counter_f10ke:wysi_counter|q[3] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "8.700 ns" { enable enable~out SCANCNT4B:u1|lpm_counter:CNT4_rtl_2|alt_counter_f10ke:wysi_counter|q[3] } { 0.000ns 0.000ns 3.500ns } { 0.000ns 3.500ns 1.700ns } } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "2.500 ns + " "Info: + Micro setup delay of destination is 2.500 ns" {  } { { "alt_counter_f10ke.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/alt_counter_f10ke.tdf" 271 2 0 } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock destination 5.300 ns - Shortest register " "Info: - Shortest clock path from clock \"clock\" to destination register is 5.300 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.800 ns) 2.800 ns clock 1 CLK PIN_2 15 " "Info: 1: + IC(0.000 ns) + CELL(2.800 ns) = 2.800 ns; Loc. = PIN_2; Fanout = 15; CLK Node = 'clock'" {  } { { "E:/EDA/DDS/10k844/scan_divf_sinx/db/scan_divf_sinx_cmp.qrpt" "" { Report "E:/EDA/DDS/10k844/scan_divf_sinx/db/scan_divf_sinx_cmp.qrpt" Compiler "scan_divf_sinx" "UNKNOWN" "V1" "E:/EDA/DDS/10k844/scan_divf_sinx/db/scan_divf_sinx.quartus_db" { Floorplan "E:/EDA/DDS/10k844/scan_divf_sinx/" "" "" { clock } "NODE_NAME" } "" } } { "scan_divf_sinx.vhd" "" { Text "E:/EDA/DDS/10k844/scan_divf_sinx/scan_divf_sinx.vhd" 6 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.500 ns) + CELL(0.000 ns) 5.300 ns SCANCNT4B:u1\|lpm_counter:CNT4_rtl_2\|alt_counter_f10ke:wysi_counter\|q\[3\] 2 REG LC6_B12 2 " "Info: 2: + IC(2.500 ns) + CELL(0.000 ns) = 5.300 ns; Loc. = LC6_B12; Fanout = 2; REG Node = 'SCANCNT4B:u1\|lpm_counter:CNT4_rtl_2\|alt_counter_f10ke:wysi_counter\|q\[3\]'" {  } { { "E:/EDA/DDS/10k844/scan_divf_sinx/db/scan_divf_sinx_cmp.qrpt" "" { Report "E:/EDA/DDS/10k844/scan_divf_sinx/db/scan_divf_sinx_cmp.qrpt" Compiler "scan_divf_sinx" "UNKNOWN" "V1" "E:/EDA/DDS/10k844/scan_divf_sinx/db/scan_divf_sinx.quartus_db" { Floorplan "E:/EDA/DDS/10k844/scan_divf_sinx/" "" "2.500 ns" { clock SCANCNT4B:u1|lpm_counter:CNT4_rtl_2|alt_counter_f10ke:wysi_counter|q[3] } "NODE_NAME" } "" } } { "alt_counter_f10ke.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/alt_counter_f10ke.tdf" 271 2 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.800 ns 52.83 % " "Info: Total cell delay = 2.800 ns ( 52.83 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.500 ns 47.17 % " "Info: Total interconnect delay = 2.500 ns ( 47.17 % )" {  } {  } 0}  } { { "E:/EDA/DDS/10k844/scan_divf_sinx/db/scan_divf_sinx_cmp.qrpt" "" { Report "E:/EDA/DDS/10k844/scan_divf_sinx/db/scan_divf_sinx_cmp.qrpt" Compiler "scan_divf_sinx" "UNKNOWN" "V1" "E:/EDA/DDS/10k844/scan_divf_sinx/db/scan_divf_sinx.quartus_db" { Floorplan "E:/EDA/DDS/10k844/scan_divf_sinx/" "" "5.300 ns" { clock SCANCNT4B:u1|lpm_counter:CNT4_rtl_2|alt_counter_f10ke:wysi_counter|q[3] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "5.300 ns" { clock clock~out SCANCNT4B:u1|lpm_counter:CNT4_rtl_2|alt_counter_f10ke:wysi_counter|q[3] } { 0.000ns 0.000ns 2.500ns } { 0.000ns 2.800ns 0.000ns } } }  } 0}  } { { "E:/EDA/DDS/10k844/scan_divf_sinx/db/scan_divf_sinx_cmp.qrpt" "" { Report "E:/EDA/DDS/10k844/scan_divf_sinx/db/scan_divf_sinx_cmp.qrpt" Compiler "scan_divf_sinx" "UNKNOWN" "V1" "E:/EDA/DDS/10k844/scan_divf_sinx/db/scan_divf_sinx.quartus_db" { Floorplan "E:/EDA/DDS/10k844/scan_divf_sinx/" "" "8.700 ns" { enable SCANCNT4B:u1|lpm_counter:CNT4_rtl_2|alt_counter_f10ke:wysi_counter|q[3] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "8.700 ns" { enable enable~out SCANCNT4B:u1|lpm_counter:CNT4_rtl_2|alt_counter_f10ke:wysi_counter|q[3] } { 0.000ns 0.000ns 3.500ns } { 0.000ns 3.500ns 1.700ns } } } { "E:/EDA/DDS/10k844/scan_divf_sinx/db/scan_divf_sinx_cmp.qrpt" "" { Report "E:/EDA/DDS/10k844/scan_divf_sinx/db/scan_divf_sinx_cmp.qrpt" Compiler "scan_divf_sinx" "UNKNOWN" "V1" "E:/EDA/DDS/10k844/scan_divf_sinx/db/scan_divf_sinx.quartus_db" { Floorplan "E:/EDA/DDS/10k844/scan_divf_sinx/" "" "5.300 ns" { clock SCANCNT4B:u1|lpm_counter:CNT4_rtl_2|alt_counter_f10ke:wysi_counter|q[3] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "5.300 ns" { clock clock~out SCANCNT4B:u1|lpm_counter:CNT4_rtl_2|alt_counter_f10ke:wysi_counter|q[3] } { 0.000ns 0.000ns 2.500ns } { 0.000ns 2.800ns 0.000ns } } }  } 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clock da_data\[0\] divf16_sinx:u2\|singt3:u2\|lpm_counter:q_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[0\] 34.800 ns register " "Info: tco from clock \"clock\" to destination pin \"da_data\[0\]\" through register \"divf16_sinx:u2\|singt3:u2\|lpm_counter:q_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[0\]\" is 34.800 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock source 11.000 ns + Longest register " "Info: + Longest clock path from clock \"clock\" to source register is 11.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.800 ns) 2.800 ns clock 1 CLK PIN_2 15 " "Info: 1: + IC(0.000 ns) + CELL(2.800 ns) = 2.800 ns; Loc. = PIN_2; Fanout = 15; CLK Node = 'clock'" {  } { { "E:/EDA/DDS/10k844/scan_divf_sinx/db/scan_divf_sinx_cmp.qrpt" "" { Report "E:/EDA/DDS/10k844/scan_divf_sinx/db/scan_divf_sinx_cmp.qrpt" Compiler "scan_divf_sinx" "UNKNOWN" "V1" "E:/EDA/DDS/10k844/scan_divf_sinx/db/scan_divf_sinx.quartus_db" { Floorplan "E:/EDA/DDS/10k844/scan_divf_sinx/" "" "" { clock } "NODE_NAME" } "" } } { "scan_divf_sinx.vhd" "" { Text "E:/EDA/DDS/10k844/scan_divf_sinx/scan_divf_sinx.vhd" 6 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.500 ns) + CELL(1.100 ns) 6.400 ns divf16_sinx:u2\|divf:u1\|COUT 2 REG LC1_B10 11 " "Info: 2: + IC(2.500 ns) + CELL(1.100 ns) = 6.400 ns; Loc. = LC1_B10; Fanout = 11; REG Node = 'divf16_sinx:u2\|divf:u1\|COUT'" {  } { { "E:/EDA/DDS/10k844/scan_divf_sinx/db/scan_divf_sinx_cmp.qrpt" "" { Report "E:/EDA/DDS/10k844/scan_divf_sinx/db/scan_divf_sinx_cmp.qrpt" Compiler "scan_divf_sinx" "UNKNOWN" "V1" "E:/EDA/DDS/10k844/scan_divf_sinx/db/scan_divf_sinx.quartus_db" { Floorplan "E:/EDA/DDS/10k844/scan_divf_sinx/" "" "3.600 ns" { clock divf16_sinx:u2|divf:u1|COUT } "NODE_NAME" } "" } } { "divf.vhd" "" { Text "E:/EDA/DDS/10k844/scan_divf_sinx/divf.vhd" 9 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(4.600 ns) + CELL(0.000 ns) 11.000 ns divf16_sinx:u2\|singt3:u2\|lpm_counter:q_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[0\] 3 REG LC1_B13 51 " "Info: 3: + IC(4.600 ns) + CELL(0.000 ns) = 11.000 ns; Loc. = LC1_B13; Fanout = 51; REG Node = 'divf16_sinx:u2\|singt3:u2\|lpm_counter:q_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[0\]'" {  } { { "E:/EDA/DDS/10k844/scan_divf_sinx/db/scan_divf_sinx_cmp.qrpt" "" { Report "E:/EDA/DDS/10k844/scan_divf_sinx/db/scan_divf_sinx_cmp.qrpt" Compiler "scan_divf_sinx" "UNKNOWN" "V1" "E:/EDA/DDS/10k844/scan_divf_sinx/db/scan_divf_sinx.quartus_db" { Floorplan "E:/EDA/DDS/10k844/scan_divf_sinx/" "" "4.600 ns" { divf16_sinx:u2|divf:u1|COUT divf16_sinx:u2|singt3:u2|lpm_counter:q_rtl_0|alt_counter_f10ke:wysi_counter|q[0] } "NODE_NAME" } "" } } { "alt_counter_f10ke.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/alt_counter_f10ke.tdf" 271 2 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.900 ns 35.45 % " "Info: Total cell delay = 3.900 ns ( 35.45 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "7.100 ns 64.55 % " "Info: Total interconnect delay = 7.100 ns ( 64.55 % )" {  } {  } 0}  } { { "E:/EDA/DDS/10k844/scan_divf_sinx/db/scan_divf_sinx_cmp.qrpt" "" { Report "E:/EDA/DDS/10k844/scan_divf_sinx/db/scan_divf_sinx_cmp.qrpt" Compiler "scan_divf_sinx" "UNKNOWN" "V1" "E:/EDA/DDS/10k844/scan_divf_sinx/db/scan_divf_sinx.quartus_db" { Floorplan "E:/EDA/DDS/10k844/scan_divf_sinx/" "" "11.000 ns" { clock divf16_sinx:u2|divf:u1|COUT divf16_sinx:u2|singt3:u2|lpm_counter:q_rtl_0|alt_counter_f10ke:wysi_counter|q[0] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "11.000 ns" { clock clock~out divf16_sinx:u2|divf:u1|COUT divf16_sinx:u2|singt3:u2|lpm_counter:q_rtl_0|alt_counter_f10ke:wysi_counter|q[0] } { 0.000ns 0.000ns 2.500ns 4.600ns } { 0.000ns 2.800ns 1.100ns 0.000ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.100 ns + " "Info: + Micro clock to output delay of source is 1.100 ns" {  } { { "alt_counter_f10ke.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/alt_counter_f10ke.tdf" 271 2 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "22.700 ns + Longest register pin " "Info: + Longest register to pin delay is 22.700 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns divf16_sinx:u2\|singt3:u2\|lpm_counter:q_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[0\] 1 REG LC1_B13 51 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC1_B13; Fanout = 51; REG Node = 'divf16_sinx:u2\|singt3:u2\|lpm_counter:q_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[0\]'" {  } { { "E:/EDA/DDS/10k844/scan_divf_sinx/db/scan_divf_sinx_cmp.qrpt" "" { Report "E:/EDA/DDS/10k844/scan_divf_sinx/db/scan_divf_sinx_cmp.qrpt" Compiler "scan_divf_sinx" "UNKNOWN" "V1" "E:/EDA/DDS/10k844/scan_divf_sinx/db/scan_divf_sinx.quartus_db" { Floorplan "E:/EDA/DDS/10k844/scan_divf_sinx/" "" "" { divf16_sinx:u2|singt3:u2|lpm_counter:q_rtl_0|alt_counter_f10ke:wysi_counter|q[0] } "NODE_NAME" } "" } } { "alt_counter_f10ke.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/alt_counter_f10ke.tdf" 271 2 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.500 ns) + CELL(2.300 ns) 5.800 ns divf16_sinx:u2\|singt3:u2\|dout\[0\]~648 2 COMB LC4_A15 1 " "Info: 2: + IC(3.500 ns) + CELL(2.300 ns) = 5.800 ns; Loc. = LC4_A15; Fanout = 1; COMB Node = 'divf16_sinx:u2\|singt3:u2\|dout\[0\]~648'" {  } { { "E:/EDA/DDS/10k844/scan_divf_sinx/db/scan_divf_sinx_cmp.qrpt" "" { Report "E:/EDA/DDS/10k844/scan_divf_sinx/db/scan_divf_sinx_cmp.qrpt" Compiler "scan_divf_sinx" "UNKNOWN" "V1" "E:/EDA/DDS/10k844/scan_divf_sinx/db/scan_divf_sinx.quartus_db" { Floorplan "E:/EDA/DDS/10k844/scan_divf_sinx/" "" "5.800 ns" { divf16_sinx:u2|singt3:u2|lpm_counter:q_rtl_0|alt_counter_f10ke:wysi_counter|q[0] divf16_sinx:u2|singt3:u2|dout[0]~648 } "NODE_NAME" } "" } } { "singt3.vhd" "" { Text "E:/EDA/DDS/10k844/scan_divf_sinx/singt3.vhd" 7 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.600 ns) + CELL(2.300 ns) 8.700 ns divf16_sinx:u2\|singt3:u2\|dout\[0\]~650 3 COMB LC6_A15 1 " "Info: 3: + IC(0.600 ns) + CELL(2.300 ns) = 8.700 ns; Loc. = LC6_A15; Fanout = 1; COMB Node = 'divf16_sinx:u2\|singt3:u2\|dout\[0\]~650'" {  } { { "E:/EDA/DDS/10k844/scan_divf_sinx/db/scan_divf_sinx_cmp.qrpt" "" { Report "E:/EDA/DDS/10k844/scan_divf_sinx/db/scan_divf_sinx_cmp.qrpt" Compiler "scan_divf_sinx" "UNKNOWN" "V1" "E:/EDA/DDS/10k844/scan_divf_sinx/db/scan_divf_sinx.quartus_db" { Floorplan "E:/EDA/DDS/10k844/scan_divf_sinx/" "" "2.900 ns" { divf16_sinx:u2|singt3:u2|dout[0]~648 divf16_sinx:u2|singt3:u2|dout[0]~650 } "NODE_NAME" } "" } } { "singt3.vhd" "" { Text "E:/EDA/DDS/10k844/scan_divf_sinx/singt3.vhd" 7 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.600 ns) + CELL(2.300 ns) 11.600 ns divf16_sinx:u2\|singt3:u2\|dout\[0\]~652 4 COMB LC2_A15 1 " "Info: 4: + IC(0.600 ns) + CELL(2.300 ns) = 11.600 ns; Loc. = LC2_A15; Fanout = 1; COMB Node = 'divf16_sinx:u2\|singt3:u2\|dout\[0\]~652'" {  } { { "E:/EDA/DDS/10k844/scan_divf_sinx/db/scan_divf_sinx_cmp.qrpt" "" { Report "E:/EDA/DDS/10k844/scan_divf_sinx/db/scan_divf_sinx_cmp.qrpt" Compiler "scan_divf_sinx" "UNKNOWN" "V1" "E:/EDA/DDS/10k844/scan_divf_sinx/db/scan_divf_sinx.quartus_db" { Floorplan "E:/EDA/DDS/10k844/scan_divf_sinx/" "" "2.900 ns" { divf16_sinx:u2|singt3:u2|dout[0]~650 divf16_sinx:u2|singt3:u2|dout[0]~652 } "NODE_NAME" } "" } } { "singt3.vhd" "" { Text "E:/EDA/DDS/10k844/scan_divf_sinx/singt3.vhd" 7 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.600 ns) + CELL(2.300 ns) 16.500 ns divf16_sinx:u2\|singt3:u2\|dout\[0\]~653 5 COMB LC1_A11 1 " "Info: 5: + IC(2.600 ns) + CELL(2.300 ns) = 16.500 ns; Loc. = LC1_A11; Fanout = 1; COMB Node = 'divf16_sinx:u2\|singt3:u2\|dout\[0\]~653'" {  } { { "E:/EDA/DDS/10k844/scan_divf_sinx/db/scan_divf_sinx_cmp.qrpt" "" { Report "E:/EDA/DDS/10k844/scan_divf_sinx/db/scan_divf_sinx_cmp.qrpt" Compiler "scan_divf_sinx" "UNKNOWN" "V1" "E:/EDA/DDS/10k844/scan_divf_sinx/db/scan_divf_sinx.quartus_db" { Floorplan "E:/EDA/DDS/10k844/scan_divf_sinx/" "" "4.900 ns" { divf16_sinx:u2|singt3:u2|dout[0]~652 divf16_sinx:u2|singt3:u2|dout[0]~653 } "NODE_NAME" } "" } } { "singt3.vhd" "" { Text "E:/EDA/DDS/10k844/scan_divf_sinx/singt3.vhd" 7 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.100 ns) + CELL(5.100 ns) 22.700 ns da_data\[0\] 6 PIN PIN_39 0 " "Info: 6: + IC(1.100 ns) + CELL(5.100 ns) = 22.700 ns; Loc. = PIN_39; Fanout = 0; PIN Node = 'da_data\[0\]'" {  } { { "E:/EDA/DDS/10k844/scan_divf_sinx/db/scan_divf_sinx_cmp.qrpt" "" { Report "E:/EDA/DDS/10k844/scan_divf_sinx/db/scan_divf_sinx_cmp.qrpt" Compiler "scan_divf_sinx" "UNKNOWN" "V1" "E:/EDA/DDS/10k844/scan_divf_sinx/db/scan_divf_sinx.quartus_db" { Floorplan "E:/EDA/DDS/10k844/scan_divf_sinx/" "" "6.200 ns" { divf16_sinx:u2|singt3:u2|dout[0]~653 da_data[0] } "NODE_NAME" } "" } } { "scan_divf_sinx.vhd" "" { Text "E:/EDA/DDS/10k844/scan_divf_sinx/scan_divf_sinx.vhd" 8 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "14.300 ns 63.00 % " "Info: Total cell delay = 14.300 ns ( 63.00 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "8.400 ns 37.00 % " "Info: Total interconnect delay = 8.400 ns ( 37.00 % )" {  } {  } 0}  } { { "E:/EDA/DDS/10k844/scan_divf_sinx/db/scan_divf_sinx_cmp.qrpt" "" { Report "E:/EDA/DDS/10k844/scan_divf_sinx/db/scan_divf_sinx_cmp.qrpt" Compiler "scan_divf_sinx" "UNKNOWN" "V1" "E:/EDA/DDS/10k844/scan_divf_sinx/db/scan_divf_sinx.quartus_db" { Floorplan "E:/EDA/DDS/10k844/scan_divf_sinx/" "" "22.700 ns" { divf16_sinx:u2|singt3:u2|lpm_counter:q_rtl_0|alt_counter_f10ke:wysi_counter|q[0] divf16_sinx:u2|singt3:u2|dout[0]~648 divf16_sinx:u2|singt3:u2|dout[0]~650 divf16_sinx:u2|singt3:u2|dout[0]~652 divf16_sinx:u2|singt3:u2|dout[0]~653 da_data[0] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "22.700 ns" { divf16_sinx:u2|singt3:u2|lpm_counter:q_rtl_0|alt_counter_f10ke:wysi_counter|q[0] divf16_sinx:u2|singt3:u2|dout[0]~648 divf16_sinx:u2|singt3:u2|dout[0]~650 divf16_sinx:u2|singt3:u2|dout[0]~652 divf16_sinx:u2|singt3:u2|dout[0]~653 da_data[0] } { 0.000ns 3.500ns 0.600ns 0.600ns 2.600ns 1.100ns } { 0.000ns 2.300ns 2.300ns 2.300ns 2.300ns 5.100ns } } }  } 0}  } { { "E:/EDA/DDS/10k844/scan_divf_sinx/db/scan_divf_sinx_cmp.qrpt" "" { Report "E:/EDA/DDS/10k844/scan_divf_sinx/db/scan_divf_sinx_cmp.qrpt" Compiler "scan_divf_sinx" "UNKNOWN" "V1" "E:/EDA/DDS/10k844/scan_divf_sinx/db/scan_divf_sinx.quartus_db" { Floorplan "E:/EDA/DDS/10k844/scan_divf_sinx/" "" "11.000 ns" { clock divf16_sinx:u2|divf:u1|COUT divf16_sinx:u2|singt3:u2|lpm_counter:q_rtl_0|alt_counter_f10ke:wysi_counter|q[0] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "11.000 ns" { clock clock~out divf16_sinx:u2|divf:u1|COUT divf16_sinx:u2|singt3:u2|lpm_counter:q_rtl_0|alt_counter_f10ke:wysi_counter|q[0] } { 0.000ns 0.000ns 2.500ns 4.600ns } { 0.000ns 2.800ns 1.100ns 0.000ns } } } { "E:/EDA/DDS/10k844/scan_divf_sinx/db/scan_divf_sinx_cmp.qrpt" "" { Report "E:/EDA/DDS/10k844/scan_divf_sinx/db/scan_divf_sinx_cmp.qrpt" Compiler "scan_divf_sinx" "UNKNOWN" "V1" "E:/EDA/DDS/10k844/scan_divf_sinx/db/scan_divf_sinx.quartus_db" { Floorplan "E:/EDA/DDS/10k844/scan_divf_sinx/" "" "22.700 ns" { divf16_sinx:u2|singt3:u2|lpm_counter:q_rtl_0|alt_counter_f10ke:wysi_counter|q[0] divf16_sinx:u2|singt3:u2|dout[0]~648 divf16_sinx:u2|singt3:u2|dout[0]~650 divf16_sinx:u2|singt3:u2|dout[0]~652 divf16_sinx:u2|singt3:u2|dout[0]~653 da_data[0] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "22.700 ns" { divf16_sinx:u2|singt3:u2|lpm_counter:q_rtl_0|alt_counter_f10ke:wysi_counter|q[0] divf16_sinx:u2|singt3:u2|dout[0]~648 divf16_sinx:u2|singt3:u2|dout[0]~650 divf16_sinx:u2|singt3:u2|dout[0]~652 divf16_sinx:u2|singt3:u2|dout[0]~653 da_data[0] } { 0.000ns 3.500ns 0.600ns 0.600ns 2.600ns 1.100ns } { 0.000ns 2.300ns 2.300ns 2.300ns 2.300ns 5.100ns } } }  } 0}
{ "Info" "ITDB_TH_RESULT" "SCANCNT4B:u1\|lpm_counter:CNT4_rtl_2\|alt_counter_f10ke:wysi_counter\|q\[3\] enable clock -1.300 ns register " "Info: th for register \"SCANCNT4B:u1\|lpm_counter:CNT4_rtl_2\|alt_counter_f10ke:wysi_counter\|q\[3\]\" (data pin = \"enable\", clock pin = \"clock\") is -1.300 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock destination 5.300 ns + Longest register " "Info: + Longest clock path from clock \"clock\" to destination register is 5.300 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.800 ns) 2.800 ns clock 1 CLK PIN_2 15 " "Info: 1: + IC(0.000 ns) + CELL(2.800 ns) = 2.800 ns; Loc. = PIN_2; Fanout = 15; CLK Node = 'clock'" {  } { { "E:/EDA/DDS/10k844/scan_divf_sinx/db/scan_divf_sinx_cmp.qrpt" "" { Report "E:/EDA/DDS/10k844/scan_divf_sinx/db/scan_divf_sinx_cmp.qrpt" Compiler "scan_divf_sinx" "UNKNOWN" "V1" "E:/EDA/DDS/10k844/scan_divf_sinx/db/scan_divf_sinx.quartus_db" { Floorplan "E:/EDA/DDS/10k844/scan_divf_sinx/" "" "" { clock } "NODE_NAME" } "" } } { "scan_divf_sinx.vhd" "" { Text "E:/EDA/DDS/10k844/scan_divf_sinx/scan_divf_sinx.vhd" 6 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.500 ns) + CELL(0.000 ns) 5.300 ns SCANCNT4B:u1\|lpm_counter:CNT4_rtl_2\|alt_counter_f10ke:wysi_counter\|q\[3\] 2 REG LC6_B12 2 " "Info: 2: + IC(2.500 ns) + CELL(0.000 ns) = 5.300 ns; Loc. = LC6_B12; Fanout = 2; REG Node = 'SCANCNT4B:u1\|lpm_counter:CNT4_rtl_2\|alt_counter_f10ke:wysi_counter\|q\[3\]'" {  } { { "E:/EDA/DDS/10k844/scan_divf_sinx/db/scan_divf_sinx_cmp.qrpt" "" { Report "E:/EDA/DDS/10k844/scan_divf_sinx/db/scan_divf_sinx_cmp.qrpt" Compiler "scan_divf_sinx" "UNKNOWN" "V1" "E:/EDA/DDS/10k844/scan_divf_sinx/db/scan_divf_sinx.quartus_db" { Floorplan "E:/EDA/DDS/10k844/scan_divf_sinx/" "" "2.500 ns" { clock SCANCNT4B:u1|lpm_counter:CNT4_rtl_2|alt_counter_f10ke:wysi_counter|q[3] } "NODE_NAME" } "" } } { "alt_counter_f10ke.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/alt_counter_f10ke.tdf" 271 2 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.800 ns 52.83 % " "Info: Total cell delay = 2.800 ns ( 52.83 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.500 ns 47.17 % " "Info: Total interconnect delay = 2.500 ns ( 47.17 % )" {  } {  } 0}  } { { "E:/EDA/DDS/10k844/scan_divf_sinx/db/scan_divf_sinx_cmp.qrpt" "" { Report "E:/EDA/DDS/10k844/scan_divf_sinx/db/scan_divf_sinx_cmp.qrpt" Compiler "scan_divf_sinx" "UNKNOWN" "V1" "E:/EDA/DDS/10k844/scan_divf_sinx/db/scan_divf_sinx.quartus_db" { Floorplan "E:/EDA/DDS/10k844/scan_divf_sinx/" "" "5.300 ns" { clock SCANCNT4B:u1|lpm_counter:CNT4_rtl_2|alt_counter_f10ke:wysi_counter|q[3] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "5.300 ns" { clock clock~out SCANCNT4B:u1|lpm_counter:CNT4_rtl_2|alt_counter_f10ke:wysi_counter|q[3] } { 0.000ns 0.000ns 2.500ns } { 0.000ns 2.800ns 0.000ns } } }  } 0} { "Info" "ITDB_FULL_TH_DELAY" "1.600 ns + " "Info: + Micro hold delay of destination is 1.600 ns" {  } { { "alt_counter_f10ke.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/alt_counter_f10ke.tdf" 271 2 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "8.200 ns - Shortest pin register " "Info: - Shortest pin to register delay is 8.200 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.500 ns) 3.500 ns enable 1 PIN PIN_5 14 " "Info: 1: + IC(0.000 ns) + CELL(3.500 ns) = 3.500 ns; Loc. = PIN_5; Fanout = 14; PIN Node = 'enable'" {  } { { "E:/EDA/DDS/10k844/scan_divf_sinx/db/scan_divf_sinx_cmp.qrpt" "" { Report "E:/EDA/DDS/10k844/scan_divf_sinx/db/scan_divf_sinx_cmp.qrpt" Compiler "scan_divf_sinx" "UNKNOWN" "V1" "E:/EDA/DDS/10k844/scan_divf_sinx/db/scan_divf_sinx.quartus_db" { Floorplan "E:/EDA/DDS/10k844/scan_divf_sinx/" "" "" { enable } "NODE_NAME" } "" } } { "scan_divf_sinx.vhd" "" { Text "E:/EDA/DDS/10k844/scan_divf_sinx/scan_divf_sinx.vhd" 6 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.500 ns) + CELL(1.200 ns) 8.200 ns SCANCNT4B:u1\|lpm_counter:CNT4_rtl_2\|alt_counter_f10ke:wysi_counter\|q\[3\] 2 REG LC6_B12 2 " "Info: 2: + IC(3.500 ns) + CELL(1.200 ns) = 8.200 ns; Loc. = LC6_B12; Fanout = 2; REG Node = 'SCANCNT4B:u1\|lpm_counter:CNT4_rtl_2\|alt_counter_f10ke:wysi_counter\|q\[3\]'" {  } { { "E:/EDA/DDS/10k844/scan_divf_sinx/db/scan_divf_sinx_cmp.qrpt" "" { Report "E:/EDA/DDS/10k844/scan_divf_sinx/db/scan_divf_sinx_cmp.qrpt" Compiler "scan_divf_sinx" "UNKNOWN" "V1" "E:/EDA/DDS/10k844/scan_divf_sinx/db/scan_divf_sinx.quartus_db" { Floorplan "E:/EDA/DDS/10k844/scan_divf_sinx/" "" "4.700 ns" { enable SCANCNT4B:u1|lpm_counter:CNT4_rtl_2|alt_counter_f10ke:wysi_counter|q[3] } "NODE_NAME" } "" } } { "alt_counter_f10ke.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/alt_counter_f10ke.tdf" 271 2 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.700 ns 57.32 % " "Info: Total cell delay = 4.700 ns ( 57.32 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.500 ns 42.68 % " "Info: Total interconnect delay = 3.500 ns ( 42.68 % )" {  } {  } 0}  } { { "E:/EDA/DDS/10k844/scan_divf_sinx/db/scan_divf_sinx_cmp.qrpt" "" { Report "E:/EDA/DDS/10k844/scan_divf_sinx/db/scan_divf_sinx_cmp.qrpt" Compiler "scan_divf_sinx" "UNKNOWN" "V1" "E:/EDA/DDS/10k844/scan_divf_sinx/db/scan_divf_sinx.quartus_db" { Floorplan "E:/EDA/DDS/10k844/scan_divf_sinx/" "" "8.200 ns" { enable SCANCNT4B:u1|lpm_counter:CNT4_rtl_2|alt_counter_f10ke:wysi_counter|q[3] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "8.200 ns" { enable enable~out SCANCNT4B:u1|lpm_counter:CNT4_rtl_2|alt_counter_f10ke:wysi_counter|q[3] } { 0.000ns 0.000ns 3.500ns } { 0.000ns 3.500ns 1.200ns } } }  } 0}  } { { "E:/EDA/DDS/10k844/scan_divf_sinx/db/scan_divf_sinx_cmp.qrpt" "" { Report "E:/EDA/DDS/10k844/scan_divf_sinx/db/scan_divf_sinx_cmp.qrpt" Compiler "scan_divf_sinx" "UNKNOWN" "V1" "E:/EDA/DDS/10k844/scan_divf_sinx/db/scan_divf_sinx.quartus_db" { Floorplan "E:/EDA/DDS/10k844/scan_divf_sinx/" "" "5.300 ns" { clock SCANCNT4B:u1|lpm_counter:CNT4_rtl_2|alt_counter_f10ke:wysi_counter|q[3] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "5.300 ns" { clock clock~out SCANCNT4B:u1|lpm_counter:CNT4_rtl_2|alt_counter_f10ke:wysi_counter|q[3] } { 0.000ns 0.000ns 2.500ns } { 0.000ns 2.800ns 0.000ns } } } { "E:/EDA/DDS/10k844/scan_divf_sinx/db/scan_divf_sinx_cmp.qrpt" "" { Report "E:/EDA/DDS/10k844/scan_divf_sinx/db/scan_divf_sinx_cmp.qrpt" Compiler "scan_divf_sinx" "UNKNOWN" "V1" "E:/EDA/DDS/10k844/scan_divf_sinx/db/scan_divf_sinx.quartus_db" { Floorplan "E:/EDA/DDS/10k844/scan_divf_sinx/" "" "8.200 ns" { enable SCANCNT4B:u1|lpm_counter:CNT4_rtl_2|alt_counter_f10ke:wysi_counter|q[3] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "8.200 ns" { enable enable~out SCANCNT4B:u1|lpm_counter:CNT4_rtl_2|alt_counter_f10ke:wysi_counter|q[3] } { 0.000ns 0.000ns 3.500ns } { 0.000ns 3.500ns 1.200ns } } }  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 2 s Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Fri Apr 14 21:34:26 2006 " "Info: Processing ended: Fri Apr 14 21:34:26 2006" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Info: Elapsed time: 00:00:03" {  } {  } 0}  } {  } 0}