scan_divf_sinx.tan.qmsg

在EDA开发软件QuartusII上利用VHDL语言实现DDS信号发生器

{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clock " "Info: Assuming node \"clock\" is an undefined clock" {  } { { "scan_divf_sinx.vhd" "" { Text "E:/EDA/DDS/10k844/scan_divf_sinx/scan_divf_sinx.vhd" 6 -1 0 } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "clock" } } } }  } 0}  } {  } 0}
{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "1 " "Warning: Found 1 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "divf16_sinx:u2\|divf:u1\|COUT " "Info: Detected ripple clock \"divf16_sinx:u2\|divf:u1\|COUT\" as buffer" {  } { { "divf.vhd" "" { Text "E:/EDA/DDS/10k844/scan_divf_sinx/divf.vhd" 9 -1 0 } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "divf16_sinx:u2\|divf:u1\|COUT" } } } }  } 0}  } {  } 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clock register divf16_sinx:u2\|singt3:u2\|lpm_counter:q_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[4\] register divf16_sinx:u2\|singt3:u2\|lpm_counter:q_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[6\] 64.1 MHz 15.6 ns Internal " "Info: Clock \"clock\" has Internal fmax of 64.1 MHz between source register \"divf16_sinx:u2\|singt3:u2\|lpm_counter:q_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[4\]\" and destination register \"divf16_sinx:u2\|singt3:u2\|lpm_counter:q_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[6\]\" (period= 15.6 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "12.000 ns + Longest register register " "Info: + Longest register to register delay is 12.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns divf16_sinx:u2\|singt3:u2\|lpm_counter:q_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[4\] 1 REG LC5_B13 31 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC5_B13; Fanout = 31; REG Node = 'divf16_sinx:u2\|singt3:u2\|lpm_counter:q_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[4\]'" {  } { { "E:/EDA/DDS/10k844/scan_divf_sinx/db/scan_divf_sinx_cmp.qrpt" "" { Report "E:/EDA/DDS/10k844/scan_divf_sinx/db/scan_divf_sinx_cmp.qrpt" Compiler "scan_divf_sinx" "UNKNOWN" "V1" "E:/EDA/DDS/10k844/scan_divf_sinx/db/scan_divf_sinx.quartus_db" { Floorplan "E:/EDA/DDS/10k844/scan_divf_sinx/" "" "" { divf16_sinx:u2|singt3:u2|lpm_counter:q_rtl_0|alt_counter_f10ke:wysi_counter|q[4] } "NODE_NAME" } "" } } { "alt_counter_f10ke.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/alt_counter_f10ke.tdf" 271 2 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.500 ns) + CELL(1.700 ns) 4.200 ns divf16_sinx:u2\|singt3:u2\|LessThan~60 2 COMB LC7_B17 1 " "Info: 2: + IC(2.500 ns) + CELL(1.700 ns) = 4.200 ns; Loc. = LC7_B17; Fanout = 1; COMB Node = 'divf16_sinx:u2\|singt3:u2\|LessThan~60'" {  } { { "E:/EDA/DDS/10k844/scan_divf_sinx/db/scan_divf_sinx_cmp.qrpt" "" { Report "E:/EDA/DDS/10k844/scan_divf_sinx/db/scan_divf_sinx_cmp.qrpt" Compiler "scan_divf_sinx" "UNKNOWN" "V1" "E:/EDA/DDS/10k844/scan_divf_sinx/db/scan_divf_sinx.quartus_db" { Floorplan "E:/EDA/DDS/10k844/scan_divf_sinx/" "" "4.200 ns" { divf16_sinx:u2|singt3:u2|lpm_counter:q_rtl_0|alt_counter_f10ke:wysi_counter|q[4] divf16_sinx:u2|singt3:u2|LessThan~60 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.500 ns) 5.700 ns divf16_sinx:u2\|singt3:u2\|LessThan~56 3 COMB LC8_B17 1 " "Info: 3: + IC(0.000 ns) + CELL(1.500 ns) = 5.700 ns; Loc. = LC8_B17; Fanout = 1; COMB Node = 'divf16_sinx:u2\|singt3:u2\|LessThan~56'" {  } { { "E:/EDA/DDS/10k844/scan_divf_sinx/db/scan_divf_sinx_cmp.qrpt" "" { Report "E:/EDA/DDS/10k844/scan_divf_sinx/db/scan_divf_sinx_cmp.qrpt" Compiler "scan_divf_sinx" "UNKNOWN" "V1" "E:/EDA/DDS/10k844/scan_divf_sinx/db/scan_divf_sinx.quartus_db" { Floorplan "E:/EDA/DDS/10k844/scan_divf_sinx/" "" "1.500 ns" { divf16_sinx:u2|singt3:u2|LessThan~60 divf16_sinx:u2|singt3:u2|LessThan~56 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.200 ns) + CELL(1.800 ns) 9.700 ns divf16_sinx:u2\|singt3:u2\|LessThan~58 4 COMB LC8_B13 11 " "Info: 4: + IC(2.200 ns) + CELL(1.800 ns) = 9.700 ns; Loc. = LC8_B13; Fanout = 11; COMB Node = 'divf16_sinx:u2\|singt3:u2\|LessThan~58'" {  } { { "E:/EDA/DDS/10k844/scan_divf_sinx/db/scan_divf_sinx_cmp.qrpt" "" { Report "E:/EDA/DDS/10k844/scan_divf_sinx/db/scan_divf_sinx_cmp.qrpt" Compiler "scan_divf_sinx" "UNKNOWN" "V1" "E:/EDA/DDS/10k844/scan_divf_sinx/db/scan_divf_sinx.quartus_db" { Floorplan "E:/EDA/DDS/10k844/scan_divf_sinx/" "" "4.000 ns" { divf16_sinx:u2|singt3:u2|LessThan~56 divf16_sinx:u2|singt3:u2|LessThan~58 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.600 ns) + CELL(1.700 ns) 12.000 ns divf16_sinx:u2\|singt3:u2\|lpm_counter:q_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[6\] 5 REG LC7_B13 10 " "Info: 5: + IC(0.600 ns) + CELL(1.700 ns) = 12.000 ns; Loc. = LC7_B13; Fanout = 10; REG Node = 'divf16_sinx:u2\|singt3:u2\|lpm_counter:q_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[6\]'" {  } { { "E:/EDA/DDS/10k844/scan_divf_sinx/db/scan_divf_sinx_cmp.qrpt" "" { Report "E:/EDA/DDS/10k844/scan_divf_sinx/db/scan_divf_sinx_cmp.qrpt" Compiler "scan_divf_sinx" "UNKNOWN" "V1" "E:/EDA/DDS/10k844/scan_divf_sinx/db/scan_divf_sinx.quartus_db" { Floorplan "E:/EDA/DDS/10k844/scan_divf_sinx/" "" "2.300 ns" { divf16_sinx:u2|singt3:u2|LessThan~58 divf16_sinx:u2|singt3:u2|lpm_counter:q_rtl_0|alt_counter_f10ke:wysi_counter|q[6] } "NODE_NAME" } "" } } { "alt_counter_f10ke.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/alt_counter_f10ke.tdf" 271 2 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "6.700 ns 55.83 % " "Info: Total cell delay = 6.700 ns ( 55.83 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.300 ns 44.17 % " "Info: Total interconnect delay = 5.300 ns ( 44.17 % )" {  } {  } 0}  } { { "E:/EDA/DDS/10k844/scan_divf_sinx/db/scan_divf_sinx_cmp.qrpt" "" { Report "E:/EDA/DDS/10k844/scan_divf_sinx/db/scan_divf_sinx_cmp.qrpt" Compiler "scan_divf_sinx" "UNKNOWN" "V1" "E:/EDA/DDS/10k844/scan_divf_sinx/db/scan_divf_sinx.quartus_db" { Floorplan "E:/EDA/DDS/10k844/scan_divf_sinx/" "" "12.000 ns" { divf16_sinx:u2|singt3:u2|lpm_counter:q_rtl_0|alt_counter_f10ke:wysi_counter|q[4] divf16_sinx:u2|singt3:u2|LessThan~60 divf16_sinx:u2|singt3:u2|LessThan~56 divf16_sinx:u2|singt3:u2|LessThan~58 divf16_sinx:u2|singt3:u2|lpm_counter:q_rtl_0|alt_counter_f10ke:wysi_counter|q[6] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "12.000 ns" { divf16_sinx:u2|singt3:u2|lpm_counter:q_rtl_0|alt_counter_f10ke:wysi_counter|q[4] divf16_sinx:u2|singt3:u2|LessThan~60 divf16_sinx:u2|singt3:u2|LessThan~56 divf16_sinx:u2|singt3:u2|LessThan~58 divf16_sinx:u2|singt3:u2|lpm_counter:q_rtl_0|alt_counter_f10ke:wysi_counter|q[6] } { 0.000ns 2.500ns 0.000ns 2.200ns 0.600ns } { 0.000ns 1.700ns 1.500ns 1.800ns 1.700ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock destination 11.000 ns + Shortest register " "Info: + Shortest clock path from clock \"clock\" to destination register is 11.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.800 ns) 2.800 ns clock 1 CLK PIN_2 15 " "Info: 1: + IC(0.000 ns) + CELL(2.800 ns) = 2.800 ns; Loc. = PIN_2; Fanout = 15; CLK Node = 'clock'" {  } { { "E:/EDA/DDS/10k844/scan_divf_sinx/db/scan_divf_sinx_cmp.qrpt" "" { Report "E:/EDA/DDS/10k844/scan_divf_sinx/db/scan_divf_sinx_cmp.qrpt" Compiler "scan_divf_sinx" "UNKNOWN" "V1" "E:/EDA/DDS/10k844/scan_divf_sinx/db/scan_divf_sinx.quartus_db" { Floorplan "E:/EDA/DDS/10k844/scan_divf_sinx/" "" "" { clock } "NODE_NAME" } "" } } { "scan_divf_sinx.vhd" "" { Text "E:/EDA/DDS/10k844/scan_divf_sinx/scan_divf_sinx.vhd" 6 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.500 ns) + CELL(1.100 ns) 6.400 ns divf16_sinx:u2\|divf:u1\|COUT 2 REG LC1_B10 11 " "Info: 2: + IC(2.500 ns) + CELL(1.100 ns) = 6.400 ns; Loc. = LC1_B10; Fanout = 11; REG Node = 'divf16_sinx:u2\|divf:u1\|COUT'" {  } { { "E:/EDA/DDS/10k844/scan_divf_sinx/db/scan_divf_sinx_cmp.qrpt" "" { Report "E:/EDA/DDS/10k844/scan_divf_sinx/db/scan_divf_sinx_cmp.qrpt" Compiler "scan_divf_sinx" "UNKNOWN" "V1" "E:/EDA/DDS/10k844/scan_divf_sinx/db/scan_divf_sinx.quartus_db" { Floorplan "E:/EDA/DDS/10k844/scan_divf_sinx/" "" "3.600 ns" { clock divf16_sinx:u2|divf:u1|COUT } "NODE_NAME" } "" } } { "divf.vhd" "" { Text "E:/EDA/DDS/10k844/scan_divf_sinx/divf.vhd" 9 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(4.600 ns) + CELL(0.000 ns) 11.000 ns divf16_sinx:u2\|singt3:u2\|lpm_counter:q_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[6\] 3 REG LC7_B13 10 " "Info: 3: + IC(4.600 ns) + CELL(0.000 ns) = 11.000 ns; Loc. = LC7_B13; Fanout = 10; REG Node = 'divf16_sinx:u2\|singt3:u2\|lpm_counter:q_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[6\]'" {  } { { "E:/EDA/DDS/10k844/scan_divf_sinx/db/scan_divf_sinx_cmp.qrpt" "" { Report "E:/EDA/DDS/10k844/scan_divf_sinx/db/scan_divf_sinx_cmp.qrpt" Compiler "scan_divf_sinx" "UNKNOWN" "V1" "E:/EDA/DDS/10k844/scan_divf_sinx/db/scan_divf_sinx.quartus_db" { Floorplan "E:/EDA/DDS/10k844/scan_divf_sinx/" "" "4.600 ns" { divf16_sinx:u2|divf:u1|COUT divf16_sinx:u2|singt3:u2|lpm_counter:q_rtl_0|alt_counter_f10ke:wysi_counter|q[6] } "NODE_NAME" } "" } } { "alt_counter_f10ke.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/alt_counter_f10ke.tdf" 271 2 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.900 ns 35.45 % " "Info: Total cell delay = 3.900 ns ( 35.45 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "7.100 ns 64.55 % " "Info: Total interconnect delay = 7.100 ns ( 64.55 % )" {  } {  } 0}  } { { "E:/EDA/DDS/10k844/scan_divf_sinx/db/scan_divf_sinx_cmp.qrpt" "" { Report "E:/EDA/DDS/10k844/scan_divf_sinx/db/scan_divf_sinx_cmp.qrpt" Compiler "scan_divf_sinx" "UNKNOWN" "V1" "E:/EDA/DDS/10k844/scan_divf_sinx/db/scan_divf_sinx.quartus_db" { Floorplan "E:/EDA/DDS/10k844/scan_divf_sinx/" "" "11.000 ns" { clock divf16_sinx:u2|divf:u1|COUT divf16_sinx:u2|singt3:u2|lpm_counter:q_rtl_0|alt_counter_f10ke:wysi_counter|q[6] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "11.000 ns" { clock clock~out divf16_sinx:u2|divf:u1|COUT divf16_sinx:u2|singt3:u2|lpm_counter:q_rtl_0|alt_counter_f10ke:wysi_counter|q[6] } { 0.000ns 0.000ns 2.500ns 4.600ns } { 0.000ns 2.800ns 1.100ns 0.000ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock source 11.000 ns - Longest register " "Info: - Longest clock path from clock \"clock\" to source register is 11.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.800 ns) 2.800 ns clock 1 CLK PIN_2 15 " "Info: 1: + IC(0.000 ns) + CELL(2.800 ns) = 2.800 ns; Loc. = PIN_2; Fanout = 15; CLK Node = 'clock'" {  } { { "E:/EDA/DDS/10k844/scan_divf_sinx/db/scan_divf_sinx_cmp.qrpt" "" { Report "E:/EDA/DDS/10k844/scan_divf_sinx/db/scan_divf_sinx_cmp.qrpt" Compiler "scan_divf_sinx" "UNKNOWN" "V1" "E:/EDA/DDS/10k844/scan_divf_sinx/db/scan_divf_sinx.quartus_db" { Floorplan "E:/EDA/DDS/10k844/scan_divf_sinx/" "" "" { clock } "NODE_NAME" } "" } } { "scan_divf_sinx.vhd" "" { Text "E:/EDA/DDS/10k844/scan_divf_sinx/scan_divf_sinx.vhd" 6 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.500 ns) + CELL(1.100 ns) 6.400 ns divf16_sinx:u2\|divf:u1\|COUT 2 REG LC1_B10 11 " "Info: 2: + IC(2.500 ns) + CELL(1.100 ns) = 6.400 ns; Loc. = LC1_B10; Fanout = 11; REG Node = 'divf16_sinx:u2\|divf:u1\|COUT'" {  } { { "E:/EDA/DDS/10k844/scan_divf_sinx/db/scan_divf_sinx_cmp.qrpt" "" { Report "E:/EDA/DDS/10k844/scan_divf_sinx/db/scan_divf_sinx_cmp.qrpt" Compiler "scan_divf_sinx" "UNKNOWN" "V1" "E:/EDA/DDS/10k844/scan_divf_sinx/db/scan_divf_sinx.quartus_db" { Floorplan "E:/EDA/DDS/10k844/scan_divf_sinx/" "" "3.600 ns" { clock divf16_sinx:u2|divf:u1|COUT } "NODE_NAME" } "" } } { "divf.vhd" "" { Text "E:/EDA/DDS/10k844/scan_divf_sinx/divf.vhd" 9 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(4.600 ns) + CELL(0.000 ns) 11.000 ns divf16_sinx:u2\|singt3:u2\|lpm_counter:q_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[4\] 3 REG LC5_B13 31 " "Info: 3: + IC(4.600 ns) + CELL(0.000 ns) = 11.000 ns; Loc. = LC5_B13; Fanout = 31; REG Node = 'divf16_sinx:u2\|singt3:u2\|lpm_counter:q_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[4\]'" {  } { { "E:/EDA/DDS/10k844/scan_divf_sinx/db/scan_divf_sinx_cmp.qrpt" "" { Report "E:/EDA/DDS/10k844/scan_divf_sinx/db/scan_divf_sinx_cmp.qrpt" Compiler "scan_divf_sinx" "UNKNOWN" "V1" "E:/EDA/DDS/10k844/scan_divf_sinx/db/scan_divf_sinx.quartus_db" { Floorplan "E:/EDA/DDS/10k844/scan_divf_sinx/" "" "4.600 ns" { divf16_sinx:u2|divf:u1|COUT divf16_sinx:u2|singt3:u2|lpm_counter:q_rtl_0|alt_counter_f10ke:wysi_counter|q[4] } "NODE_NAME" } "" } } { "alt_counter_f10ke.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/alt_counter_f10ke.tdf" 271 2 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.900 ns 35.45 % " "Info: Total cell delay = 3.900 ns ( 35.45 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "7.100 ns 64.55 % " "Info: Total interconnect delay = 7.100 ns ( 64.55 % )" {  } {  } 0}  } { { "E:/EDA/DDS/10k844/scan_divf_sinx/db/scan_divf_sinx_cmp.qrpt" "" { Report "E:/EDA/DDS/10k844/scan_divf_sinx/db/scan_divf_sinx_cmp.qrpt" Compiler "scan_divf_sinx" "UNKNOWN" "V1" "E:/EDA/DDS/10k844/scan_divf_sinx/db/scan_divf_sinx.quartus_db" { Floorplan "E:/EDA/DDS/10k844/scan_divf_sinx/" "" "11.000 ns" { clock divf16_sinx:u2|divf:u1|COUT divf16_sinx:u2|singt3:u2|lpm_counter:q_rtl_0|alt_counter_f10ke:wysi_counter|q[4] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "11.000 ns" { clock clock~out divf16_sinx:u2|divf:u1|COUT divf16_sinx:u2|singt3:u2|lpm_counter:q_rtl_0|alt_counter_f10ke:wysi_counter|q[4] } { 0.000ns 0.000ns 2.500ns 4.600ns } { 0.000ns 2.800ns 1.100ns 0.000ns } } }  } 0}  } { { "E:/EDA/DDS/10k844/scan_divf_sinx/db/scan_divf_sinx_cmp.qrpt" "" { Report "E:/EDA/DDS/10k844/scan_divf_sinx/db/scan_divf_sinx_cmp.qrpt" Compiler "scan_divf_sinx" "UNKNOWN" "V1" "E:/EDA/DDS/10k844/scan_divf_sinx/db/scan_divf_sinx.quartus_db" { Floorplan "E:/EDA/DDS/10k844/scan_divf_sinx/" "" "11.000 ns" { clock divf16_sinx:u2|divf:u1|COUT divf16_sinx:u2|singt3:u2|lpm_counter:q_rtl_0|alt_counter_f10ke:wysi_counter|q[6] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "11.000 ns" { clock clock~out divf16_sinx:u2|divf:u1|COUT divf16_sinx:u2|singt3:u2|lpm_counter:q_rtl_0|alt_counter_f10ke:wysi_counter|q[6] } { 0.000ns 0.000ns 2.500ns 4.600ns } { 0.000ns 2.800ns 1.100ns 0.000ns } } } { "E:/EDA/DDS/10k844/scan_divf_sinx/db/scan_divf_sinx_cmp.qrpt" "" { Report "E:/EDA/DDS/10k844/scan_divf_sinx/db/scan_divf_sinx_cmp.qrpt" Compiler "scan_divf_sinx" "UNKNOWN" "V1" "E:/EDA/DDS/10k844/scan_divf_sinx/db/scan_divf_sinx.quartus_db" { Floorplan "E:/EDA/DDS/10k844/scan_divf_sinx/" "" "11.000 ns" { clock divf16_sinx:u2|divf:u1|COUT divf16_sinx:u2|singt3:u2|lpm_counter:q_rtl_0|alt_counter_f10ke:wysi_counter|q[4] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "11.000 ns" { clock clock~out divf16_sinx:u2|divf:u1|COUT divf16_sinx:u2|singt3:u2|lpm_counter:q_rtl_0|alt_counter_f10ke:wysi_counter|q[4] } { 0.000ns 0.000ns 2.500ns 4.600ns } { 0.000ns 2.800ns 1.100ns 0.000ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.100 ns + " "Info: + Micro clock to output delay of source is 1.100 ns" {  } { { "alt_counter_f10ke.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/alt_counter_f10ke.tdf" 271 2 0 } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "2.500 ns + " "Info: + Micro setup delay of destination is 2.500 ns" {  } { { "alt_counter_f10ke.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/alt_counter_f10ke.tdf" 271 2 0 } }  } 0}  } { { "E:/EDA/DDS/10k844/scan_divf_sinx/db/scan_divf_sinx_cmp.qrpt" "" { Report "E:/EDA/DDS/10k844/scan_divf_sinx/db/scan_divf_sinx_cmp.qrpt" Compiler "scan_divf_sinx" "UNKNOWN" "V1" "E:/EDA/DDS/10k844/scan_divf_sinx/db/scan_divf_sinx.quartus_db" { Floorplan "E:/EDA/DDS/10k844/scan_divf_sinx/" "" "12.000 ns" { divf16_sinx:u2|singt3:u2|lpm_counter:q_rtl_0|alt_counter_f10ke:wysi_counter|q[4] divf16_sinx:u2|singt3:u2|LessThan~60 divf16_sinx:u2|singt3:u2|LessThan~56 divf16_sinx:u2|singt3:u2|LessThan~58 divf16_sinx:u2|singt3:u2|lpm_counter:q_rtl_0|alt_counter_f10ke:wysi_counter|q[6] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "12.000 ns" { divf16_sinx:u2|singt3:u2|lpm_counter:q_rtl_0|alt_counter_f10ke:wysi_counter|q[4] divf16_sinx:u2|singt3:u2|LessThan~60 divf16_sinx:u2|singt3:u2|LessThan~56 divf16_sinx:u2|singt3:u2|LessThan~58 divf16_sinx:u2|singt3:u2|lpm_counter:q_rtl_0|alt_counter_f10ke:wysi_counter|q[6] } { 0.000ns 2.500ns 0.000ns 2.200ns 0.600ns } { 0.000ns 1.700ns 1.500ns 1.800ns 1.700ns } } } { "E:/EDA/DDS/10k844/scan_divf_sinx/db/scan_divf_sinx_cmp.qrpt" "" { Report "E:/EDA/DDS/10k844/scan_divf_sinx/db/scan_divf_sinx_cmp.qrpt" Compiler "scan_divf_sinx" "UNKNOWN" "V1" "E:/EDA/DDS/10k844/scan_divf_sinx/db/scan_divf_sinx.quartus_db" { Floorplan "E:/EDA/DDS/10k844/scan_divf_sinx/" "" "11.000 ns" { clock divf16_sinx:u2|divf:u1|COUT divf16_sinx:u2|singt3:u2|lpm_counter:q_rtl_0|alt_counter_f10ke:wysi_counter|q[6] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "11.000 ns" { clock clock~out divf16_sinx:u2|divf:u1|COUT divf16_sinx:u2|singt3:u2|lpm_counter:q_rtl_0|alt_counter_f10ke:wysi_counter|q[6] } { 0.000ns 0.000ns 2.500ns 4.600ns } { 0.000ns 2.800ns 1.100ns 0.000ns } } } { "E:/EDA/DDS/10k844/scan_divf_sinx/db/scan_divf_sinx_cmp.qrpt" "" { Report "E:/EDA/DDS/10k844/scan_divf_sinx/db/scan_divf_sinx_cmp.qrpt" Compiler "scan_divf_sinx" "UNKNOWN" "V1" "E:/EDA/DDS/10k844/scan_divf_sinx/db/scan_divf_sinx.quartus_db" { Floorplan "E:/EDA/DDS/10k844/scan_divf_sinx/" "" "11.000 ns" { clock divf16_sinx:u2|divf:u1|COUT divf16_sinx:u2|singt3:u2|lpm_counter:q_rtl_0|alt_counter_f10ke:wysi_counter|q[4] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "11.000 ns" { clock clock~out divf16_sinx:u2|divf:u1|COUT divf16_sinx:u2|singt3:u2|lpm_counter:q_rtl_0|alt_counter_f10ke:wysi_counter|q[4] } { 0.000ns 0.000ns 2.500ns 4.600ns } { 0.000ns 2.800ns 1.100ns 0.000ns } } }  } 0}