📄 cnt8b.tan.qmsg
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{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "CLK register lpm_counter:Q1_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[4\] register C~reg0 96.15 MHz 10.4 ns Internal " "Info: Clock \"CLK\" has Internal fmax of 96.15 MHz between source register \"lpm_counter:Q1_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[4\]\" and destination register \"C~reg0\" (period= 10.4 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.800 ns + Longest register register " "Info: + Longest register to register delay is 6.800 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns lpm_counter:Q1_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[4\] 1 REG LC5_C14 5 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC5_C14; Fanout = 5; REG Node = 'lpm_counter:Q1_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[4\]'" { } { { "E:/EDA/DDS/INIT_DATA/db/CNT8B_cmp.qrpt" "" { Report "E:/EDA/DDS/INIT_DATA/db/CNT8B_cmp.qrpt" Compiler "CNT8B" "UNKNOWN" "V1" "E:/EDA/DDS/INIT_DATA/db/CNT8B.quartus_db" { Floorplan "E:/EDA/DDS/INIT_DATA/" "" "" { lpm_counter:Q1_rtl_0|alt_counter_f10ke:wysi_counter|q[4] } "NODE_NAME" } "" } } { "alt_counter_f10ke.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/alt_counter_f10ke.tdf" 271 2 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.200 ns) + CELL(2.300 ns) 4.500 ns reduce_nor~41 2 COMB LC2_C13 1 " "Info: 2: + IC(2.200 ns) + CELL(2.300 ns) = 4.500 ns; Loc. = LC2_C13; Fanout = 1; COMB Node = 'reduce_nor~41'" { } { { "E:/EDA/DDS/INIT_DATA/db/CNT8B_cmp.qrpt" "" { Report "E:/EDA/DDS/INIT_DATA/db/CNT8B_cmp.qrpt" Compiler "CNT8B" "UNKNOWN" "V1" "E:/EDA/DDS/INIT_DATA/db/CNT8B.quartus_db" { Floorplan "E:/EDA/DDS/INIT_DATA/" "" "4.500 ns" { lpm_counter:Q1_rtl_0|alt_counter_f10ke:wysi_counter|q[4] reduce_nor~41 } "NODE_NAME" } "" } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.600 ns) + CELL(1.700 ns) 6.800 ns C~reg0 3 REG LC3_C13 1 " "Info: 3: + IC(0.600 ns) + CELL(1.700 ns) = 6.800 ns; Loc. = LC3_C13; Fanout = 1; REG Node = 'C~reg0'" { } { { "E:/EDA/DDS/INIT_DATA/db/CNT8B_cmp.qrpt" "" { Report "E:/EDA/DDS/INIT_DATA/db/CNT8B_cmp.qrpt" Compiler "CNT8B" "UNKNOWN" "V1" "E:/EDA/DDS/INIT_DATA/db/CNT8B.quartus_db" { Floorplan "E:/EDA/DDS/INIT_DATA/" "" "2.300 ns" { reduce_nor~41 C~reg0 } "NODE_NAME" } "" } } { "CNT8B.vhd" "" { Text "E:/EDA/DDS/INIT_DATA/CNT8B.vhd" 18 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.000 ns 58.82 % " "Info: Total cell delay = 4.000 ns ( 58.82 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.800 ns 41.18 % " "Info: Total interconnect delay = 2.800 ns ( 41.18 % )" { } { } 0} } { { "E:/EDA/DDS/INIT_DATA/db/CNT8B_cmp.qrpt" "" { Report "E:/EDA/DDS/INIT_DATA/db/CNT8B_cmp.qrpt" Compiler "CNT8B" "UNKNOWN" "V1" "E:/EDA/DDS/INIT_DATA/db/CNT8B.quartus_db" { Floorplan "E:/EDA/DDS/INIT_DATA/" "" "6.800 ns" { lpm_counter:Q1_rtl_0|alt_counter_f10ke:wysi_counter|q[4] reduce_nor~41 C~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "6.800 ns" { lpm_counter:Q1_rtl_0|alt_counter_f10ke:wysi_counter|q[4] reduce_nor~41 C~reg0 } { 0.000ns 2.200ns 0.600ns } { 0.000ns 2.300ns 1.700ns } } } } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK destination 5.300 ns + Shortest register " "Info: + Shortest clock path from clock \"CLK\" to destination register is 5.300 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.800 ns) 2.800 ns CLK 1 CLK PIN_43 16 " "Info: 1: + IC(0.000 ns) + CELL(2.800 ns) = 2.800 ns; Loc. = PIN_43; Fanout = 16; CLK Node = 'CLK'" { } { { "E:/EDA/DDS/INIT_DATA/db/CNT8B_cmp.qrpt" "" { Report "E:/EDA/DDS/INIT_DATA/db/CNT8B_cmp.qrpt" Compiler "CNT8B" "UNKNOWN" "V1" "E:/EDA/DDS/INIT_DATA/db/CNT8B.quartus_db" { Floorplan "E:/EDA/DDS/INIT_DATA/" "" "" { CLK } "NODE_NAME" } "" } } { "CNT8B.vhd" "" { Text "E:/EDA/DDS/INIT_DATA/CNT8B.vhd" 6 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.500 ns) + CELL(0.000 ns) 5.300 ns C~reg0 2 REG LC3_C13 1 " "Info: 2: + IC(2.500 ns) + CELL(0.000 ns) = 5.300 ns; Loc. = LC3_C13; Fanout = 1; REG Node = 'C~reg0'" { } { { "E:/EDA/DDS/INIT_DATA/db/CNT8B_cmp.qrpt" "" { Report "E:/EDA/DDS/INIT_DATA/db/CNT8B_cmp.qrpt" Compiler "CNT8B" "UNKNOWN" "V1" "E:/EDA/DDS/INIT_DATA/db/CNT8B.quartus_db" { Floorplan "E:/EDA/DDS/INIT_DATA/" "" "2.500 ns" { CLK C~reg0 } "NODE_NAME" } "" } } { "CNT8B.vhd" "" { Text "E:/EDA/DDS/INIT_DATA/CNT8B.vhd" 18 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.800 ns 52.83 % " "Info: Total cell delay = 2.800 ns ( 52.83 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.500 ns 47.17 % " "Info: Total interconnect delay = 2.500 ns ( 47.17 % )" { } { } 0} } { { "E:/EDA/DDS/INIT_DATA/db/CNT8B_cmp.qrpt" "" { Report "E:/EDA/DDS/INIT_DATA/db/CNT8B_cmp.qrpt" Compiler "CNT8B" "UNKNOWN" "V1" "E:/EDA/DDS/INIT_DATA/db/CNT8B.quartus_db" { Floorplan "E:/EDA/DDS/INIT_DATA/" "" "5.300 ns" { CLK C~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "5.300 ns" { CLK CLK~out C~reg0 } { 0.000ns 0.000ns 2.500ns } { 0.000ns 2.800ns 0.000ns } } } } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK source 5.300 ns - Longest register " "Info: - Longest clock path from clock \"CLK\" to source register is 5.300 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.800 ns) 2.800 ns CLK 1 CLK PIN_43 16 " "Info: 1: + IC(0.000 ns) + CELL(2.800 ns) = 2.800 ns; Loc. = PIN_43; Fanout = 16; CLK Node = 'CLK'" { } { { "E:/EDA/DDS/INIT_DATA/db/CNT8B_cmp.qrpt" "" { Report "E:/EDA/DDS/INIT_DATA/db/CNT8B_cmp.qrpt" Compiler "CNT8B" "UNKNOWN" "V1" "E:/EDA/DDS/INIT_DATA/db/CNT8B.quartus_db" { Floorplan "E:/EDA/DDS/INIT_DATA/" "" "" { CLK } "NODE_NAME" } "" } } { "CNT8B.vhd" "" { Text "E:/EDA/DDS/INIT_DATA/CNT8B.vhd" 6 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.500 ns) + CELL(0.000 ns) 5.300 ns lpm_counter:Q1_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[4\] 2 REG LC5_C14 5 " "Info: 2: + IC(2.500 ns) + CELL(0.000 ns) = 5.300 ns; Loc. = LC5_C14; Fanout = 5; REG Node = 'lpm_counter:Q1_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[4\]'" { } { { "E:/EDA/DDS/INIT_DATA/db/CNT8B_cmp.qrpt" "" { Report "E:/EDA/DDS/INIT_DATA/db/CNT8B_cmp.qrpt" Compiler "CNT8B" "UNKNOWN" "V1" "E:/EDA/DDS/INIT_DATA/db/CNT8B.quartus_db" { Floorplan "E:/EDA/DDS/INIT_DATA/" "" "2.500 ns" { CLK lpm_counter:Q1_rtl_0|alt_counter_f10ke:wysi_counter|q[4] } "NODE_NAME" } "" } } { "alt_counter_f10ke.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/alt_counter_f10ke.tdf" 271 2 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.800 ns 52.83 % " "Info: Total cell delay = 2.800 ns ( 52.83 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.500 ns 47.17 % " "Info: Total interconnect delay = 2.500 ns ( 47.17 % )" { } { } 0} } { { "E:/EDA/DDS/INIT_DATA/db/CNT8B_cmp.qrpt" "" { Report "E:/EDA/DDS/INIT_DATA/db/CNT8B_cmp.qrpt" Compiler "CNT8B" "UNKNOWN" "V1" "E:/EDA/DDS/INIT_DATA/db/CNT8B.quartus_db" { Floorplan "E:/EDA/DDS/INIT_DATA/" "" "5.300 ns" { CLK lpm_counter:Q1_rtl_0|alt_counter_f10ke:wysi_counter|q[4] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "5.300 ns" { CLK CLK~out lpm_counter:Q1_rtl_0|alt_counter_f10ke:wysi_counter|q[4] } { 0.000ns 0.000ns 2.500ns } { 0.000ns 2.800ns 0.000ns } } } } 0} } { { "E:/EDA/DDS/INIT_DATA/db/CNT8B_cmp.qrpt" "" { Report "E:/EDA/DDS/INIT_DATA/db/CNT8B_cmp.qrpt" Compiler "CNT8B" "UNKNOWN" "V1" "E:/EDA/DDS/INIT_DATA/db/CNT8B.quartus_db" { Floorplan "E:/EDA/DDS/INIT_DATA/" "" "5.300 ns" { CLK C~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "5.300 ns" { CLK CLK~out C~reg0 } { 0.000ns 0.000ns 2.500ns } { 0.000ns 2.800ns 0.000ns } } } { "E:/EDA/DDS/INIT_DATA/db/CNT8B_cmp.qrpt" "" { Report "E:/EDA/DDS/INIT_DATA/db/CNT8B_cmp.qrpt" Compiler "CNT8B" "UNKNOWN" "V1" "E:/EDA/DDS/INIT_DATA/db/CNT8B.quartus_db" { Floorplan "E:/EDA/DDS/INIT_DATA/" "" "5.300 ns" { CLK lpm_counter:Q1_rtl_0|alt_counter_f10ke:wysi_counter|q[4] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "5.300 ns" { CLK CLK~out lpm_counter:Q1_rtl_0|alt_counter_f10ke:wysi_counter|q[4] } { 0.000ns 0.000ns 2.500ns } { 0.000ns 2.800ns 0.000ns } } } } 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.100 ns + " "Info: + Micro clock to output delay of source is 1.100 ns" { } { { "alt_counter_f10ke.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/alt_counter_f10ke.tdf" 271 2 0 } } } 0} { "Info" "ITDB_FULL_TSU_DELAY" "2.500 ns + " "Info: + Micro setup delay of destination is 2.500 ns" { } { { "CNT8B.vhd" "" { Text "E:/EDA/DDS/INIT_DATA/CNT8B.vhd" 18 -1 0 } } } 0} } { { "E:/EDA/DDS/INIT_DATA/db/CNT8B_cmp.qrpt" "" { Report "E:/EDA/DDS/INIT_DATA/db/CNT8B_cmp.qrpt" Compiler "CNT8B" "UNKNOWN" "V1" "E:/EDA/DDS/INIT_DATA/db/CNT8B.quartus_db" { Floorplan "E:/EDA/DDS/INIT_DATA/" "" "6.800 ns" { lpm_counter:Q1_rtl_0|alt_counter_f10ke:wysi_counter|q[4] reduce_nor~41 C~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "6.800 ns" { lpm_counter:Q1_rtl_0|alt_counter_f10ke:wysi_counter|q[4] reduce_nor~41 C~reg0 } { 0.000ns 2.200ns 0.600ns } { 0.000ns 2.300ns 1.700ns } } } { "E:/EDA/DDS/INIT_DATA/db/CNT8B_cmp.qrpt" "" { Report "E:/EDA/DDS/INIT_DATA/db/CNT8B_cmp.qrpt" Compiler "CNT8B" "UNKNOWN" "V1" "E:/EDA/DDS/INIT_DATA/db/CNT8B.quartus_db" { Floorplan "E:/EDA/DDS/INIT_DATA/" "" "5.300 ns" { CLK C~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "5.300 ns" { CLK CLK~out C~reg0 } { 0.000ns 0.000ns 2.500ns } { 0.000ns 2.800ns 0.000ns } } } { "E:/EDA/DDS/INIT_DATA/db/CNT8B_cmp.qrpt" "" { Report "E:/EDA/DDS/INIT_DATA/db/CNT8B_cmp.qrpt" Compiler "CNT8B" "UNKNOWN" "V1" "E:/EDA/DDS/INIT_DATA/db/CNT8B.quartus_db" { Floorplan "E:/EDA/DDS/INIT_DATA/" "" "5.300 ns" { CLK lpm_counter:Q1_rtl_0|alt_counter_f10ke:wysi_counter|q[4] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "5.300 ns" { CLK CLK~out lpm_counter:Q1_rtl_0|alt_counter_f10ke:wysi_counter|q[4] } { 0.000ns 0.000ns 2.500ns } { 0.000ns 2.800ns 0.000ns } } } } 0}
{ "Info" "ITDB_TSU_RESULT" "lpm_counter:Q1_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[0\] EN CLK 3.600 ns register " "Info: tsu for register \"lpm_counter:Q1_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[0\]\" (data pin = \"EN\", clock pin = \"CLK\") is 3.600 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.400 ns + Longest pin register " "Info: + Longest pin to register delay is 6.400 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.800 ns) 2.800 ns EN 1 PIN PIN_84 31 " "Info: 1: + IC(0.000 ns) + CELL(2.800 ns) = 2.800 ns; Loc. = PIN_84; Fanout = 31; PIN Node = 'EN'" { } { { "E:/EDA/DDS/INIT_DATA/db/CNT8B_cmp.qrpt" "" { Report "E:/EDA/DDS/INIT_DATA/db/CNT8B_cmp.qrpt" Compiler "CNT8B" "UNKNOWN" "V1" "E:/EDA/DDS/INIT_DATA/db/CNT8B.quartus_db" { Floorplan "E:/EDA/DDS/INIT_DATA/" "" "" { EN } "NODE_NAME" } "" } } { "CNT8B.vhd" "" { Text "E:/EDA/DDS/INIT_DATA/CNT8B.vhd" 6 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.900 ns) + CELL(1.700 ns) 6.400 ns lpm_counter:Q1_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[0\] 2 REG LC1_C14 5 " "Info: 2: + IC(1.900 ns) + CELL(1.700 ns) = 6.400 ns; Loc. = LC1_C14; Fanout = 5; REG Node = 'lpm_counter:Q1_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[0\]'" { } { { "E:/EDA/DDS/INIT_DATA/db/CNT8B_cmp.qrpt" "" { Report "E:/EDA/DDS/INIT_DATA/db/CNT8B_cmp.qrpt" Compiler "CNT8B" "UNKNOWN" "V1" "E:/EDA/DDS/INIT_DATA/db/CNT8B.quartus_db" { Floorplan "E:/EDA/DDS/INIT_DATA/" "" "3.600 ns" { EN lpm_counter:Q1_rtl_0|alt_counter_f10ke:wysi_counter|q[0] } "NODE_NAME" } "" } } { "alt_counter_f10ke.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/alt_counter_f10ke.tdf" 271 2 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.500 ns 70.31 % " "Info: Total cell delay = 4.500 ns ( 70.31 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.900 ns 29.69 % " "Info: Total interconnect delay = 1.900 ns ( 29.69 % )" { } { } 0} } { { "E:/EDA/DDS/INIT_DATA/db/CNT8B_cmp.qrpt" "" { Report "E:/EDA/DDS/INIT_DATA/db/CNT8B_cmp.qrpt" Compiler "CNT8B" "UNKNOWN" "V1" "E:/EDA/DDS/INIT_DATA/db/CNT8B.quartus_db" { Floorplan "E:/EDA/DDS/INIT_DATA/" "" "6.400 ns" { EN lpm_counter:Q1_rtl_0|alt_counter_f10ke:wysi_counter|q[0] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "6.400 ns" { EN EN~out lpm_counter:Q1_rtl_0|alt_counter_f10ke:wysi_counter|q[0] } { 0.000ns 0.000ns 1.900ns } { 0.000ns 2.800ns 1.700ns } } } } 0} { "Info" "ITDB_FULL_TSU_DELAY" "2.500 ns + " "Info: + Micro setup delay of destination is 2.500 ns" { } { { "alt_counter_f10ke.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/alt_counter_f10ke.tdf" 271 2 0 } } } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK destination 5.300 ns - Shortest register " "Info: - Shortest clock path from clock \"CLK\" to destination register is 5.300 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.800 ns) 2.800 ns CLK 1 CLK PIN_43 16 " "Info: 1: + IC(0.000 ns) + CELL(2.800 ns) = 2.800 ns; Loc. = PIN_43; Fanout = 16; CLK Node = 'CLK'" { } { { "E:/EDA/DDS/INIT_DATA/db/CNT8B_cmp.qrpt" "" { Report "E:/EDA/DDS/INIT_DATA/db/CNT8B_cmp.qrpt" Compiler "CNT8B" "UNKNOWN" "V1" "E:/EDA/DDS/INIT_DATA/db/CNT8B.quartus_db" { Floorplan "E:/EDA/DDS/INIT_DATA/" "" "" { CLK } "NODE_NAME" } "" } } { "CNT8B.vhd" "" { Text "E:/EDA/DDS/INIT_DATA/CNT8B.vhd" 6 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.500 ns) + CELL(0.000 ns) 5.300 ns lpm_counter:Q1_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[0\] 2 REG LC1_C14 5 " "Info: 2: + IC(2.500 ns) + CELL(0.000 ns) = 5.300 ns; Loc. = LC1_C14; Fanout = 5; REG Node = 'lpm_counter:Q1_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[0\]'" { } { { "E:/EDA/DDS/INIT_DATA/db/CNT8B_cmp.qrpt" "" { Report "E:/EDA/DDS/INIT_DATA/db/CNT8B_cmp.qrpt" Compiler "CNT8B" "UNKNOWN" "V1" "E:/EDA/DDS/INIT_DATA/db/CNT8B.quartus_db" { Floorplan "E:/EDA/DDS/INIT_DATA/" "" "2.500 ns" { CLK lpm_counter:Q1_rtl_0|alt_counter_f10ke:wysi_counter|q[0] } "NODE_NAME" } "" } } { "alt_counter_f10ke.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/alt_counter_f10ke.tdf" 271 2 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.800 ns 52.83 % " "Info: Total cell delay = 2.800 ns ( 52.83 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.500 ns 47.17 % " "Info: Total interconnect delay = 2.500 ns ( 47.17 % )" { } { } 0} } { { "E:/EDA/DDS/INIT_DATA/db/CNT8B_cmp.qrpt" "" { Report "E:/EDA/DDS/INIT_DATA/db/CNT8B_cmp.qrpt" Compiler "CNT8B" "UNKNOWN" "V1" "E:/EDA/DDS/INIT_DATA/db/CNT8B.quartus_db" { Floorplan "E:/EDA/DDS/INIT_DATA/" "" "5.300 ns" { CLK lpm_counter:Q1_rtl_0|alt_counter_f10ke:wysi_counter|q[0] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "5.300 ns" { CLK CLK~out lpm_counter:Q1_rtl_0|alt_counter_f10ke:wysi_counter|q[0] } { 0.000ns 0.000ns 2.500ns } { 0.000ns 2.800ns 0.000ns } } } } 0} } { { "E:/EDA/DDS/INIT_DATA/db/CNT8B_cmp.qrpt" "" { Report "E:/EDA/DDS/INIT_DATA/db/CNT8B_cmp.qrpt" Compiler "CNT8B" "UNKNOWN" "V1" "E:/EDA/DDS/INIT_DATA/db/CNT8B.quartus_db" { Floorplan "E:/EDA/DDS/INIT_DATA/" "" "6.400 ns" { EN lpm_counter:Q1_rtl_0|alt_counter_f10ke:wysi_counter|q[0] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "6.400 ns" { EN EN~out lpm_counter:Q1_rtl_0|alt_counter_f10ke:wysi_counter|q[0] } { 0.000ns 0.000ns 1.900ns } { 0.000ns 2.800ns 1.700ns } } } { "E:/EDA/DDS/INIT_DATA/db/CNT8B_cmp.qrpt" "" { Report "E:/EDA/DDS/INIT_DATA/db/CNT8B_cmp.qrpt" Compiler "CNT8B" "UNKNOWN" "V1" "E:/EDA/DDS/INIT_DATA/db/CNT8B.quartus_db" { Floorplan "E:/EDA/DDS/INIT_DATA/" "" "5.300 ns" { CLK lpm_counter:Q1_rtl_0|alt_counter_f10ke:wysi_counter|q[0] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "5.300 ns" { CLK CLK~out lpm_counter:Q1_rtl_0|alt_counter_f10ke:wysi_counter|q[0] } { 0.000ns 0.000ns 2.500ns } { 0.000ns 2.800ns 0.000ns } } } } 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "CLK Q\[7\] lpm_counter:Q1_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[7\] 14.800 ns register " "Info: tco from clock \"CLK\" to destination pin \"Q\[7\]\" through register \"lpm_counter:Q1_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[7\]\" is 14.800 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK source 5.300 ns + Longest register " "Info: + Longest clock path from clock \"CLK\" to source register is 5.300 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.800 ns) 2.800 ns CLK 1 CLK PIN_43 16 " "Info: 1: + IC(0.000 ns) + CELL(2.800 ns) = 2.800 ns; Loc. = PIN_43; Fanout = 16; CLK Node = 'CLK'" { } { { "E:/EDA/DDS/INIT_DATA/db/CNT8B_cmp.qrpt" "" { Report "E:/EDA/DDS/INIT_DATA/db/CNT8B_cmp.qrpt" Compiler "CNT8B" "UNKNOWN" "V1" "E:/EDA/DDS/INIT_DATA/db/CNT8B.quartus_db" { Floorplan "E:/EDA/DDS/INIT_DATA/" "" "" { CLK } "NODE_NAME" } "" } } { "CNT8B.vhd" "" { Text "E:/EDA/DDS/INIT_DATA/CNT8B.vhd" 6 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.500 ns) + CELL(0.000 ns) 5.300 ns lpm_counter:Q1_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[7\] 2 REG LC8_C14 3 " "Info: 2: + IC(2.500 ns) + CELL(0.000 ns) = 5.300 ns; Loc. = LC8_C14; Fanout = 3; REG Node = 'lpm_counter:Q1_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[7\]'" { } { { "E:/EDA/DDS/INIT_DATA/db/CNT8B_cmp.qrpt" "" { Report "E:/EDA/DDS/INIT_DATA/db/CNT8B_cmp.qrpt" Compiler "CNT8B" "UNKNOWN" "V1" "E:/EDA/DDS/INIT_DATA/db/CNT8B.quartus_db" { Floorplan "E:/EDA/DDS/INIT_DATA/" "" "2.500 ns" { CLK lpm_counter:Q1_rtl_0|alt_counter_f10ke:wysi_counter|q[7] } "NODE_NAME" } "" } } { "alt_counter_f10ke.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/alt_counter_f10ke.tdf" 271 2 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.800 ns 52.83 % " "Info: Total cell delay = 2.800 ns ( 52.83 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.500 ns 47.17 % " "Info: Total interconnect delay = 2.500 ns ( 47.17 % )" { } { } 0} } { { "E:/EDA/DDS/INIT_DATA/db/CNT8B_cmp.qrpt" "" { Report "E:/EDA/DDS/INIT_DATA/db/CNT8B_cmp.qrpt" Compiler "CNT8B" "UNKNOWN" "V1" "E:/EDA/DDS/INIT_DATA/db/CNT8B.quartus_db" { Floorplan "E:/EDA/DDS/INIT_DATA/" "" "5.300 ns" { CLK lpm_counter:Q1_rtl_0|alt_counter_f10ke:wysi_counter|q[7] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "5.300 ns" { CLK CLK~out lpm_counter:Q1_rtl_0|alt_counter_f10ke:wysi_counter|q[7] } { 0.000ns 0.000ns 2.500ns } { 0.000ns 2.800ns 0.000ns } } } } 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.100 ns + " "Info: + Micro clock to output delay of source is 1.100 ns" { } { { "alt_counter_f10ke.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/alt_counter_f10ke.tdf" 271 2 0 } } } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "8.400 ns + Longest register pin " "Info: + Longest register to pin delay is 8.400 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns lpm_counter:Q1_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[7\] 1 REG LC8_C14 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC8_C14; Fanout = 3; REG Node = 'lpm_counter:Q1_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[7\]'" { } { { "E:/EDA/DDS/INIT_DATA/db/CNT8B_cmp.qrpt" "" { Report "E:/EDA/DDS/INIT_DATA/db/CNT8B_cmp.qrpt" Compiler "CNT8B" "UNKNOWN" "V1" "E:/EDA/DDS/INIT_DATA/db/CNT8B.quartus_db" { Floorplan "E:/EDA/DDS/INIT_DATA/" "" "" { lpm_counter:Q1_rtl_0|alt_counter_f10ke:wysi_counter|q[7] } "NODE_NAME" } "" } } { "alt_counter_f10ke.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/alt_counter_f10ke.tdf" 271 2 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.300 ns) + CELL(5.100 ns) 8.400 ns Q\[7\] 2 PIN PIN_25 0 " "Info: 2: + IC(3.300 ns) + CELL(5.100 ns) = 8.400 ns; Loc. = PIN_25; Fanout = 0; PIN Node = 'Q\[7\]'" { } { { "E:/EDA/DDS/INIT_DATA/db/CNT8B_cmp.qrpt" "" { Report "E:/EDA/DDS/INIT_DATA/db/CNT8B_cmp.qrpt" Compiler "CNT8B" "UNKNOWN" "V1" "E:/EDA/DDS/INIT_DATA/db/CNT8B.quartus_db" { Floorplan "E:/EDA/DDS/INIT_DATA/" "" "8.400 ns" { lpm_counter:Q1_rtl_0|alt_counter_f10ke:wysi_counter|q[7] Q[7] } "NODE_NAME" } "" } } { "CNT8B.vhd" "" { Text "E:/EDA/DDS/INIT_DATA/CNT8B.vhd" 7 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "5.100 ns 60.71 % " "Info: Total cell delay = 5.100 ns ( 60.71 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.300 ns 39.29 % " "Info: Total interconnect delay = 3.300 ns ( 39.29 % )" { } { } 0} } { { "E:/EDA/DDS/INIT_DATA/db/CNT8B_cmp.qrpt" "" { Report "E:/EDA/DDS/INIT_DATA/db/CNT8B_cmp.qrpt" Compiler "CNT8B" "UNKNOWN" "V1" "E:/EDA/DDS/INIT_DATA/db/CNT8B.quartus_db" { Floorplan "E:/EDA/DDS/INIT_DATA/" "" "8.400 ns" { lpm_counter:Q1_rtl_0|alt_counter_f10ke:wysi_counter|q[7] Q[7] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "8.400 ns" { lpm_counter:Q1_rtl_0|alt_counter_f10ke:wysi_counter|q[7] Q[7] } { 0.000ns 3.300ns } { 0.000ns 5.100ns } } } } 0} } { { "E:/EDA/DDS/INIT_DATA/db/CNT8B_cmp.qrpt" "" { Report "E:/EDA/DDS/INIT_DATA/db/CNT8B_cmp.qrpt" Compiler "CNT8B" "UNKNOWN" "V1" "E:/EDA/DDS/INIT_DATA/db/CNT8B.quartus_db" { Floorplan "E:/EDA/DDS/INIT_DATA/" "" "5.300 ns" { CLK lpm_counter:Q1_rtl_0|alt_counter_f10ke:wysi_counter|q[7] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "5.300 ns" { CLK CLK~out lpm_counter:Q1_rtl_0|alt_counter_f10ke:wysi_counter|q[7] } { 0.000ns 0.000ns 2.500ns } { 0.000ns 2.800ns 0.000ns } } } { "E:/EDA/DDS/INIT_DATA/db/CNT8B_cmp.qrpt" "" { Report "E:/EDA/DDS/INIT_DATA/db/CNT8B_cmp.qrpt" Compiler "CNT8B" "UNKNOWN" "V1" "E:/EDA/DDS/INIT_DATA/db/CNT8B.quartus_db" { Floorplan "E:/EDA/DDS/INIT_DATA/" "" "8.400 ns" { lpm_counter:Q1_rtl_0|alt_counter_f10ke:wysi_counter|q[7] Q[7] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "8.400 ns" { lpm_counter:Q1_rtl_0|alt_counter_f10ke:wysi_counter|q[7] Q[7] } { 0.000ns 3.300ns } { 0.000ns 5.100ns } } } } 0}
{ "Info" "ITDB_TH_RESULT" "lpm_counter:Q1_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[0\] EN CLK 1.000 ns register " "Info: th for register \"lpm_counter:Q1_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[0\]\" (data pin = \"EN\", clock pin = \"CLK\") is 1.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK destination 5.300 ns + Longest register " "Info: + Longest clock path from clock \"CLK\" to destination register is 5.300 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.800 ns) 2.800 ns CLK 1 CLK PIN_43 16 " "Info: 1: + IC(0.000 ns) + CELL(2.800 ns) = 2.800 ns; Loc. = PIN_43; Fanout = 16; CLK Node = 'CLK'" { } { { "E:/EDA/DDS/INIT_DATA/db/CNT8B_cmp.qrpt" "" { Report "E:/EDA/DDS/INIT_DATA/db/CNT8B_cmp.qrpt" Compiler "CNT8B" "UNKNOWN" "V1" "E:/EDA/DDS/INIT_DATA/db/CNT8B.quartus_db" { Floorplan "E:/EDA/DDS/INIT_DATA/" "" "" { CLK } "NODE_NAME" } "" } } { "CNT8B.vhd" "" { Text "E:/EDA/DDS/INIT_DATA/CNT8B.vhd" 6 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.500 ns) + CELL(0.000 ns) 5.300 ns lpm_counter:Q1_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[0\] 2 REG LC1_C14 5 " "Info: 2: + IC(2.500 ns) + CELL(0.000 ns) = 5.300 ns; Loc. = LC1_C14; Fanout = 5; REG Node = 'lpm_counter:Q1_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[0\]'" { } { { "E:/EDA/DDS/INIT_DATA/db/CNT8B_cmp.qrpt" "" { Report "E:/EDA/DDS/INIT_DATA/db/CNT8B_cmp.qrpt" Compiler "CNT8B" "UNKNOWN" "V1" "E:/EDA/DDS/INIT_DATA/db/CNT8B.quartus_db" { Floorplan "E:/EDA/DDS/INIT_DATA/" "" "2.500 ns" { CLK lpm_counter:Q1_rtl_0|alt_counter_f10ke:wysi_counter|q[0] } "NODE_NAME" } "" } } { "alt_counter_f10ke.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/alt_counter_f10ke.tdf" 271 2 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.800 ns 52.83 % " "Info: Total cell delay = 2.800 ns ( 52.83 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.500 ns 47.17 % " "Info: Total interconnect delay = 2.500 ns ( 47.17 % )" { } { } 0} } { { "E:/EDA/DDS/INIT_DATA/db/CNT8B_cmp.qrpt" "" { Report "E:/EDA/DDS/INIT_DATA/db/CNT8B_cmp.qrpt" Compiler "CNT8B" "UNKNOWN" "V1" "E:/EDA/DDS/INIT_DATA/db/CNT8B.quartus_db" { Floorplan "E:/EDA/DDS/INIT_DATA/" "" "5.300 ns" { CLK lpm_counter:Q1_rtl_0|alt_counter_f10ke:wysi_counter|q[0] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "5.300 ns" { CLK CLK~out lpm_counter:Q1_rtl_0|alt_counter_f10ke:wysi_counter|q[0] } { 0.000ns 0.000ns 2.500ns } { 0.000ns 2.800ns 0.000ns } } } } 0} { "Info" "ITDB_FULL_TH_DELAY" "1.600 ns + " "Info: + Micro hold delay of destination is 1.600 ns" { } { { "alt_counter_f10ke.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/alt_counter_f10ke.tdf" 271 2 0 } } } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.900 ns - Shortest pin register " "Info: - Shortest pin to register delay is 5.900 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.800 ns) 2.800 ns EN 1 PIN PIN_84 31 " "Info: 1: + IC(0.000 ns) + CELL(2.800 ns) = 2.800 ns; Loc. = PIN_84; Fanout = 31; PIN Node = 'EN'" { } { { "E:/EDA/DDS/INIT_DATA/db/CNT8B_cmp.qrpt" "" { Report "E:/EDA/DDS/INIT_DATA/db/CNT8B_cmp.qrpt" Compiler "CNT8B" "UNKNOWN" "V1" "E:/EDA/DDS/INIT_DATA/db/CNT8B.quartus_db" { Floorplan "E:/EDA/DDS/INIT_DATA/" "" "" { EN } "NODE_NAME" } "" } } { "CNT8B.vhd" "" { Text "E:/EDA/DDS/INIT_DATA/CNT8B.vhd" 6 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.900 ns) + CELL(1.200 ns) 5.900 ns lpm_counter:Q1_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[0\] 2 REG LC1_C14 5 " "Info: 2: + IC(1.900 ns) + CELL(1.200 ns) = 5.900 ns; Loc. = LC1_C14; Fanout = 5; REG Node = 'lpm_counter:Q1_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[0\]'" { } { { "E:/EDA/DDS/INIT_DATA/db/CNT8B_cmp.qrpt" "" { Report "E:/EDA/DDS/INIT_DATA/db/CNT8B_cmp.qrpt" Compiler "CNT8B" "UNKNOWN" "V1" "E:/EDA/DDS/INIT_DATA/db/CNT8B.quartus_db" { Floorplan "E:/EDA/DDS/INIT_DATA/" "" "3.100 ns" { EN lpm_counter:Q1_rtl_0|alt_counter_f10ke:wysi_counter|q[0] } "NODE_NAME" } "" } } { "alt_counter_f10ke.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/alt_counter_f10ke.tdf" 271 2 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.000 ns 67.80 % " "Info: Total cell delay = 4.000 ns ( 67.80 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.900 ns 32.20 % " "Info: Total interconnect delay = 1.900 ns ( 32.20 % )" { } { } 0} } { { "E:/EDA/DDS/INIT_DATA/db/CNT8B_cmp.qrpt" "" { Report "E:/EDA/DDS/INIT_DATA/db/CNT8B_cmp.qrpt" Compiler "CNT8B" "UNKNOWN" "V1" "E:/EDA/DDS/INIT_DATA/db/CNT8B.quartus_db" { Floorplan "E:/EDA/DDS/INIT_DATA/" "" "5.900 ns" { EN lpm_counter:Q1_rtl_0|alt_counter_f10ke:wysi_counter|q[0] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "5.900 ns" { EN EN~out lpm_counter:Q1_rtl_0|alt_counter_f10ke:wysi_counter|q[0] } { 0.000ns 0.000ns 1.900ns } { 0.000ns 2.800ns 1.200ns } } } } 0} } { { "E:/EDA/DDS/INIT_DATA/db/CNT8B_cmp.qrpt" "" { Report "E:/EDA/DDS/INIT_DATA/db/CNT8B_cmp.qrpt" Compiler "CNT8B" "UNKNOWN" "V1" "E:/EDA/DDS/INIT_DATA/db/CNT8B.quartus_db" { Floorplan "E:/EDA/DDS/INIT_DATA/" "" "5.300 ns" { CLK lpm_counter:Q1_rtl_0|alt_counter_f10ke:wysi_counter|q[0] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "5.300 ns" { CLK CLK~out lpm_counter:Q1_rtl_0|alt_counter_f10ke:wysi_counter|q[0] } { 0.000ns 0.000ns 2.500ns } { 0.000ns 2.800ns 0.000ns } } } { "E:/EDA/DDS/INIT_DATA/db/CNT8B_cmp.qrpt" "" { Report "E:/EDA/DDS/INIT_DATA/db/CNT8B_cmp.qrpt" Compiler "CNT8B" "UNKNOWN" "V1" "E:/EDA/DDS/INIT_DATA/db/CNT8B.quartus_db" { Floorplan "E:/EDA/DDS/INIT_DATA/" "" "5.900 ns" { EN lpm_counter:Q1_rtl_0|alt_counter_f10ke:wysi_counter|q[0] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "5.900 ns" { EN EN~out lpm_counter:Q1_rtl_0|alt_counter_f10ke:wysi_counter|q[0] } { 0.000ns 0.000ns 1.900ns } { 0.000ns 2.800ns 1.200ns } } } } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 1 Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Sun Apr 09 21:34:31 2006 " "Info: Processing ended: Sun Apr 09 21:34:31 2006" { } { } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" { } { } 0} } { } 0}
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