top_sinx.tan.qmsg

在EDA开发软件QuartusII上利用VHDL语言实现DDS信号发生器

{ "Info" "ITDB_TSU_RESULT" "INIT_CNT8B:U1\|lpm_counter:CNT8_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[4\] ain\[4\] clkin 5.900 ns register " "Info: tsu for register \"INIT_CNT8B:U1\|lpm_counter:CNT8_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[4\]\" (data pin = \"ain\[4\]\", clock pin = \"clkin\") is 5.900 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "8.700 ns + Longest pin register " "Info: + Longest pin to register delay is 8.700 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.500 ns) 3.500 ns ain\[4\] 1 PIN PIN_79 2 " "Info: 1: + IC(0.000 ns) + CELL(3.500 ns) = 3.500 ns; Loc. = PIN_79; Fanout = 2; PIN Node = 'ain\[4\]'" {  } { { "E:/EDA/DDS/10k844/top/db/top_sinx_cmp.qrpt" "" { Report "E:/EDA/DDS/10k844/top/db/top_sinx_cmp.qrpt" Compiler "top_sinx" "UNKNOWN" "V1" "E:/EDA/DDS/10k844/top/db/top_sinx.quartus_db" { Floorplan "E:/EDA/DDS/10k844/top/" "" "" { ain[4] } "NODE_NAME" } "" } } { "top_sinx.vhd" "" { Text "E:/EDA/DDS/10k844/top/top_sinx.vhd" 6 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.500 ns) + CELL(1.700 ns) 8.700 ns INIT_CNT8B:U1\|lpm_counter:CNT8_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[4\] 2 REG LC3_B17 5 " "Info: 2: + IC(3.500 ns) + CELL(1.700 ns) = 8.700 ns; Loc. = LC3_B17; Fanout = 5; REG Node = 'INIT_CNT8B:U1\|lpm_counter:CNT8_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[4\]'" {  } { { "E:/EDA/DDS/10k844/top/db/top_sinx_cmp.qrpt" "" { Report "E:/EDA/DDS/10k844/top/db/top_sinx_cmp.qrpt" Compiler "top_sinx" "UNKNOWN" "V1" "E:/EDA/DDS/10k844/top/db/top_sinx.quartus_db" { Floorplan "E:/EDA/DDS/10k844/top/" "" "5.200 ns" { ain[4] INIT_CNT8B:U1|lpm_counter:CNT8_rtl_0|alt_counter_f10ke:wysi_counter|q[4] } "NODE_NAME" } "" } } { "alt_counter_f10ke.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/alt_counter_f10ke.tdf" 271 2 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "5.200 ns 59.77 % " "Info: Total cell delay = 5.200 ns ( 59.77 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.500 ns 40.23 % " "Info: Total interconnect delay = 3.500 ns ( 40.23 % )" {  } {  } 0}  } { { "E:/EDA/DDS/10k844/top/db/top_sinx_cmp.qrpt" "" { Report "E:/EDA/DDS/10k844/top/db/top_sinx_cmp.qrpt" Compiler "top_sinx" "UNKNOWN" "V1" "E:/EDA/DDS/10k844/top/db/top_sinx.quartus_db" { Floorplan "E:/EDA/DDS/10k844/top/" "" "8.700 ns" { ain[4] INIT_CNT8B:U1|lpm_counter:CNT8_rtl_0|alt_counter_f10ke:wysi_counter|q[4] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "8.700 ns" { ain[4] ain[4]~out INIT_CNT8B:U1|lpm_counter:CNT8_rtl_0|alt_counter_f10ke:wysi_counter|q[4] } { 0.000ns 0.000ns 3.500ns } { 0.000ns 3.500ns 1.700ns } } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "2.500 ns + " "Info: + Micro setup delay of destination is 2.500 ns" {  } { { "alt_counter_f10ke.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/alt_counter_f10ke.tdf" 271 2 0 } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clkin destination 5.300 ns - Shortest register " "Info: - Shortest clock path from clock \"clkin\" to destination register is 5.300 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.800 ns) 2.800 ns clkin 1 CLK PIN_43 13 " "Info: 1: + IC(0.000 ns) + CELL(2.800 ns) = 2.800 ns; Loc. = PIN_43; Fanout = 13; CLK Node = 'clkin'" {  } { { "E:/EDA/DDS/10k844/top/db/top_sinx_cmp.qrpt" "" { Report "E:/EDA/DDS/10k844/top/db/top_sinx_cmp.qrpt" Compiler "top_sinx" "UNKNOWN" "V1" "E:/EDA/DDS/10k844/top/db/top_sinx.quartus_db" { Floorplan "E:/EDA/DDS/10k844/top/" "" "" { clkin } "NODE_NAME" } "" } } { "top_sinx.vhd" "" { Text "E:/EDA/DDS/10k844/top/top_sinx.vhd" 5 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.500 ns) + CELL(0.000 ns) 5.300 ns INIT_CNT8B:U1\|lpm_counter:CNT8_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[4\] 2 REG LC3_B17 5 " "Info: 2: + IC(2.500 ns) + CELL(0.000 ns) = 5.300 ns; Loc. = LC3_B17; Fanout = 5; REG Node = 'INIT_CNT8B:U1\|lpm_counter:CNT8_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[4\]'" {  } { { "E:/EDA/DDS/10k844/top/db/top_sinx_cmp.qrpt" "" { Report "E:/EDA/DDS/10k844/top/db/top_sinx_cmp.qrpt" Compiler "top_sinx" "UNKNOWN" "V1" "E:/EDA/DDS/10k844/top/db/top_sinx.quartus_db" { Floorplan "E:/EDA/DDS/10k844/top/" "" "2.500 ns" { clkin INIT_CNT8B:U1|lpm_counter:CNT8_rtl_0|alt_counter_f10ke:wysi_counter|q[4] } "NODE_NAME" } "" } } { "alt_counter_f10ke.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/alt_counter_f10ke.tdf" 271 2 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.800 ns 52.83 % " "Info: Total cell delay = 2.800 ns ( 52.83 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.500 ns 47.17 % " "Info: Total interconnect delay = 2.500 ns ( 47.17 % )" {  } {  } 0}  } { { "E:/EDA/DDS/10k844/top/db/top_sinx_cmp.qrpt" "" { Report "E:/EDA/DDS/10k844/top/db/top_sinx_cmp.qrpt" Compiler "top_sinx" "UNKNOWN" "V1" "E:/EDA/DDS/10k844/top/db/top_sinx.quartus_db" { Floorplan "E:/EDA/DDS/10k844/top/" "" "5.300 ns" { clkin INIT_CNT8B:U1|lpm_counter:CNT8_rtl_0|alt_counter_f10ke:wysi_counter|q[4] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "5.300 ns" { clkin clkin~out INIT_CNT8B:U1|lpm_counter:CNT8_rtl_0|alt_counter_f10ke:wysi_counter|q[4] } { 0.000ns 0.000ns 2.500ns } { 0.000ns 2.800ns 0.000ns } } }  } 0}  } { { "E:/EDA/DDS/10k844/top/db/top_sinx_cmp.qrpt" "" { Report "E:/EDA/DDS/10k844/top/db/top_sinx_cmp.qrpt" Compiler "top_sinx" "UNKNOWN" "V1" "E:/EDA/DDS/10k844/top/db/top_sinx.quartus_db" { Floorplan "E:/EDA/DDS/10k844/top/" "" "8.700 ns" { ain[4] INIT_CNT8B:U1|lpm_counter:CNT8_rtl_0|alt_counter_f10ke:wysi_counter|q[4] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "8.700 ns" { ain[4] ain[4]~out INIT_CNT8B:U1|lpm_counter:CNT8_rtl_0|alt_counter_f10ke:wysi_counter|q[4] } { 0.000ns 0.000ns 3.500ns } { 0.000ns 3.500ns 1.700ns } } } { "E:/EDA/DDS/10k844/top/db/top_sinx_cmp.qrpt" "" { Report "E:/EDA/DDS/10k844/top/db/top_sinx_cmp.qrpt" Compiler "top_sinx" "UNKNOWN" "V1" "E:/EDA/DDS/10k844/top/db/top_sinx.quartus_db" { Floorplan "E:/EDA/DDS/10k844/top/" "" "5.300 ns" { clkin INIT_CNT8B:U1|lpm_counter:CNT8_rtl_0|alt_counter_f10ke:wysi_counter|q[4] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "5.300 ns" { clkin clkin~out INIT_CNT8B:U1|lpm_counter:CNT8_rtl_0|alt_counter_f10ke:wysi_counter|q[4] } { 0.000ns 0.000ns 2.500ns } { 0.000ns 2.800ns 0.000ns } } }  } 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clkin da_data\[7\] SINGT2:U2\|data_rom_10k:u1\|lpm_rom:lpm_rom_component\|altrom:srom\|q\[7\]~reg_ra0 36.700 ns memory " "Info: tco from clock \"clkin\" to destination pin \"da_data\[7\]\" through memory \"SINGT2:U2\|data_rom_10k:u1\|lpm_rom:lpm_rom_component\|altrom:srom\|q\[7\]~reg_ra0\" is 36.700 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clkin source 12.000 ns + Longest memory " "Info: + Longest clock path from clock \"clkin\" to source memory is 12.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.800 ns) 2.800 ns clkin 1 CLK PIN_43 13 " "Info: 1: + IC(0.000 ns) + CELL(2.800 ns) = 2.800 ns; Loc. = PIN_43; Fanout = 13; CLK Node = 'clkin'" {  } { { "E:/EDA/DDS/10k844/top/db/top_sinx_cmp.qrpt" "" { Report "E:/EDA/DDS/10k844/top/db/top_sinx_cmp.qrpt" Compiler "top_sinx" "UNKNOWN" "V1" "E:/EDA/DDS/10k844/top/db/top_sinx.quartus_db" { Floorplan "E:/EDA/DDS/10k844/top/" "" "" { clkin } "NODE_NAME" } "" } } { "top_sinx.vhd" "" { Text "E:/EDA/DDS/10k844/top/top_sinx.vhd" 5 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.500 ns) + CELL(1.100 ns) 6.400 ns INIT_CNT8B:U1\|lpm_counter:CNT8_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[2\] 2 REG LC1_B17 74 " "Info: 2: + IC(2.500 ns) + CELL(1.100 ns) = 6.400 ns; Loc. = LC1_B17; Fanout = 74; REG Node = 'INIT_CNT8B:U1\|lpm_counter:CNT8_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[2\]'" {  } { { "E:/EDA/DDS/10k844/top/db/top_sinx_cmp.qrpt" "" { Report "E:/EDA/DDS/10k844/top/db/top_sinx_cmp.qrpt" Compiler "top_sinx" "UNKNOWN" "V1" "E:/EDA/DDS/10k844/top/db/top_sinx.quartus_db" { Floorplan "E:/EDA/DDS/10k844/top/" "" "3.600 ns" { clkin INIT_CNT8B:U1|lpm_counter:CNT8_rtl_0|alt_counter_f10ke:wysi_counter|q[2] } "NODE_NAME" } "" } } { "alt_counter_f10ke.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/alt_counter_f10ke.tdf" 271 2 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(5.600 ns) + CELL(0.000 ns) 12.000 ns SINGT2:U2\|data_rom_10k:u1\|lpm_rom:lpm_rom_component\|altrom:srom\|q\[7\]~reg_ra0 3 MEM EC5_B 1 " "Info: 3: + IC(5.600 ns) + CELL(0.000 ns) = 12.000 ns; Loc. = EC5_B; Fanout = 1; MEM Node = 'SINGT2:U2\|data_rom_10k:u1\|lpm_rom:lpm_rom_component\|altrom:srom\|q\[7\]~reg_ra0'" {  } { { "E:/EDA/DDS/10k844/top/db/top_sinx_cmp.qrpt" "" { Report "E:/EDA/DDS/10k844/top/db/top_sinx_cmp.qrpt" Compiler "top_sinx" "UNKNOWN" "V1" "E:/EDA/DDS/10k844/top/db/top_sinx.quartus_db" { Floorplan "E:/EDA/DDS/10k844/top/" "" "5.600 ns" { INIT_CNT8B:U1|lpm_counter:CNT8_rtl_0|alt_counter_f10ke:wysi_counter|q[2] SINGT2:U2|data_rom_10k:u1|lpm_rom:lpm_rom_component|altrom:srom|q[7]~reg_ra0 } "NODE_NAME" } "" } } { "altrom.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/altrom.tdf" 80 2 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.900 ns 32.50 % " "Info: Total cell delay = 3.900 ns ( 32.50 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "8.100 ns 67.50 % " "Info: Total interconnect delay = 8.100 ns ( 67.50 % )" {  } {  } 0}  } { { "E:/EDA/DDS/10k844/top/db/top_sinx_cmp.qrpt" "" { Report "E:/EDA/DDS/10k844/top/db/top_sinx_cmp.qrpt" Compiler "top_sinx" "UNKNOWN" "V1" "E:/EDA/DDS/10k844/top/db/top_sinx.quartus_db" { Floorplan "E:/EDA/DDS/10k844/top/" "" "12.000 ns" { clkin INIT_CNT8B:U1|lpm_counter:CNT8_rtl_0|alt_counter_f10ke:wysi_counter|q[2] SINGT2:U2|data_rom_10k:u1|lpm_rom:lpm_rom_component|altrom:srom|q[7]~reg_ra0 } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "12.000 ns" { clkin clkin~out INIT_CNT8B:U1|lpm_counter:CNT8_rtl_0|alt_counter_f10ke:wysi_counter|q[2] SINGT2:U2|data_rom_10k:u1|lpm_rom:lpm_rom_component|altrom:srom|q[7]~reg_ra0 } { 0.000ns 0.000ns 2.500ns 5.600ns } { 0.000ns 2.800ns 1.100ns 0.000ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.600 ns + " "Info: + Micro clock to output delay of source is 0.600 ns" {  } { { "altrom.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/altrom.tdf" 80 2 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "24.100 ns + Longest memory pin " "Info: + Longest memory to pin delay is 24.100 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns SINGT2:U2\|data_rom_10k:u1\|lpm_rom:lpm_rom_component\|altrom:srom\|q\[7\]~reg_ra0 1 MEM EC5_B 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = EC5_B; Fanout = 1; MEM Node = 'SINGT2:U2\|data_rom_10k:u1\|lpm_rom:lpm_rom_component\|altrom:srom\|q\[7\]~reg_ra0'" {  } { { "E:/EDA/DDS/10k844/top/db/top_sinx_cmp.qrpt" "" { Report "E:/EDA/DDS/10k844/top/db/top_sinx_cmp.qrpt" Compiler "top_sinx" "UNKNOWN" "V1" "E:/EDA/DDS/10k844/top/db/top_sinx.quartus_db" { Floorplan "E:/EDA/DDS/10k844/top/" "" "" { SINGT2:U2|data_rom_10k:u1|lpm_rom:lpm_rom_component|altrom:srom|q[7]~reg_ra0 } "NODE_NAME" } "" } } { "altrom.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/altrom.tdf" 80 2 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(10.700 ns) 10.700 ns SINGT2:U2\|data_rom_10k:u1\|lpm_rom:lpm_rom_component\|altrom:srom\|q\[7\]~mem_cell_ra0 2 MEM EC5_B 1 " "Info: 2: + IC(0.000 ns) + CELL(10.700 ns) = 10.700 ns; Loc. = EC5_B; Fanout = 1; MEM Node = 'SINGT2:U2\|data_rom_10k:u1\|lpm_rom:lpm_rom_component\|altrom:srom\|q\[7\]~mem_cell_ra0'" {  } { { "E:/EDA/DDS/10k844/top/db/top_sinx_cmp.qrpt" "" { Report "E:/EDA/DDS/10k844/top/db/top_sinx_cmp.qrpt" Compiler "top_sinx" "UNKNOWN" "V1" "E:/EDA/DDS/10k844/top/db/top_sinx.quartus_db" { Floorplan "E:/EDA/DDS/10k844/top/" "" "10.700 ns" { SINGT2:U2|data_rom_10k:u1|lpm_rom:lpm_rom_component|altrom:srom|q[7]~reg_ra0 SINGT2:U2|data_rom_10k:u1|lpm_rom:lpm_rom_component|altrom:srom|q[7]~mem_cell_ra0 } "NODE_NAME" } "" } } { "altrom.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/altrom.tdf" 80 2 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.500 ns) 13.200 ns SINGT2:U2\|data_rom_10k:u1\|lpm_rom:lpm_rom_component\|altrom:srom\|q\[7\] 3 MEM EC5_B 1 " "Info: 3: + IC(0.000 ns) + CELL(2.500 ns) = 13.200 ns; Loc. = EC5_B; Fanout = 1; MEM Node = 'SINGT2:U2\|data_rom_10k:u1\|lpm_rom:lpm_rom_component\|altrom:srom\|q\[7\]'" {  } { { "E:/EDA/DDS/10k844/top/db/top_sinx_cmp.qrpt" "" { Report "E:/EDA/DDS/10k844/top/db/top_sinx_cmp.qrpt" Compiler "top_sinx" "UNKNOWN" "V1" "E:/EDA/DDS/10k844/top/db/top_sinx.quartus_db" { Floorplan "E:/EDA/DDS/10k844/top/" "" "2.500 ns" { SINGT2:U2|data_rom_10k:u1|lpm_rom:lpm_rom_component|altrom:srom|q[7]~mem_cell_ra0 SINGT2:U2|data_rom_10k:u1|lpm_rom:lpm_rom_component|altrom:srom|q[7] } "NODE_NAME" } "" } } { "altrom.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/altrom.tdf" 80 2 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(5.800 ns) + CELL(5.100 ns) 24.100 ns da_data\[7\] 4 PIN PIN_24 0 " "Info: 4: + IC(5.800 ns) + CELL(5.100 ns) = 24.100 ns; Loc. = PIN_24; Fanout = 0; PIN Node = 'da_data\[7\]'" {  } { { "E:/EDA/DDS/10k844/top/db/top_sinx_cmp.qrpt" "" { Report "E:/EDA/DDS/10k844/top/db/top_sinx_cmp.qrpt" Compiler "top_sinx" "UNKNOWN" "V1" "E:/EDA/DDS/10k844/top/db/top_sinx.quartus_db" { Floorplan "E:/EDA/DDS/10k844/top/" "" "10.900 ns" { SINGT2:U2|data_rom_10k:u1|lpm_rom:lpm_rom_component|altrom:srom|q[7] da_data[7] } "NODE_NAME" } "" } } { "top_sinx.vhd" "" { Text "E:/EDA/DDS/10k844/top/top_sinx.vhd" 7 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "18.300 ns 75.93 % " "Info: Total cell delay = 18.300 ns ( 75.93 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.800 ns 24.07 % " "Info: Total interconnect delay = 5.800 ns ( 24.07 % )" {  } {  } 0}  } { { "E:/EDA/DDS/10k844/top/db/top_sinx_cmp.qrpt" "" { Report "E:/EDA/DDS/10k844/top/db/top_sinx_cmp.qrpt" Compiler "top_sinx" "UNKNOWN" "V1" "E:/EDA/DDS/10k844/top/db/top_sinx.quartus_db" { Floorplan "E:/EDA/DDS/10k844/top/" "" "24.100 ns" { SINGT2:U2|data_rom_10k:u1|lpm_rom:lpm_rom_component|altrom:srom|q[7]~reg_ra0 SINGT2:U2|data_rom_10k:u1|lpm_rom:lpm_rom_component|altrom:srom|q[7]~mem_cell_ra0 SINGT2:U2|data_rom_10k:u1|lpm_rom:lpm_rom_component|altrom:srom|q[7] da_data[7] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "24.100 ns" { SINGT2:U2|data_rom_10k:u1|lpm_rom:lpm_rom_component|altrom:srom|q[7]~reg_ra0 SINGT2:U2|data_rom_10k:u1|lpm_rom:lpm_rom_component|altrom:srom|q[7]~mem_cell_ra0 SINGT2:U2|data_rom_10k:u1|lpm_rom:lpm_rom_component|altrom:srom|q[7] da_data[7] } { 0.000ns 0.000ns 0.000ns 5.800ns } { 0.000ns 10.700ns 2.500ns 5.100ns } } }  } 0}  } { { "E:/EDA/DDS/10k844/top/db/top_sinx_cmp.qrpt" "" { Report "E:/EDA/DDS/10k844/top/db/top_sinx_cmp.qrpt" Compiler "top_sinx" "UNKNOWN" "V1" "E:/EDA/DDS/10k844/top/db/top_sinx.quartus_db" { Floorplan "E:/EDA/DDS/10k844/top/" "" "12.000 ns" { clkin INIT_CNT8B:U1|lpm_counter:CNT8_rtl_0|alt_counter_f10ke:wysi_counter|q[2] SINGT2:U2|data_rom_10k:u1|lpm_rom:lpm_rom_component|altrom:srom|q[7]~reg_ra0 } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "12.000 ns" { clkin clkin~out INIT_CNT8B:U1|lpm_counter:CNT8_rtl_0|alt_counter_f10ke:wysi_counter|q[2] SINGT2:U2|data_rom_10k:u1|lpm_rom:lpm_rom_component|altrom:srom|q[7]~reg_ra0 } { 0.000ns 0.000ns 2.500ns 5.600ns } { 0.000ns 2.800ns 1.100ns 0.000ns } } } { "E:/EDA/DDS/10k844/top/db/top_sinx_cmp.qrpt" "" { Report "E:/EDA/DDS/10k844/top/db/top_sinx_cmp.qrpt" Compiler "top_sinx" "UNKNOWN" "V1" "E:/EDA/DDS/10k844/top/db/top_sinx.quartus_db" { Floorplan "E:/EDA/DDS/10k844/top/" "" "24.100 ns" { SINGT2:U2|data_rom_10k:u1|lpm_rom:lpm_rom_component|altrom:srom|q[7]~reg_ra0 SINGT2:U2|data_rom_10k:u1|lpm_rom:lpm_rom_component|altrom:srom|q[7]~mem_cell_ra0 SINGT2:U2|data_rom_10k:u1|lpm_rom:lpm_rom_component|altrom:srom|q[7] da_data[7] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "24.100 ns" { SINGT2:U2|data_rom_10k:u1|lpm_rom:lpm_rom_component|altrom:srom|q[7]~reg_ra0 SINGT2:U2|data_rom_10k:u1|lpm_rom:lpm_rom_component|altrom:srom|q[7]~mem_cell_ra0 SINGT2:U2|data_rom_10k:u1|lpm_rom:lpm_rom_component|altrom:srom|q[7] da_data[7] } { 0.000ns 0.000ns 0.000ns 5.800ns } { 0.000ns 10.700ns 2.500ns 5.100ns } } }  } 0}
{ "Info" "ITDB_TH_RESULT" "INIT_CNT8B:U1\|lpm_counter:CNT8_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[7\] ain\[7\] clkin 0.800 ns register " "Info: th for register \"INIT_CNT8B:U1\|lpm_counter:CNT8_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[7\]\" (data pin = \"ain\[7\]\", clock pin = \"clkin\") is 0.800 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clkin destination 5.300 ns + Longest register " "Info: + Longest clock path from clock \"clkin\" to destination register is 5.300 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.800 ns) 2.800 ns clkin 1 CLK PIN_43 13 " "Info: 1: + IC(0.000 ns) + CELL(2.800 ns) = 2.800 ns; Loc. = PIN_43; Fanout = 13; CLK Node = 'clkin'" {  } { { "E:/EDA/DDS/10k844/top/db/top_sinx_cmp.qrpt" "" { Report "E:/EDA/DDS/10k844/top/db/top_sinx_cmp.qrpt" Compiler "top_sinx" "UNKNOWN" "V1" "E:/EDA/DDS/10k844/top/db/top_sinx.quartus_db" { Floorplan "E:/EDA/DDS/10k844/top/" "" "" { clkin } "NODE_NAME" } "" } } { "top_sinx.vhd" "" { Text "E:/EDA/DDS/10k844/top/top_sinx.vhd" 5 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.500 ns) + CELL(0.000 ns) 5.300 ns INIT_CNT8B:U1\|lpm_counter:CNT8_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[7\] 2 REG LC6_B17 2 " "Info: 2: + IC(2.500 ns) + CELL(0.000 ns) = 5.300 ns; Loc. = LC6_B17; Fanout = 2; REG Node = 'INIT_CNT8B:U1\|lpm_counter:CNT8_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[7\]'" {  } { { "E:/EDA/DDS/10k844/top/db/top_sinx_cmp.qrpt" "" { Report "E:/EDA/DDS/10k844/top/db/top_sinx_cmp.qrpt" Compiler "top_sinx" "UNKNOWN" "V1" "E:/EDA/DDS/10k844/top/db/top_sinx.quartus_db" { Floorplan "E:/EDA/DDS/10k844/top/" "" "2.500 ns" { clkin INIT_CNT8B:U1|lpm_counter:CNT8_rtl_0|alt_counter_f10ke:wysi_counter|q[7] } "NODE_NAME" } "" } } { "alt_counter_f10ke.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/alt_counter_f10ke.tdf" 271 2 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.800 ns 52.83 % " "Info: Total cell delay = 2.800 ns ( 52.83 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.500 ns 47.17 % " "Info: Total interconnect delay = 2.500 ns ( 47.17 % )" {  } {  } 0}  } { { "E:/EDA/DDS/10k844/top/db/top_sinx_cmp.qrpt" "" { Report "E:/EDA/DDS/10k844/top/db/top_sinx_cmp.qrpt" Compiler "top_sinx" "UNKNOWN" "V1" "E:/EDA/DDS/10k844/top/db/top_sinx.quartus_db" { Floorplan "E:/EDA/DDS/10k844/top/" "" "5.300 ns" { clkin INIT_CNT8B:U1|lpm_counter:CNT8_rtl_0|alt_counter_f10ke:wysi_counter|q[7] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "5.300 ns" { clkin clkin~out INIT_CNT8B:U1|lpm_counter:CNT8_rtl_0|alt_counter_f10ke:wysi_counter|q[7] } { 0.000ns 0.000ns 2.500ns } { 0.000ns 2.800ns 0.000ns } } }  } 0} { "Info" "ITDB_FULL_TH_DELAY" "1.600 ns + " "Info: + Micro hold delay of destination is 1.600 ns" {  } { { "alt_counter_f10ke.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/alt_counter_f10ke.tdf" 271 2 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.100 ns - Shortest pin register " "Info: - Shortest pin to register delay is 6.100 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.800 ns) 2.800 ns ain\[7\] 1 PIN PIN_1 1 " "Info: 1: + IC(0.000 ns) + CELL(2.800 ns) = 2.800 ns; Loc. = PIN_1; Fanout = 1; PIN Node = 'ain\[7\]'" {  } { { "E:/EDA/DDS/10k844/top/db/top_sinx_cmp.qrpt" "" { Report "E:/EDA/DDS/10k844/top/db/top_sinx_cmp.qrpt" Compiler "top_sinx" "UNKNOWN" "V1" "E:/EDA/DDS/10k844/top/db/top_sinx.quartus_db" { Floorplan "E:/EDA/DDS/10k844/top/" "" "" { ain[7] } "NODE_NAME" } "" } } { "top_sinx.vhd" "" { Text "E:/EDA/DDS/10k844/top/top_sinx.vhd" 6 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.600 ns) + CELL(1.700 ns) 6.100 ns INIT_CNT8B:U1\|lpm_counter:CNT8_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[7\] 2 REG LC6_B17 2 " "Info: 2: + IC(1.600 ns) + CELL(1.700 ns) = 6.100 ns; Loc. = LC6_B17; Fanout = 2; REG Node = 'INIT_CNT8B:U1\|lpm_counter:CNT8_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[7\]'" {  } { { "E:/EDA/DDS/10k844/top/db/top_sinx_cmp.qrpt" "" { Report "E:/EDA/DDS/10k844/top/db/top_sinx_cmp.qrpt" Compiler "top_sinx" "UNKNOWN" "V1" "E:/EDA/DDS/10k844/top/db/top_sinx.quartus_db" { Floorplan "E:/EDA/DDS/10k844/top/" "" "3.300 ns" { ain[7] INIT_CNT8B:U1|lpm_counter:CNT8_rtl_0|alt_counter_f10ke:wysi_counter|q[7] } "NODE_NAME" } "" } } { "alt_counter_f10ke.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/alt_counter_f10ke.tdf" 271 2 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.500 ns 73.77 % " "Info: Total cell delay = 4.500 ns ( 73.77 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.600 ns 26.23 % " "Info: Total interconnect delay = 1.600 ns ( 26.23 % )" {  } {  } 0}  } { { "E:/EDA/DDS/10k844/top/db/top_sinx_cmp.qrpt" "" { Report "E:/EDA/DDS/10k844/top/db/top_sinx_cmp.qrpt" Compiler "top_sinx" "UNKNOWN" "V1" "E:/EDA/DDS/10k844/top/db/top_sinx.quartus_db" { Floorplan "E:/EDA/DDS/10k844/top/" "" "6.100 ns" { ain[7] INIT_CNT8B:U1|lpm_counter:CNT8_rtl_0|alt_counter_f10ke:wysi_counter|q[7] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "6.100 ns" { ain[7] ain[7]~out INIT_CNT8B:U1|lpm_counter:CNT8_rtl_0|alt_counter_f10ke:wysi_counter|q[7] } { 0.000ns 0.000ns 1.600ns } { 0.000ns 2.800ns 1.700ns } } }  } 0}  } { { "E:/EDA/DDS/10k844/top/db/top_sinx_cmp.qrpt" "" { Report "E:/EDA/DDS/10k844/top/db/top_sinx_cmp.qrpt" Compiler "top_sinx" "UNKNOWN" "V1" "E:/EDA/DDS/10k844/top/db/top_sinx.quartus_db" { Floorplan "E:/EDA/DDS/10k844/top/" "" "5.300 ns" { clkin INIT_CNT8B:U1|lpm_counter:CNT8_rtl_0|alt_counter_f10ke:wysi_counter|q[7] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "5.300 ns" { clkin clkin~out INIT_CNT8B:U1|lpm_counter:CNT8_rtl_0|alt_counter_f10ke:wysi_counter|q[7] } { 0.000ns 0.000ns 2.500ns } { 0.000ns 2.800ns 0.000ns } } } { "E:/EDA/DDS/10k844/top/db/top_sinx_cmp.qrpt" "" { Report "E:/EDA/DDS/10k844/top/db/top_sinx_cmp.qrpt" Compiler "top_sinx" "UNKNOWN" "V1" "E:/EDA/DDS/10k844/top/db/top_sinx.quartus_db" { Floorplan "E:/EDA/DDS/10k844/top/" "" "6.100 ns" { ain[7] INIT_CNT8B:U1|lpm_counter:CNT8_rtl_0|alt_counter_f10ke:wysi_counter|q[7] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "6.100 ns" { ain[7] ain[7]~out INIT_CNT8B:U1|lpm_counter:CNT8_rtl_0|alt_counter_f10ke:wysi_counter|q[7] } { 0.000ns 0.000ns 1.600ns } { 0.000ns 2.800ns 1.700ns } } }  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 2 s Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Fri Apr 14 04:09:16 2006 " "Info: Processing ended: Fri Apr 14 04:09:16 2006" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" {  } {  } 0}  } {  } 0}