cotal.vhd

来自「在EDA软件上编程」· VHDL 代码 · 共 16 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
ENTITY cotal IS
  PORT(lock : IN STD_LOGIC;
       d : in STD_LOGIC_VECTOR(31 DOWNTO 0);
       q : OUT STD_LOGIC_VECTOR(31 DOWNTO 0) );
END cotal;
ARCHITECTURE BEHAV OF cotal IS
BEGIN
  PROCESS(lock,d)
 begin
  IF lock'EVENT AND lock='1' THEN q<=d;
  end if;
  END PROCESS;
END BEHAV;