shuma.vhd

我们学校做VHDL实验的源码

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED;
ENTITY SHUMA IS
  PORT(A:IN STD_LOGIC_VECTOR(3 DOWNTO 0);
       B:OUT STD_LOGIC_VECTOR(6 DOWNTO 0);
       W:OUT STD_LOGIC
      );
END ENTITY;
ARCHITECTURE BHV OF SHUMA IS
  BEGIN
 PROCESS(A)
  BEGIN
    CASE A IS
   WHEN "0000" =>B<="0111111";
   WHEN "0001" =>B<="0000110";
   WHEN "0010" =>B<="1011011";
   WHEN "0011" =>B<="1001111";
   WHEN "0100" =>B<="1100110";
   WHEN "0101" =>B<="1101101";
   WHEN "0110" =>B<="1111101";
   WHEN "0111" =>B<="0000111";
   WHEN "1000" =>B<="1111111";
   WHEN "1001" =>B<="1101111";
   WHEN "1010" =>B<="1110111";
   WHEN "1011" =>B<="1111100";
   WHEN "1100" =>B<="0111001";
   WHEN "1101" =>B<="1011110";
   WHEN "1110" =>B<="1111001";
   WHEN OTHERS =>B<="1110001";
     END CASE;
   END PROCESS;
   W<='1';

   
  END BHV;