counter.rpt

我们学校做VHDL实验的源码

  80    126    H         FF      t        1      0   1    4    4    5    1  JISHU0 (:17)
  79    125    H         FF      t        1      0   1    4    3    5    1  JISHU1 (:16)
  77    123    H         FF      t        1      0   1    4    5    4    1  JISHU2 (:15)
  76    120    H         FF      t        2      0   1    4    4    5    0  JISHU3 (:14)


Code:

s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell


Device-Specific Information:                   c:\the road\counter\counter.rpt
counter

** BURIED LOGIC **

                                         Shareable
                                         Expanders     Fan-In    Fan-Out
 Pin     LC  LAB  Primitive    Code   Total Shared n/a INP  FBK  OUT  FBK  Name
   -    113    H       SOFT      t        0      0   0    0    3    1    0  |LPM_ADD_SUB:92|addcore:adder|addcore:adder0|result_node2


Code:

s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell


Device-Specific Information:                   c:\the road\counter\counter.rpt
counter

** LOGIC CELL INTERCONNECTIONS **

Logic Array Block 'H':

                     Logic cells placed in LAB 'H'
        +----------- LC128 C
        | +--------- LC126 JISHU0
        | | +------- LC125 JISHU1
        | | | +----- LC123 JISHU2
        | | | | +--- LC120 JISHU3
        | | | | | +- LC113 |LPM_ADD_SUB:92|addcore:adder|addcore:adder0|result_node2
        | | | | | | 
        | | | | | |   Other LABs fed by signals
        | | | | | |   that feed LAB 'H'
LC      | | | | | | | A B C D E F G H |     Logic cells that feed LAB 'H':
LC128-> * - - - - - | - - - - - - - * | <-- C
LC126-> * * * * * * | - - - - - - - * | <-- JISHU0
LC125-> * * * * * * | - - - - - - - * | <-- JISHU1
LC123-> * * - * * * | - - - - - - - * | <-- JISHU2
LC120-> * * * * * - | - - - - - - - * | <-- JISHU3
LC113-> - - - * - - | - - - - - - - * | <-- |LPM_ADD_SUB:92|addcore:adder|addcore:adder0|result_node2

Pin
2    -> * * * * * - | - - - - - - - * | <-- CLK
31   -> * * * * * - | - - - - - - - * | <-- EN
34   -> - * - - - - | - - - - - - - * | <-- LOAD0
35   -> - - * - - - | - - - - - - - * | <-- LOAD1
36   -> - - - * - - | - - - - - - - * | <-- LOAD2
37   -> - - - - * - | - - - - - - - * | <-- LOAD3
33   -> * * * * * - | - - - - - - - * | <-- S


* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).


Device-Specific Information:                   c:\the road\counter\counter.rpt
counter

** EQUATIONS **

CLK      : INPUT;
EN       : INPUT;
LOAD0    : INPUT;
LOAD1    : INPUT;
LOAD2    : INPUT;
LOAD3    : INPUT;
S        : INPUT;

-- Node name is 'C' = ':8' 
-- Equation name is 'C', type is output 
 C       = DFFE( _EQ001 $  VCC,  CLK,  VCC,  VCC,  VCC);
  _EQ001 =  EN & !JISHU0 & !JISHU1 & !JISHU2 & !S
         #  EN & !JISHU3 & !S
         # !C &  S
         # !C & !EN;

-- Node name is 'JISHU0' = 'TEMP0' 
-- Equation name is 'JISHU0', location is LC126, type is output.
 JISHU0  = DFFE( _EQ002 $  GND,  CLK,  VCC,  VCC,  VCC);
  _EQ002 =  EN & !JISHU0 & !JISHU1 & !JISHU2 &  JISHU3 & !S
         #  EN & !JISHU0 & !JISHU3 & !S
         #  EN &  LOAD0 &  S
         # !EN &  JISHU0;

-- Node name is 'JISHU1' = 'TEMP1' 
-- Equation name is 'JISHU1', location is LC125, type is output.
 JISHU1  = DFFE( _EQ003 $  GND,  CLK,  VCC,  VCC,  VCC);
  _EQ003 =  EN & !JISHU0 &  JISHU1 & !JISHU3 & !S
         #  EN &  JISHU0 & !JISHU1 & !JISHU3 & !S
         #  EN &  LOAD1 &  S
         # !EN &  JISHU1;

-- Node name is 'JISHU2' = 'TEMP2' 
-- Equation name is 'JISHU2', location is LC123, type is output.
 JISHU2  = DFFE( _EQ004 $  GND,  CLK,  VCC,  VCC,  VCC);
  _EQ004 =  EN & !JISHU0 & !JISHU1 & !JISHU2 &  JISHU3 &  _LC113 & !S
         #  EN & !JISHU3 &  _LC113 & !S
         #  EN &  LOAD2 &  S
         # !EN &  JISHU2;

-- Node name is 'JISHU3' = 'TEMP3' 
-- Equation name is 'JISHU3', location is LC120, type is output.
 JISHU3  = DFFE( _EQ005 $  GND,  CLK,  VCC,  VCC,  VCC);
  _EQ005 =  EN & !JISHU0 & !JISHU1 & !JISHU2 &  JISHU3 & !S &  _X001
         #  EN &  JISHU0 &  JISHU1 &  JISHU2 & !JISHU3 & !S
         #  EN &  LOAD3 &  S
         # !EN &  JISHU3;
  _X001  = EXP( JISHU0 &  JISHU1 &  JISHU2);

-- Node name is '|LPM_ADD_SUB:92|addcore:adder|addcore:adder0|result_node2' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC113', type is buried 
_LC113   = LCELL( JISHU2 $  _EQ006);
  _EQ006 =  JISHU0 &  JISHU1;



--     Shareable expanders that are duplicated in multiple LABs:
--     (none)




Project Information                            c:\the road\counter\counter.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Standard

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'MAX7000S' family

      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      PARALLEL_EXPANDERS                  = off
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SOFT_BUFFER_INSERTION               = on
      SUBFACTOR_EXTRACTION                = on
      TURBO_BIT                           = on
      XOR_SYNTHESIS                       = on
      IGNORE_SOFT_BUFFERS                 = off
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = off
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      One-Hot State Machine Encoding      = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = off

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:00
   Database Builder                       00:00:00
   Logic Synthesizer                      00:00:00
   Partitioner                            00:00:01
   Fitter                                 00:00:00
   Timing SNF Extractor                   00:00:01
   Assembler                              00:00:02
   --------------------------             --------
   Total Time                             00:00:04


Memory Allocated
-----------------

Peak memory allocated during compilation  = 4,528K