show.rpt

我们学校做VHDL实验的源码

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** LOGIC CELL INTERCONNECTIONS **

Logic Array Block 'A':

                       Logic cells placed in LAB 'A'
        +------------- LC16 MID0
        | +----------- LC14 MID1
        | | +--------- LC13 MID2
        | | | +------- LC11 MID3
        | | | | +----- LC8 MID4
        | | | | | +--- LC6 MID5
        | | | | | | +- LC5 MID6
        | | | | | | | 
        | | | | | | |   Other LABs fed by signals
        | | | | | | |   that feed LAB 'A'
LC      | | | | | | | | A B C D E F G H |     Logic cells that feed LAB 'A':

Pin
2    -> - - - - - - - | - - - - - - - - | <-- CLK_IN
LC115-> * * * * * * * | * - - - - - - * | <-- |COUNTER:U1|TEMP3
LC114-> * * * * * * * | * - - - - - - * | <-- |COUNTER:U1|TEMP2
LC113-> * * * * * * * | * - - - - - - * | <-- |COUNTER:U1|TEMP1
LC116-> * * * * * * * | * - - - - - - * | <-- |COUNTER:U1|TEMP0


* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).


Device-Specific Information:                      c:\the road\counter\show.rpt
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** LOGIC CELL INTERCONNECTIONS **

Logic Array Block 'B':

           Logic cells placed in LAB 'B'
        +- LC29 L
        | 
        |   Other LABs fed by signals
        |   that feed LAB 'B'
LC      | | A B C D E F G H |     Logic cells that feed LAB 'B':

Pin
2    -> - | - - - - - - - - | <-- CLK_IN


* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).


Device-Specific Information:                      c:\the road\counter\show.rpt
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** LOGIC CELL INTERCONNECTIONS **

Logic Array Block 'H':

                     Logic cells placed in LAB 'H'
        +----------- LC117 |COUNTER:U1|LPM_ADD_SUB:92|addcore:adder|addcore:adder0|result_node2
        | +--------- LC115 |COUNTER:U1|TEMP3
        | | +------- LC114 |COUNTER:U1|TEMP2
        | | | +----- LC113 |COUNTER:U1|TEMP1
        | | | | +--- LC116 |COUNTER:U1|TEMP0
        | | | | | +- LC128 C_OUT
        | | | | | | 
        | | | | | |   Other LABs fed by signals
        | | | | | |   that feed LAB 'H'
LC      | | | | | | | A B C D E F G H |     Logic cells that feed LAB 'H':
LC117-> - - * - - - | - - - - - - - * | <-- |COUNTER:U1|LPM_ADD_SUB:92|addcore:adder|addcore:adder0|result_node2
LC115-> - * * * * * | * - - - - - - * | <-- |COUNTER:U1|TEMP3
LC114-> * * * - * * | * - - - - - - * | <-- |COUNTER:U1|TEMP2
LC113-> * * * * * * | * - - - - - - * | <-- |COUNTER:U1|TEMP1
LC116-> * * * * * * | * - - - - - - * | <-- |COUNTER:U1|TEMP0
LC128-> - - - - - * | - - - - - - - * | <-- C_OUT

Pin
2    -> - - - - - - | - - - - - - - - | <-- CLK_IN
33   -> - * * * * * | - - - - - - - * | <-- EN_IN
34   -> - - - - * - | - - - - - - - * | <-- LOAD_IN0
35   -> - - - * - - | - - - - - - - * | <-- LOAD_IN1
36   -> - - * - - - | - - - - - - - * | <-- LOAD_IN2
37   -> - * - - - - | - - - - - - - * | <-- LOAD_IN3
31   -> - * * * * * | - - - - - - - * | <-- S_IN


* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).


Device-Specific Information:                      c:\the road\counter\show.rpt
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** EQUATIONS **

CLK_IN   : INPUT;
EN_IN    : INPUT;
LOAD_IN0 : INPUT;
LOAD_IN1 : INPUT;
LOAD_IN2 : INPUT;
LOAD_IN3 : INPUT;
S_IN     : INPUT;

-- Node name is 'C_OUT' = '|COUNTER:U1|:8' 
-- Equation name is 'C_OUT', type is output 
 C_OUT   = DFFE( _EQ001 $  EN_IN, GLOBAL( CLK_IN),  VCC,  VCC,  VCC);
  _EQ001 =  EN_IN & !_LC113 & !_LC114 & !_LC116 & !S_IN
         # !C_OUT &  EN_IN &  S_IN
         #  EN_IN & !_LC115 & !S_IN
         #  C_OUT & !EN_IN;

-- Node name is 'L' 
-- Equation name is 'L', location is LC029, type is output.
 L       = LCELL( GND $  GND);

-- Node name is 'MID0' 
-- Equation name is 'MID0', location is LC016, type is output.
 MID0    = LCELL( _EQ002 $  VCC);
  _EQ002 = !_LC113 &  _LC114 &  _LC115 &  _LC116
         #  _LC113 & !_LC114 &  _LC115 &  _LC116
         # !_LC113 & !_LC114 & !_LC115 &  _LC116
         # !_LC113 &  _LC114 & !_LC115 & !_LC116;

-- Node name is 'MID1' 
-- Equation name is 'MID1', location is LC014, type is output.
 MID1    = LCELL( _EQ003 $  VCC);
  _EQ003 = !_LC113 &  _LC114 & !_LC115 &  _LC116
         #  _LC113 &  _LC115 &  _LC116
         #  _LC113 &  _LC114 & !_LC116
         #  _LC114 &  _LC115 & !_LC116;

-- Node name is 'MID2' 
-- Equation name is 'MID2', location is LC013, type is output.
 MID2    = LCELL( _EQ004 $  VCC);
  _EQ004 =  _LC113 & !_LC114 & !_LC115 & !_LC116
         #  _LC113 &  _LC114 &  _LC115
         #  _LC114 &  _LC115 & !_LC116;

-- Node name is 'MID3' 
-- Equation name is 'MID3', location is LC011, type is output.
 MID3    = LCELL( _EQ005 $  VCC);
  _EQ005 =  _LC113 & !_LC114 &  _LC115 & !_LC116
         # !_LC113 & !_LC114 & !_LC115 &  _LC116
         # !_LC113 &  _LC114 & !_LC115 & !_LC116
         #  _LC113 &  _LC114 &  _LC116;

-- Node name is 'MID4' 
-- Equation name is 'MID4', location is LC008, type is output.
 MID4    = LCELL( _EQ006 $  VCC);
  _EQ006 = !_LC113 &  _LC114 & !_LC115
         # !_LC113 & !_LC114 &  _LC116
         # !_LC115 &  _LC116;

-- Node name is 'MID5' 
-- Equation name is 'MID5', location is LC006, type is output.
 MID5    = LCELL( _EQ007 $  VCC);
  _EQ007 = !_LC113 &  _LC114 &  _LC115 &  _LC116
         # !_LC113 & !_LC114 & !_LC115 &  _LC116
         #  _LC113 & !_LC114 & !_LC115 & !_LC116
         #  _LC113 & !_LC115 &  _LC116;

-- Node name is 'MID6' 
-- Equation name is 'MID6', location is LC005, type is output.
 MID6    = LCELL( _EQ008 $  VCC);
  _EQ008 =  _LC113 &  _LC114 & !_LC115 &  _LC116
         # !_LC113 &  _LC114 &  _LC115 & !_LC116
         # !_LC113 & !_LC114 & !_LC115;

-- Node name is '|COUNTER:U1|LPM_ADD_SUB:92|addcore:adder|addcore:adder0|result_node2' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC117', type is buried 
_LC117   = LCELL( _LC114 $  _EQ009);
  _EQ009 =  _LC113 &  _LC116;

-- Node name is '|COUNTER:U1|:17' = '|COUNTER:U1|TEMP0' 
-- Equation name is '_LC116', type is buried 
_LC116   = DFFE( _EQ010 $  GND, GLOBAL( CLK_IN),  VCC,  VCC,  VCC);
  _EQ010 =  EN_IN & !_LC113 & !_LC114 &  _LC115 & !_LC116 & !S_IN
         #  EN_IN & !_LC115 & !_LC116 & !S_IN
         #  EN_IN &  LOAD_IN0 &  S_IN
         # !EN_IN &  _LC116;

-- Node name is '|COUNTER:U1|:16' = '|COUNTER:U1|TEMP1' 
-- Equation name is '_LC113', type is buried 
_LC113   = DFFE( _EQ011 $  GND, GLOBAL( CLK_IN),  VCC,  VCC,  VCC);
  _EQ011 =  EN_IN &  _LC113 & !_LC115 & !_LC116 & !S_IN
         #  EN_IN & !_LC113 & !_LC115 &  _LC116 & !S_IN
         #  EN_IN &  LOAD_IN1 &  S_IN
         # !EN_IN &  _LC113;

-- Node name is '|COUNTER:U1|:15' = '|COUNTER:U1|TEMP2' 
-- Equation name is '_LC114', type is buried 
_LC114   = DFFE( _EQ012 $  GND, GLOBAL( CLK_IN),  VCC,  VCC,  VCC);
  _EQ012 =  EN_IN & !_LC113 & !_LC114 &  _LC115 & !_LC116 &  _LC117 & !S_IN
         #  EN_IN & !_LC115 &  _LC117 & !S_IN
         #  EN_IN &  LOAD_IN2 &  S_IN
         # !EN_IN &  _LC114;

-- Node name is '|COUNTER:U1|:14' = '|COUNTER:U1|TEMP3' 
-- Equation name is '_LC115', type is buried 
_LC115   = DFFE( _EQ013 $  GND, GLOBAL( CLK_IN),  VCC,  VCC,  VCC);
  _EQ013 =  EN_IN & !_LC113 & !_LC114 &  _LC115 & !_LC116 & !S_IN &  _X001
         #  EN_IN &  _LC113 &  _LC114 & !_LC115 &  _LC116 & !S_IN
         #  EN_IN &  LOAD_IN3 &  S_IN
         # !EN_IN &  _LC115;
  _X001  = EXP( _LC113 &  _LC114 &  _LC116);



--     Shareable expanders that are duplicated in multiple LABs:
--     (none)




Project Information                               c:\the road\counter\show.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Standard

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'MAX7000S' family

      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      PARALLEL_EXPANDERS                  = off
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SOFT_BUFFER_INSERTION               = on
      SUBFACTOR_EXTRACTION                = on
      TURBO_BIT                           = on
      XOR_SYNTHESIS                       = on
      IGNORE_SOFT_BUFFERS                 = off
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      One-Hot State Machine Encoding      = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = off

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:00
   Database Builder                       00:00:00
   Logic Synthesizer                      00:00:00
   Partitioner                            00:00:00
   Fitter                                 00:00:00
   Timing SNF Extractor                   00:00:00
   Assembler                              00:00:02
   --------------------------             --------
   Total Time                             00:00:02


Memory Allocated
-----------------

Peak memory allocated during compilation  = 5,115K