chooser.vhd

我们学校做VHDL实验的源码

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY CHOOSER IS
  PORT(A:IN STD_LOGIC_VECTOR(3 DOWNTO 0);
       S: IN STD_LOGIC_VECTOR(1 DOWNTO 0);
       P:OUT STD_LOGIC);
END ENTITY;
ARCHITECTURE BHV OF CHOOSER IS

   BEGIN
    P<=A(0) WHEN S="00" ELSE
       A(1) WHEN S="01" ELSE 
       A(2) WHEN S="10" ELSE
       A(3)  ;
 
END BHV;