coder.vhd

我们学校做VHDL实验的源码

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY CODER IS
  PORT(EN: IN STD_LOGIC;
        A:IN STD_LOGIC_VECTOR(6 DOWNTO 0);
        B:OUT STD_LOGIC_VECTOR(2 DOWNTO 0)
      );
END ENTITY;
ARCHITECTURE BHV OF CODER IS
 BEGIN
  PROCESS(EN,A)
  BEGIN
  IF(EN='1') THEN B<="111";
  ELSE CASE A IS 
       WHEN "0000001"=>B<="000";
       WHEN "0000010"=>B<="001";
       WHEN "0000100"=>B<="010";
       WHEN "0001000"=>B<="011";
       WHEN "0010000"=>B<="100";
       WHEN "0100000"=>B<="101";
       WHEN OTHERS=>B<="XXX";
       END CASE;
  END IF;
 END PROCESS;
END BHV;