comparator.vhd

我们学校做VHDL实验的源码

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY COMPARATOR IS
   PORT(A,B:IN STD_LOGIC_VECTOR(3 DOWNTO 0);
        DY,XY,QY:OUT STD_LOGIC);
END COMPARATOR;
ARCHITECTURE BHV OF COMPARATOR IS
BEGIN
  PROCESS(A,B)
  BEGIN
  IF(A>B) THEN DY<='1';
               XY<='0';
               QY<='0';
     ELSIF(A=B) THEN  DY<='0';
                     XY<='1';
                     QY<='0';
     ELSE DY<='0';
          XY<='0';
          QY<='1';
  END IF;
  END PROCESS;
END BHV;