bcd.rpt

我们学校做VHDL实验的源码


Device-Specific Information:                           c:\the road\bcd\bcd.rpt
bcd

** OUTPUTS **

                                         Shareable
                                         Expanders     Fan-In    Fan-Out
 Pin     LC  LAB  Primitive    Code   Total Shared n/a INP  FBK  OUT  FBK  Name
  81    128    H     OUTPUT      t        0      0   0    1    0    0    0  B0
  80    126    H     OUTPUT      t        0      0   0    3    0    0    0  B1
  79    125    H     OUTPUT      t        0      0   0    3    0    0    0  B2
  77    123    H     OUTPUT      t        0      0   0    3    1    0    0  B3
  76    120    H     OUTPUT      t        0      0   0    3    0    0    0  B4


Code:

s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell


Device-Specific Information:                           c:\the road\bcd\bcd.rpt
bcd

** BURIED LOGIC **

                                         Shareable
                                         Expanders     Fan-In    Fan-Out
 Pin     LC  LAB  Primitive    Code   Total Shared n/a INP  FBK  OUT  FBK  Name
   -    113    H       SOFT      t        0      0   0    3    0    1    0  |LPM_ADD_SUB:156|addcore:adder|addcore:adder0|gcp2


Code:

s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell


Device-Specific Information:                           c:\the road\bcd\bcd.rpt
bcd

** LOGIC CELL INTERCONNECTIONS **

Logic Array Block 'H':

                     Logic cells placed in LAB 'H'
        +----------- LC128 B0
        | +--------- LC126 B1
        | | +------- LC125 B2
        | | | +----- LC123 B3
        | | | | +--- LC120 B4
        | | | | | +- LC113 |LPM_ADD_SUB:156|addcore:adder|addcore:adder0|gcp2
        | | | | | | 
        | | | | | |   Other LABs fed by signals
        | | | | | |   that feed LAB 'H'
LC      | | | | | | | A B C D E F G H |     Logic cells that feed LAB 'H':
LC113-> - - - * - - | - - - - - - - * | <-- |LPM_ADD_SUB:156|addcore:adder|addcore:adder0|gcp2

Pin
31   -> * - - - - * | - - - - - - - * | <-- A0
33   -> - * * * * * | - - - - - - - * | <-- A1
34   -> - * * * * * | - - - - - - - * | <-- A2
35   -> - * * * * - | - - - - - - - * | <-- A3


* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).


Device-Specific Information:                           c:\the road\bcd\bcd.rpt
bcd

** EQUATIONS **

A0       : INPUT;
A1       : INPUT;
A2       : INPUT;
A3       : INPUT;

-- Node name is 'B0' 
-- Equation name is 'B0', location is LC128, type is output.
 B0      = LCELL( A0 $  GND);

-- Node name is 'B1' 
-- Equation name is 'B1', location is LC126, type is output.
 B1      = LCELL( _EQ001 $  A1);
  _EQ001 = !A1 &  A2 &  A3
         #  A1 &  A3;

-- Node name is 'B2' 
-- Equation name is 'B2', location is LC125, type is output.
 B2      = LCELL( _EQ002 $  A2);
  _EQ002 = !A1 &  A2 &  A3;

-- Node name is 'B3' 
-- Equation name is 'B3', location is LC123, type is output.
 B3      = LCELL( _EQ003 $  A3);
  _EQ003 =  A2 &  A3 &  _LC113
         #  A1 &  A3;

-- Node name is 'B4' 
-- Equation name is 'B4', location is LC120, type is output.
 B4      = LCELL( _EQ004 $  A3);
  _EQ004 = !A1 & !A2 &  A3;

-- Node name is '|LPM_ADD_SUB:156|addcore:adder|addcore:adder0|gcp2' from file "addcore.tdf" line 160, column 8
-- Equation name is '_LC113', type is buried 
_LC113   = LCELL( _EQ005 $  A2);
  _EQ005 =  A0 &  A1 & !A2;



--     Shareable expanders that are duplicated in multiple LABs:
--     (none)




Project Information                                    c:\the road\bcd\bcd.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Standard

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'MAX7000S' family

      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      PARALLEL_EXPANDERS                  = off
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SOFT_BUFFER_INSERTION               = on
      SUBFACTOR_EXTRACTION                = on
      TURBO_BIT                           = on
      XOR_SYNTHESIS                       = on
      IGNORE_SOFT_BUFFERS                 = off
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      One-Hot State Machine Encoding      = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = off

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:00
   Database Builder                       00:00:00
   Logic Synthesizer                      00:00:00
   Partitioner                            00:00:00
   Fitter                                 00:00:01
   Timing SNF Extractor                   00:00:00
   Assembler                              00:00:01
   --------------------------             --------
   Total Time                             00:00:02


Memory Allocated
-----------------

Peak memory allocated during compilation  = 4,247K