bcd.vhd

我们学校做VHDL实验的源码

                                                                                                                                                                                                                               LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY BCD IS
 PORT( A:IN STD_LOGIC_VECTOR(3 DOWNTO 0);
       B:OUT STD_LOGIC_VECTOR(4 DOWNTO 0)
      );
END BCD;
ARCHITECTURE BHV OF BCD IS
   BEGIN 
    PROCESS(A)
      BEGIN
        IF(A<"1010") THEN B(3 DOWNTO 0)<=A;
                        B(4)<='0';
        ELSE B(3 DOWNTO 0)<=(A-"1010");
                       B(4)<='1';
      END IF;
     END PROCESS;
END BHV;