vtopgen.pl

【原创】生成各个子模块verilog文件的顶层文件

#!/exec/local/bin/perl
#############################################################################
#
#  Copyright (c) 2006 DICDER
#  DICDER Scripts Share Group(DSSG)
#
#  PROJECT     : 
#  ENGINEER    :    [e-mail]
#  DESCRIPTION :
#
#  Generate the top file of verilog module.  
#
#############################################################################
                                                                                                               
###### PACKAGES ######
use Getopt::Std;
 
## ------------
## Subroutines declarations
## ------------
use subs qw( PrintHeader(),ParseCommand(),Convert(),Convert_onefile(),PrintTailer() );
 
## -----------
## Variable declarations
## -----------
 
 
###### ARGUMENTS ######
getopts('l:f:t: h');
 
###### Command Options ###
ParseCommand();
 
###### Print Starting ####
PrintHeader();
 
## ------------
## Convert routine
## ------------
Convert();
 
## -----------
## Print End 
## -----------
PrintTailer();
 
exit(0);
## ------------
## End main program
## ------------
 
sub PrintHeader(){
 
   print  "--------------------------- \n";
   print  " Start Translating ........ \n";
   print  "--------------------------- \n";
 
}
 
sub ParseCommand(){
    ###### HELP ######
        if ($opt_h)
        {
                system ("perldoc $0");
                exit(0);
        }
        if (!$opt_l && !$opt_f)
        {
                printf STDERR ("ERROR: no list file and filename specified \n");
                printf STDERR ("Try typing $0 -h for some help \n\n");
                exit 1;
        }
 
        if ($opt_l && $opt_f )
        {
                printf STDERR ("ERROR: Only one of filename and list file can be specified \n");
                printf STDERR ("Try typing $0 -h for some help \n\n");
                exit 1;
        }
        ############ Filelist ########
        if ($opt_l)
        {
                $file_list ="$opt_l";
        }
 
        if ($opt_f)
        {
                $file_name ="$opt_f";
        }
}
 
sub Convert(){
 
   ## ---------------
   ## List file program
   ## ---------------
 
   open( fplist,"$file_list");
   @file = <fplist>;
   chomp(@file);
   close(fplist);
   
   #open(TMP_FILE1,">tmp1.v");
   if($opt_l){
     $creatf = 1;
     foreach $file (@file){
       Convert_onefile($file);
       $creatf = 0;
     }
   }
   ## ---------------
   ## One file program
   ## ---------------
   # Only the filename option is defined , 
   # Running the routines
   if($opt_f){
     Convert_onefile($file_name);
   }
   #close(TMP_FILE1);
      
   open(TMP_FILE,"tmp.v");
   open(TMP_FILE1,">top.v");
 
#inout
   $i=0;
   while (($key, $value) = each %wires){
        if($value>3){
            @arrtmp0[$i] = $key;  
            $i++;
        }   
   }   
   @arrtmp0 = sort @arrtmp0;
#output
   $i=0;
   while (($key, $value) = each %wires){
        if($value==2){
            @arrtmp1[$i] = $key;  
            $i++;
        }   
   }   
   @arrtmp1 = sort @arrtmp1;
#input
   $i=0;
   while (($key, $value) = each %wires){
        if($value==1){
            @arrtmp2[$i] = $key;  
            $i++;
        }   
   }   
   @arrtmp2 = sort @arrtmp2;
##############################################################   
   print TMP_FILE1 "module top(\n";
   $itmp=0;
   while(@arrtmp0[$itmp]){
        $tmp = @arrtmp0[$itmp];
        $tmp =~ s/\[.*\]//;
        print TMP_FILE1 "    $tmp,\n";  
        $itmp++;  
   }
   $itmp=0;
   while(@arrtmp1[$itmp]){
        $tmp = @arrtmp1[$itmp];
        $tmp =~ s/\[.*\]//;
        print TMP_FILE1 "    $tmp,\n";  
        $itmp++;     
   }
   $itmp=0;
   while(@arrtmp2[$itmp]){
        $tmp = @arrtmp2[$itmp];
        $tmp =~ s/\[.*\]//;
        if($itmp==$#arrtmp2)
            {print TMP_FILE1 "    $tmp\n";}
        else
            {print TMP_FILE1 "    $tmp,\n";}  
        $itmp++;    
   }
   print TMP_FILE1 ");\n";
#######################################################   
   $itmp=0;
   while(@arrtmp0[$itmp]){
        print TMP_FILE1 "inout @arrtmp0[$itmp];\n";  
        $itmp++;  
   }
   print TMP_FILE1 "\n";
   $itmp=0;
   while(@arrtmp1[$itmp]){
        print TMP_FILE1 "output @arrtmp1[$itmp];\n"; 
        $itmp++;    
   }
   print TMP_FILE1 "\n";
   $itmp=0;
   while(@arrtmp2[$itmp]){
        print TMP_FILE1 "input @arrtmp2[$itmp];\n"; 
        $itmp++;    
   }
   print TMP_FILE1 "\n";
   #wire
   $i=0;
   while (($key, $value) = each %wires){
        if($value==3){
            @arrtmp[$i] = $key;  
            $i++;
        }   
   }   
   @arrtmp = sort @arrtmp;
   
   for($itmp = 0; $itmp < $i;$itmp++){
        print TMP_FILE1 "wire @arrtmp[$itmp];\n";  
   }        
   print TMP_FILE1 "\n";
####################################################   
   while(<TMP_FILE>){
        print TMP_FILE1 $_;
   }
   print TMP_FILE1 "\nendmodule\n"; 
   
   close(TMP_FILE);
   close(TMP_FILE1);
   system("del tmp.v");
}
 
 
sub Convert_onefile(){
 
    open(fpfile,"$_[0]");
    if($creatf){
        open(TMP_FILE,">tmp.v");
    }
    else {
        open(TMP_FILE,">>tmp.v");
    }
    
    # ------------
    # Begins to covert tab in a single file
    # ------------
    print " Convertion Processing @ File : $_[0] ... \n";
 
    $lines = join '', <fpfile>;
    
    $lines =~ s#\/\/.*\n#\n#gm;
    $lines =~ s#^(\s*)\n##gm;
    $lines =~ s#\/\*(.|\n)*?(\*\/)+?##gm;    
    $linesbak = $lines;
    $lines =~ s#\bmodule\b(.*)\(+?((.|\n)*?)(\)+?)(\s|\n)*;##gm;
    $lines =  $2;
    $modulename = $1;
    $modulename =~ s/\s//gm;
    $lines =~ s#(\s)+# #gm;
    @signals = split /,/,$lines;
    
#    $_=$linesbak;
    close(fpfile);
    open(fpfile,"$_[0]");
    while(<fpfile>)
    {
        if(/(\binput\b|\boutput\b|\binout\b)+(.*?)(;|,|\n)+?/gm)
        {
            $siglist = $2;
            $iotype = $1;
            $siglist =~ s/\breg\b//gm;
            $siglist =~ s/\s//gm;
            
            if($iotype  eq "input"){
                $wires{$siglist} = $wires{$siglist}|1;
            }
            elsif($iotype eq "output"){
                $wires{$siglist} = $wires{$siglist}|2;
            }
            else{
                $wires{$siglist} = $wires{$siglist}|4;
            }    
        }
    }    
    
    $i =0;
    print TMP_FILE "$modulename $modulename\_u0(\n";
    while($i<$#signals+1)
    {
        $_ = @signals[$i];
        $_ =~ s/\binput\b|\boutput\b|\binout\b|\breg\b|\[.*\]//g;
        $_ =~ s/\s*//gm;
        if($i == $#signals){
            print TMP_FILE "    .$_($_));\n";
        }
        else {
            print TMP_FILE "    .$_($_),\n";    
        }
        $i++;
    }         
    close(TMP_FILE);
    close(fpfile); 
}
 
sub PrintTailer(){ 
 
     print "--------------------------------- \n";
     print "SUCCESSFUL for Converting !       \n";
}