📄 fp_n.rpt
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fp_n
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 2 - A 23 AND2 0 2 0 1 |lpm_add_sub:75|addcore:adder|:55
- 4 - A 18 AND2 0 3 0 1 |lpm_add_sub:77|addcore:adder|:59
- 3 - A 23 OR2 s 2 2 0 1 ~10~1
- 1 - A 23 OR2 1 3 0 3 :10
- 5 - A 18 OR2 ! 0 4 0 3 :20
- 6 - A 18 OR2 0 4 0 1 :42
- 7 - A 18 OR2 s 0 2 0 2 ~44~1
- 3 - A 18 DFFE + 1 1 0 3 a3 (:59)
- 1 - A 18 DFFE + 1 2 0 3 a2 (:60)
- 2 - A 18 DFFE + 1 2 0 4 a1 (:61)
- 8 - A 23 DFFE + 1 0 0 5 a0 (:62)
- 8 - A 18 DFFE + 1 2 1 0 :74
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
p = Packed register
Device-Specific Information: d:\2fsk\fp_n.rpt
fp_n
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 6/ 96( 6%) 0/ 48( 0%) 1/ 48( 2%) 0/16( 0%) 1/16( 6%) 0/16( 0%)
B: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
C: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: d:\2fsk\fp_n.rpt
fp_n
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 5 clk
Device-Specific Information: d:\2fsk\fp_n.rpt
fp_n
** EQUATIONS **
clk : INPUT;
n1 : INPUT;
n2 : INPUT;
n3 : INPUT;
reset : INPUT;
-- Node name is ':62' = 'a0'
-- Equation name is 'a0', location is LC8_A23, type is buried.
a0 = DFFE( _EQ001, GLOBAL( clk), VCC, VCC, VCC);
_EQ001 = a0 & reset
# !a0 & !reset;
-- Node name is ':61' = 'a1'
-- Equation name is 'a1', location is LC2_A18, type is buried.
a1 = DFFE( _EQ002, GLOBAL( clk), VCC, VCC, VCC);
_EQ002 = a0 & !a1 & _LC7_A18 & !reset
# !a0 & a1 & _LC7_A18
# a1 & reset;
-- Node name is ':60' = 'a2'
-- Equation name is 'a2', location is LC1_A18, type is buried.
a2 = DFFE( _EQ003, GLOBAL( clk), VCC, VCC, VCC);
_EQ003 = a2 & !_LC2_A23 & _LC7_A18
# !a2 & _LC2_A23 & _LC7_A18 & !reset
# a2 & reset;
-- Node name is ':59' = 'a3'
-- Equation name is 'a3', location is LC3_A18, type is buried.
a3 = DFFE( _EQ004, GLOBAL( clk), VCC, VCC, VCC);
_EQ004 = _LC6_A18 & !reset
# a3 & reset;
-- Node name is 'clkout'
-- Equation name is 'clkout', type is output
clkout = _LC8_A18;
-- Node name is '|lpm_add_sub:75|addcore:adder|:55' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC2_A23', type is buried
_LC2_A23 = LCELL( _EQ005);
_EQ005 = a0 & a1;
-- Node name is '|lpm_add_sub:77|addcore:adder|:59' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC4_A18', type is buried
_LC4_A18 = LCELL( _EQ006);
_EQ006 = a0 & a1 & a2;
-- Node name is '~10~1'
-- Equation name is '~10~1', location is LC3_A23, type is buried.
-- synthesized logic cell
_LC3_A23 = LCELL( _EQ007);
_EQ007 = a0 & a2 & n1 & n3
# !a0 & a2 & !n1 & n3
# a0 & !a2 & n1 & !n3
# !a0 & !a2 & !n1 & !n3;
-- Node name is ':10'
-- Equation name is '_LC1_A23', type is buried
_LC1_A23 = LCELL( _EQ008);
_EQ008 = a1 & !a3 & _LC3_A23 & n2
# !a1 & !a3 & _LC3_A23 & !n2;
-- Node name is ':20'
-- Equation name is '_LC5_A18', type is buried
!_LC5_A18 = _LC5_A18~NOT;
_LC5_A18~NOT = LCELL( _EQ009);
_EQ009 = a3
# a1
# a0
# a2;
-- Node name is ':42'
-- Equation name is '_LC6_A18', type is buried
_LC6_A18 = LCELL( _EQ010);
_EQ010 = _LC1_A23 & _LC4_A18
# a3 & !_LC1_A23 & !_LC4_A18 & !_LC5_A18
# !a3 & _LC4_A18 & !_LC5_A18;
-- Node name is '~44~1'
-- Equation name is '~44~1', location is LC7_A18, type is buried.
-- synthesized logic cell
_LC7_A18 = LCELL( _EQ011);
_EQ011 = !_LC5_A18
# _LC1_A23;
-- Node name is ':74'
-- Equation name is '_LC8_A18', type is buried
_LC8_A18 = DFFE( _EQ012, GLOBAL( clk), VCC, VCC, VCC);
_EQ012 = _LC1_A23 & !_LC8_A18 & !reset
# !_LC1_A23 & !_LC5_A18 & _LC8_A18 & !reset
# _LC5_A18 & !_LC8_A18 & !reset;
Project Information d:\2fsk\fp_n.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'ACEX1K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = on
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:00
Fitter 00:00:01
Timing SNF Extractor 00:00:00
Assembler 00:00:00
-------------------------- --------
Total Time 00:00:01
Memory Allocated
-----------------
Peak memory allocated during compilation = 16,087K
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