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📄 counter.rpt

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💻 RPT
📖 第 1 页 / 共 3 页
字号:
  82      -     -    -    04     OUTPUT                 0    1    0    0  out9
  63      -     -    B    --     OUTPUT                 0    1    0    0  out10
  64      -     -    B    --     OUTPUT                 0    1    0    0  out11
  45      -     -    -    11     OUTPUT                 0    1    0    0  out12
  87      -     -    -    12     OUTPUT                 0    1    0    0  out13
  62      -     -    B    --     OUTPUT                 0    1    0    0  out14
  57      -     -    C    --     OUTPUT                 0    1    0    0  out15


Code:

s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable


Device-Specific Information:                               d:\2fsk\counter.rpt
counter

** BURIED LOGIC **

                                                    Fan-In    Fan-Out
 IOC     LC     EC   Row  Col  Primitive    Code      INP  FBK  OUT  FBK  Name
   -      4     -    A    07        OR2                0    2    0    1  |lpm_add_sub:132|addcore:adder|pcarry1
   -      6     -    A    07        OR2                0    3    0    1  |lpm_add_sub:132|addcore:adder|pcarry2
   -      2     -    A    07        OR2                0    4    0    4  |lpm_add_sub:132|addcore:adder|pcarry3
   -      3     -    B    05        OR2                0    2    0    1  |lpm_add_sub:132|addcore:adder|pcarry4
   -      1     -    B    05        OR2                0    3    0    1  |lpm_add_sub:132|addcore:adder|pcarry5
   -      2     -    B    03        OR2                0    4    0    4  |lpm_add_sub:132|addcore:adder|pcarry6
   -      4     -    B    03        OR2                0    2    0    1  |lpm_add_sub:132|addcore:adder|pcarry7
   -      7     -    B    03        OR2                0    3    0    1  |lpm_add_sub:132|addcore:adder|pcarry8
   -      8     -    B    03        OR2                0    4    0    4  |lpm_add_sub:132|addcore:adder|pcarry9
   -      5     -    B    05        OR2                0    2    0    1  |lpm_add_sub:132|addcore:adder|pcarry10
   -      7     -    B    05        OR2                0    3    0    1  |lpm_add_sub:132|addcore:adder|pcarry11
   -      5     -    B    12        OR2                0    4    0    4  |lpm_add_sub:132|addcore:adder|pcarry12
   -      7     -    B    12        OR2                0    2    0    1  |lpm_add_sub:132|addcore:adder|pcarry13
   -      8     -    B    12        OR2                0    3    0    1  |lpm_add_sub:132|addcore:adder|pcarry14
   -      2     -    B    12       DFFE   +            2    1    1    1  :88
   -      6     -    B    12       DFFE   +            2    1    1    2  :89
   -      1     -    B    12       DFFE   +            2    1    1    3  :90
   -      3     -    B    12       DFFE   +            2    1    1    1  :91
   -      2     -    B    05       DFFE   +            2    1    1    2  :92
   -      4     -    B    05       DFFE   +            2    1    1    3  :93
   -      1     -    B    03       DFFE   +            2    1    1    1  :94
   -      3     -    B    03       DFFE   +            2    1    1    2  :95
   -      6     -    B    03       DFFE   +            2    1    1    3  :96
   -      5     -    B    03       DFFE   +            2    1    1    1  :97
   -      8     -    B    05       DFFE   +            2    1    1    2  :98
   -      8     -    A    07       DFFE   +            2    1    1    3  :99
   -      7     -    A    07       DFFE   +            2    1    1    1  :100
   -      5     -    A    07       DFFE   +            2    1    1    2  :101
   -      3     -    A    07       DFFE   +            2    1    1    3  :102
   -      1     -    A    07       DFFE   +            2    0    1    4  :103
   -      4     -    B    12       AND2                0    4    1    0  :104


Code:

s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
p = Packed register


Device-Specific Information:                               d:\2fsk\counter.rpt
counter

** FASTTRACK INTERCONNECT UTILIZATION **

Row FastTrack Interconnect:

          Global         Left Half-      Right Half-
         FastTrack       FastTrack       FastTrack 
Row     Interconnect    Interconnect    Interconnect    Input Pins     Output Pins     Bidir Pins
A:       2/ 96(  2%)     4/ 48(  8%)     0/ 48(  0%)    2/16( 12%)      4/16( 25%)     0/16(  0%)
B:      12/ 96( 12%)    10/ 48( 20%)     0/ 48(  0%)    4/16( 25%)      5/16( 31%)     0/16(  0%)
C:       0/ 96(  0%)     1/ 48(  2%)     0/ 48(  0%)    0/16(  0%)      1/16(  6%)     0/16(  0%)


Column FastTrack Interconnect:

         FastTrack                                 
Column  Interconnect    Input Pins     Output Pins     Bidir Pins
01:      2/24(  8%)     2/4( 50%)      0/4(  0%)       0/4(  0%)
02:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
03:      2/24(  8%)     0/4(  0%)      2/4( 50%)       0/4(  0%)
04:      1/24(  4%)     0/4(  0%)      1/4( 25%)       0/4(  0%)
05:      1/24(  4%)     1/4( 25%)      0/4(  0%)       0/4(  0%)
06:      1/24(  4%)     1/4( 25%)      0/4(  0%)       0/4(  0%)
07:      1/24(  4%)     1/4( 25%)      0/4(  0%)       0/4(  0%)
08:      2/24(  8%)     0/4(  0%)      1/4( 25%)       0/4(  0%)
09:      1/24(  4%)     1/4( 25%)      0/4(  0%)       0/4(  0%)
10:      1/24(  4%)     1/4( 25%)      0/4(  0%)       0/4(  0%)
11:      2/24(  8%)     0/4(  0%)      1/4( 25%)       0/4(  0%)
12:      2/24(  8%)     0/4(  0%)      2/4( 50%)       0/4(  0%)
13:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
14:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
15:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
16:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
17:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
18:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
19:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
20:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
21:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
22:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
23:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
24:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
EA:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)


Device-Specific Information:                               d:\2fsk\counter.rpt
counter

** CLOCK SIGNALS **

Type     Fan-out       Name
INPUT       16         clk


Device-Specific Information:                               d:\2fsk\counter.rpt
counter

** CLEAR SIGNALS **

Type     Fan-out       Name
INPUT       16         clr


Device-Specific Information:                               d:\2fsk\counter.rpt
counter

** EQUATIONS **

clk      : INPUT;
clr      : INPUT;
data0    : INPUT;
data1    : INPUT;
data2    : INPUT;
data3    : INPUT;
data4    : INPUT;
data5    : INPUT;
data6    : INPUT;
data7    : INPUT;
data8    : INPUT;
data9    : INPUT;
data10   : INPUT;
data11   : INPUT;
data12   : INPUT;
data13   : INPUT;
data14   : INPUT;
data15   : INPUT;
load     : INPUT;

-- Node name is 'B0' 
-- Equation name is 'B0', type is output 
B0       =  _LC4_B12;

-- Node name is 'out0' 
-- Equation name is 'out0', type is output 
out0     =  _LC1_A7;

-- Node name is 'out1' 
-- Equation name is 'out1', type is output 
out1     =  _LC3_A7;

-- Node name is 'out2' 
-- Equation name is 'out2', type is output 
out2     =  _LC5_A7;

-- Node name is 'out3' 
-- Equation name is 'out3', type is output 
out3     =  _LC7_A7;

-- Node name is 'out4' 
-- Equation name is 'out4', type is output 
out4     =  _LC8_A7;

-- Node name is 'out5' 
-- Equation name is 'out5', type is output 
out5     =  _LC8_B5;

-- Node name is 'out6' 
-- Equation name is 'out6', type is output 
out6     =  _LC5_B3;

-- Node name is 'out7' 
-- Equation name is 'out7', type is output 
out7     =  _LC6_B3;

-- Node name is 'out8' 
-- Equation name is 'out8', type is output 
out8     =  _LC3_B3;

-- Node name is 'out9' 
-- Equation name is 'out9', type is output 
out9     =  _LC1_B3;

-- Node name is 'out10' 
-- Equation name is 'out10', type is output 
out10    =  _LC4_B5;

-- Node name is 'out11' 
-- Equation name is 'out11', type is output 
out11    =  _LC2_B5;

-- Node name is 'out12' 
-- Equation name is 'out12', type is output 
out12    =  _LC3_B12;

-- Node name is 'out13' 
-- Equation name is 'out13', type is output 
out13    =  _LC1_B12;

-- Node name is 'out14' 
-- Equation name is 'out14', type is output 
out14    =  _LC6_B12;

-- Node name is 'out15' 
-- Equation name is 'out15', type is output 
out15    =  _LC2_B12;

-- Node name is '|lpm_add_sub:132|addcore:adder|pcarry1' from file "addcore.tdf" line 312, column 40
-- Equation name is '_LC4_A7', type is buried 
_LC4_A7  = LCELL( _EQ001);
  _EQ001 =  _LC3_A7
         #  _LC1_A7;

-- Node name is '|lpm_add_sub:132|addcore:adder|pcarry2' from file "addcore.tdf" line 312, column 40
-- Equation name is '_LC6_A7', type is buried 
_LC6_A7  = LCELL( _EQ002);
  _EQ002 =  _LC3_A7
         #  _LC1_A7
         #  _LC5_A7;

-- Node name is '|lpm_add_sub:132|addcore:adder|pcarry3' from file "addcore.tdf" line 312, column 40
-- Equation name is '_LC2_A7', type is buried 
_LC2_A7  = LCELL( _EQ003);
  _EQ003 =  _LC3_A7
         #  _LC1_A7
         #  _LC5_A7
         #  _LC7_A7;

-- Node name is '|lpm_add_sub:132|addcore:adder|pcarry4' from file "addcore.tdf" line 312, column 40
-- Equation name is '_LC3_B5', type is buried 
_LC3_B5  = LCELL( _EQ004);
  _EQ004 =  _LC8_A7
         #  _LC2_A7;

-- Node name is '|lpm_add_sub:132|addcore:adder|pcarry5' from file "addcore.tdf" line 312, column 40
-- Equation name is '_LC1_B5', type is buried 
_LC1_B5  = LCELL( _EQ005);
  _EQ005 =  _LC8_A7
         #  _LC2_A7
         #  _LC8_B5;

-- Node name is '|lpm_add_sub:132|addcore:adder|pcarry6' from file "addcore.tdf" line 312, column 40
-- Equation name is '_LC2_B3', type is buried 
_LC2_B3  = LCELL( _EQ006);
  _EQ006 =  _LC8_A7

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