📄 bijiao.rpt
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Device-Specific Information: d:\2fsk\bijiao.rpt
bijiao
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 7 - C 19 OR2 2 1 0 1 :24
- 6 - C 19 OR2 2 1 0 1 :29
- 5 - C 19 OR2 2 1 0 1 :34
- 4 - C 19 OR2 2 1 0 1 :39
- 3 - C 19 OR2 2 1 0 1 :44
- 1 - C 19 OR2 4 0 0 1 :49
- 2 - C 19 DFFE + 2 1 1 0 :60
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
p = Packed register
Device-Specific Information: d:\2fsk\bijiao.rpt
bijiao
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
B: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
C: 9/ 96( 9%) 0/ 48( 0%) 3/ 48( 6%) 8/16( 50%) 1/16( 6%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: d:\2fsk\bijiao.rpt
bijiao
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 1 clk
Device-Specific Information: d:\2fsk\bijiao.rpt
bijiao
** EQUATIONS **
a0 : INPUT;
a1 : INPUT;
a2 : INPUT;
a3 : INPUT;
a4 : INPUT;
a5 : INPUT;
a6 : INPUT;
a7 : INPUT;
b0 : INPUT;
b1 : INPUT;
b2 : INPUT;
b3 : INPUT;
b4 : INPUT;
b5 : INPUT;
b6 : INPUT;
b7 : INPUT;
clk : INPUT;
-- Node name is 'out'
-- Equation name is 'out', type is output
out = _LC2_C19;
-- Node name is ':24'
-- Equation name is '_LC7_C19', type is buried
_LC7_C19 = LCELL( _EQ001);
_EQ001 = a6 & _LC6_C19
# !b6 & _LC6_C19
# a6 & !b6;
-- Node name is ':29'
-- Equation name is '_LC6_C19', type is buried
_LC6_C19 = LCELL( _EQ002);
_EQ002 = a5 & _LC5_C19
# !b5 & _LC5_C19
# a5 & !b5;
-- Node name is ':34'
-- Equation name is '_LC5_C19', type is buried
_LC5_C19 = LCELL( _EQ003);
_EQ003 = a4 & _LC4_C19
# !b4 & _LC4_C19
# a4 & !b4;
-- Node name is ':39'
-- Equation name is '_LC4_C19', type is buried
_LC4_C19 = LCELL( _EQ004);
_EQ004 = a3 & _LC3_C19
# !b3 & _LC3_C19
# a3 & !b3;
-- Node name is ':44'
-- Equation name is '_LC3_C19', type is buried
_LC3_C19 = LCELL( _EQ005);
_EQ005 = a2 & _LC1_C19
# !b2 & _LC1_C19
# a2 & !b2;
-- Node name is ':49'
-- Equation name is '_LC1_C19', type is buried
_LC1_C19 = LCELL( _EQ006);
_EQ006 = a1 & !b1
# a0 & a1 & !b0
# a0 & !b0 & !b1;
-- Node name is ':60'
-- Equation name is '_LC2_C19', type is buried
_LC2_C19 = DFFE( _EQ007, GLOBAL( clk), VCC, VCC, VCC);
_EQ007 = a7 & _LC7_C19
# !b7 & _LC7_C19
# a7 & !b7;
Project Information d:\2fsk\bijiao.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'ACEX1K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = on
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:00
Fitter 00:00:01
Timing SNF Extractor 00:00:00
Assembler 00:00:00
-------------------------- --------
Total Time 00:00:01
Memory Allocated
-----------------
Peak memory allocated during compilation = 16,849K
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